397 lines
13 KiB
C
397 lines
13 KiB
C
#define RADEON_SCRATCH_REG0 0x15e0
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#define RADEON_SCRATCH_REG1 0x15e4
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#define RADEON_SCRATCH_REG2 0x15e8
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#define RADEON_SCRATCH_REG3 0x15ec
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#define RADEON_SCRATCH_REG4 0x15f0
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#define RADEON_SCRATCH_REG5 0x15f4
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#define RADEON_SCRATCH_UMSK 0x0770
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#define RADEON_SCRATCH_ADDR 0x0774
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# define RS400_BUS_MASTER_DIS (1 << 14)
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//# define RADEON_BUS_MASTER_DIS (1 << 6)
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#define RADEON_ISYNC_CNTL 0x1724
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# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
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# define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
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# define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
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# define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
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# define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
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# define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
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#define RADEON_IDLE_RETRY 16 /* Fall out of idle loops after this count */
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#define RADEON_TIMEOUT 4000000 /* Fall out of wait loops after this count */
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void RADEONEngineFlush(RHDPtr info)
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{
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int i;
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if (info->ChipFamily <= CHIP_FAMILY_RV280)
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{
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MASKREG(RADEON_RB3D_DSTCACHE_CTLSTAT,RADEON_RB3D_DC_FLUSH_ALL,
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~RADEON_RB3D_DC_FLUSH_ALL);
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for (i = 0; i < RADEON_TIMEOUT; i++) {
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if (!(INREG(RADEON_RB3D_DSTCACHE_CTLSTAT) & RADEON_RB3D_DC_BUSY))
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break;
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}
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if (i == RADEON_TIMEOUT) {
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dbgprintf("DC flush timeout: %x\n",
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(u32_t)INREG(RADEON_RB3D_DSTCACHE_CTLSTAT));
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}
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}
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else
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{
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// MASKREG(R300_DSTCACHE_CTLSTAT,R300_RB2D_DC_FLUSH_ALL,
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// ~R300_RB2D_DC_FLUSH_ALL);
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// for (i = 0; i < RADEON_TIMEOUT; i++) {
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// if (!(INREG(R300_DSTCACHE_CTLSTAT) & R300_RB2D_DC_BUSY))
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// break;
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// }
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// if (i == RADEON_TIMEOUT) {
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// dbgprintf("DC flush timeout: %x\n",
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// (u32_t)INREG(R300_DSTCACHE_CTLSTAT));
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// }
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}
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}
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static Bool R5xxFIFOWaitLocal(u32_t required) //R100-R500
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{
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int i;
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for (i = 0; i < RADEON_TIMEOUT; i++)
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if (required <= (INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK))
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return TRUE;
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dbgprintf("%s: Timeout 0x%08X.\n", __func__, (u32_t) INREG(RADEON_RBBM_STATUS));
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return FALSE;
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}
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static int radeon_do_wait_for_idle()
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{
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int i, ret;
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ret = R5xxFIFOWaitLocal(64);
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if (ret)
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return ret;
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for (i = 0; i < RADEON_TIMEOUT; i++)
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{
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if (!(INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)) {
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RADEONEngineFlush(&rhd);
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return 0;
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}
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usleep(1);
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}
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dbgprintf("wait idle failed status : 0x%08X 0x%08X\n",
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INREG(RADEON_RBBM_STATUS),
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INREG(R300_VAP_CNTL_STATUS));
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return 1;
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}
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/* ================================================================
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* CP control, initialization
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*/
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/* Load the microcode for the CP */
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#include "radeon_microcode.h"
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static void load_microcode(RHDPtr info)
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{
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int i;
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const u32_t (*microcode)[2];
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OUTREG(RADEON_CP_ME_RAM_ADDR, 0);
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if ( (info->ChipFamily == CHIP_FAMILY_LEGACY ) ||
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(info->ChipFamily == CHIP_FAMILY_RADEON ) ||
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(info->ChipFamily == CHIP_FAMILY_RV100 ) ||
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(info->ChipFamily == CHIP_FAMILY_RV200 ) ||
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(info->ChipFamily == CHIP_FAMILY_RS100 ) ||
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(info->ChipFamily == CHIP_FAMILY_RS200 ))
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{
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microcode = R100_cp_microcode;
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dbgprintf("Loading R100 Microcode\n");
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}
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else if ((info->ChipFamily == CHIP_FAMILY_R200 ) ||
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(info->ChipFamily == CHIP_FAMILY_RV250) ||
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(info->ChipFamily == CHIP_FAMILY_RV280) ||
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(info->ChipFamily == CHIP_FAMILY_RS300))
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{
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microcode = R200_cp_microcode;
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dbgprintf("Loading R200 Microcode\n");
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}
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else if ((info->ChipFamily == CHIP_FAMILY_R300) ||
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(info->ChipFamily == CHIP_FAMILY_R350) ||
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(info->ChipFamily == CHIP_FAMILY_RV350) ||
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(info->ChipFamily == CHIP_FAMILY_RV380) ||
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(info->ChipFamily == CHIP_FAMILY_RS400) ||
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(info->ChipFamily == CHIP_FAMILY_RS480))
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{
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dbgprintf("Loading R300 Microcode\n");
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microcode = R300_cp_microcode;
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}
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else if ((info->ChipFamily == CHIP_FAMILY_R420) ||
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(info->ChipFamily == CHIP_FAMILY_RV410))
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{
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dbgprintf("Loading R400 Microcode\n");
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microcode = R420_cp_microcode;
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}
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else if ((info->ChipFamily == CHIP_FAMILY_RS600) ||
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(info->ChipFamily == CHIP_FAMILY_RS690) ||
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(info->ChipFamily == CHIP_FAMILY_RS740))
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{
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dbgprintf("Loading RS690/RS740 Microcode\n");
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microcode = RS690_cp_microcode;
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}
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else if ((info->ChipFamily == CHIP_FAMILY_RV515) ||
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(info->ChipFamily == CHIP_FAMILY_R520) ||
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(info->ChipFamily == CHIP_FAMILY_RV530) ||
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(info->ChipFamily == CHIP_FAMILY_R580) ||
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(info->ChipFamily == CHIP_FAMILY_RV560) ||
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(info->ChipFamily == CHIP_FAMILY_RV570))
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{
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dbgprintf("Loading R500 Microcode\n");
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microcode = R520_cp_microcode;
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}
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for (i = 0; i < 256; i++) {
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OUTREG(RADEON_CP_ME_RAM_DATAH, microcode[i][1]);
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OUTREG(RADEON_CP_ME_RAM_DATAL, microcode[i][0]);
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}
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}
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void init_ring_buffer(RHDPtr info)
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{
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u32_t ring_base;
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u32_t tmp;
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info->ringBase = CreateRingBuffer( 64*1024, PG_SW);
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dbgprintf("create cp ring buffer %x\n", rhd.ringBase);
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ring_base = GetPgAddr(rhd.ringBase);
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dbgprintf("ring base %x\n", ring_base);
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OUTREG(RADEON_CP_RB_BASE, ring_base);
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info->ring_avail = 64*1024/4 ;
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/* Set the write pointer delay */
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OUTREG(RADEON_CP_RB_WPTR_DELAY, 0);
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/* Initialize the ring buffer's read and write pointers */
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rhd.ring_rp = rhd.ring_wp = INREG(RADEON_CP_RB_RPTR);
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rhd.host_rp = rhd.ring_rp;
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OUTREG(RADEON_CP_RB_WPTR,rhd.ring_rp);
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tmp = (((u32_t)&rhd.host_rp) & 4095) + GetPgAddr((void*)&rhd.host_rp);
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OUTREG(RADEON_CP_RB_RPTR_ADDR, tmp); // ring buffer read pointer
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/* Set ring buffer size */
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OUTREG(RADEON_CP_RB_CNTL, (1<<27)|(0<<18)|(10<<8)|13);
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/* Initialize the scratch register pointer. This will cause
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* the scratch register values to be written out to memory
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* whenever they are updated.
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*
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* We simply put this behind the ring read pointer, this works
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* with PCI GART as well as (whatever kind of) AGP GART
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*/
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tmp = (((u32_t)&rhd.scratch0) & 4095) + GetPgAddr((void*)&rhd.scratch0);
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OUTREG(RADEON_SCRATCH_ADDR, tmp);
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OUTREG(RADEON_SCRATCH_UMSK, 0x0);
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//OUTREG(0x778, 1);
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/* Turn on bus mastering */
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if ( (info->ChipFamily == CHIP_FAMILY_RS400) ||
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(info->ChipFamily == CHIP_FAMILY_RS690) ||
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(info->ChipFamily == CHIP_FAMILY_RS740) )
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{
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/* rs400, rs690/rs740 */
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tmp = INREG(RADEON_BUS_CNTL) & ~RS400_BUS_MASTER_DIS;
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OUTREG(RADEON_BUS_CNTL, tmp);
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}
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else if (!((info->ChipFamily == CHIP_FAMILY_RV380) ||
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(info->ChipFamily >= CHIP_FAMILY_R420)))
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{
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/* r1xx, r2xx, r300, r(v)350, r420/r481, rs480 */
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tmp = INREG(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
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OUTREG(RADEON_BUS_CNTL, tmp);
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} /* PCIE cards appears to not need this */
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tmp = INREG(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
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OUTREG(RADEON_BUS_CNTL, tmp);
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radeon_do_wait_for_idle();
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/* Sync everything up */
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OUTREG(RADEON_ISYNC_CNTL,
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(RADEON_ISYNC_ANY2D_IDLE3D |
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RADEON_ISYNC_ANY3D_IDLE2D |
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RADEON_ISYNC_WAIT_IDLEGUI |
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RADEON_ISYNC_CPSCRATCH_IDLEGUI));
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}
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void radeon_engine_reset(RHDPtr info)
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{
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u32_t clock_cntl_index;
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u32_t mclk_cntl;
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u32_t rbbm_soft_reset;
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u32_t host_path_cntl;
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if (info->ChipFamily <= CHIP_FAMILY_RV410)
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{
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/* may need something similar for newer chips */
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clock_cntl_index = INREG(RADEON_CLOCK_CNTL_INDEX);
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mclk_cntl = INPLL( RADEON_MCLK_CNTL);
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OUTPLL(RADEON_MCLK_CNTL, (mclk_cntl |
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RADEON_FORCEON_MCLKA |
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RADEON_FORCEON_MCLKB |
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RADEON_FORCEON_YCLKA |
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RADEON_FORCEON_YCLKB |
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RADEON_FORCEON_MC |
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RADEON_FORCEON_AIC));
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}
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rbbm_soft_reset = INREG(RADEON_RBBM_SOFT_RESET);
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OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
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RADEON_SOFT_RESET_CP |
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RADEON_SOFT_RESET_HI |
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RADEON_SOFT_RESET_SE |
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RADEON_SOFT_RESET_RE |
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RADEON_SOFT_RESET_PP |
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RADEON_SOFT_RESET_E2 |
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RADEON_SOFT_RESET_RB));
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INREG(RADEON_RBBM_SOFT_RESET);
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OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
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~(RADEON_SOFT_RESET_CP |
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RADEON_SOFT_RESET_HI |
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RADEON_SOFT_RESET_SE |
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RADEON_SOFT_RESET_RE |
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RADEON_SOFT_RESET_PP |
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RADEON_SOFT_RESET_E2 |
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RADEON_SOFT_RESET_RB)));
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INREG(RADEON_RBBM_SOFT_RESET);
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if (info->ChipFamily <= CHIP_FAMILY_RV410) {
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OUTPLL(RADEON_MCLK_CNTL, mclk_cntl);
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OUTREG(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
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OUTREG(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
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}
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};
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#define RADEON_WAIT_UNTIL_IDLE() do { \
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OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 1 ) ); \
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OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
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RADEON_WAIT_3D_IDLECLEAN | \
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RADEON_WAIT_HOST_IDLECLEAN) ); \
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} while (0)
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#define R300_ZB_ZCACHE_CTLSTAT 0x4f18
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# define RADEON_RB3D_ZC_FLUSH (1 << 0)
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# define RADEON_RB3D_ZC_FREE (1 << 2)
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# define RADEON_RB3D_ZC_FLUSH_ALL 0x5
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# define RADEON_RB3D_ZC_BUSY (1 << 31)
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# define R300_ZC_FLUSH (1 << 0)
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# define R300_ZC_FREE (1 << 1)
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# define R300_ZC_BUSY (1 << 31)
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# define RADEON_RB3D_DC_FLUSH (3 << 0)
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# define RADEON_RB3D_DC_FREE (3 << 2)
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# define RADEON_RB3D_DC_FLUSH_ALL 0xf
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# define RADEON_RB3D_DC_BUSY (1 << 31)
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# define R300_RB3D_DC_FLUSH (2 << 0)
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# define R300_RB3D_DC_FREE (2 << 2)
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#
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#define RADEON_PURGE_CACHE() do { \
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if ( rhd.ChipFamily <= CHIP_FAMILY_RV280) { \
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OUT_RING(CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 1)); \
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OUT_RING(RADEON_RB3D_DC_FLUSH | RADEON_RB3D_DC_FREE); \
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} else { \
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OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 1)); \
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OUT_RING(R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE ); \
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} \
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} while (0)
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#define RADEON_FLUSH_ZCACHE() do { \
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if ( rhd.ChipFamily <= CHIP_FAMILY_RV280) { \
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OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 1 ) ); \
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OUT_RING( RADEON_RB3D_ZC_FLUSH ); \
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} else { \
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OUT_RING( CP_PACKET0( R300_ZB_ZCACHE_CTLSTAT, 1 ) ); \
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OUT_RING( R300_ZC_FLUSH ); \
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} \
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} while (0)
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#define RADEON_PURGE_ZCACHE() do { \
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if (rhd.ChipFamily <= CHIP_FAMILY_RV280) { \
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OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 1)); \
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OUT_RING(RADEON_RB3D_ZC_FLUSH | RADEON_RB3D_ZC_FREE); \
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} else { \
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OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 1)); \
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OUT_RING(R300_ZC_FLUSH | R300_ZC_FREE); \
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} \
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} while (0)
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static int radeon_cp_start(RHDPtr info)
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{
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u32_t *ring, write;
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u32_t ifl;
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radeon_do_wait_for_idle(64);
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OUTREG(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
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ifl = safe_cli();
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BEGIN_RING(8);
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/* isync can only be written through cp on r5xx write it here */
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OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 1));
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OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
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RADEON_ISYNC_ANY3D_IDLE2D |
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RADEON_ISYNC_WAIT_IDLEGUI |
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RADEON_ISYNC_CPSCRATCH_IDLEGUI);
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RADEON_PURGE_CACHE();
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RADEON_PURGE_ZCACHE();
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RADEON_WAIT_UNTIL_IDLE();
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ADVANCE_RING();
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COMMIT_RING();
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safe_sti(ifl);
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radeon_do_wait_for_idle();
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};
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Bool init_cp(RHDPtr info)
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{
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load_microcode(&rhd);
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init_ring_buffer(&rhd);
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radeon_engine_reset(&rhd);
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/* setup the raster pipes */
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init_pipes(&rhd);
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rhd.ring_rp = rhd.ring_wp = INREG(RADEON_CP_RB_RPTR);
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OUTREG(RADEON_CP_RB_WPTR, rhd.ring_rp);
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radeon_cp_start(&rhd);
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return TRUE;
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};
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