197 lines
6.4 KiB
C
197 lines
6.4 KiB
C
/*====================================================================/*
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opcodes_ddfdcb.c -> This file executes the DD/FD CB PREFIX opcodes.
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Those are the double prefix opcodes. We found the DD prefix, which
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means that we must treat HL as IX, and then we found the CB prefix,
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so we must apply this rule to the CB PREFIX list of opcodes. A
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signed byte displacement is also added, and it's located BEFORE
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the DD CB opcode:
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ie: CB 2E = SRA (HL)
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DD CB xx 2E = SRA (IX+xx)
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(or...)
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Those are the double prefix opcodes. We found the FD prefix, which
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means that we must treat HL as IY, and then we found the CB prefix,
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so we must apply this rule to the CB PREFIX list of opcodes. A
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signed byte displacement is also added, and it's located BEFORE
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the FD CB opcode:
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ie: CB 2E = SRA (HL)
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FD CB xx 2E = SRA (IY+xx)
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Call here using something like #define REGISTER regs->IX
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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Copyright (c) 2000 Santiago Romero Iglesias.
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Email: sromero@escomposlinux.org
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=====================================================================*/
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/* 15 clock cycles minimum = FD/DD CB xx opcode = 4 + 4 + 3 + 4 */
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tmpreg.W = REGISTER.W + (offset) Z80ReadMem( r_PC );
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r_PC++;
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r_meml = Z80ReadMem( tmpreg.W );
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opcode = Z80ReadMem( r_PC );
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r_PC++;
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switch(opcode)
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{
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case RLC_xIXY : RLC(r_meml); Z80WriteMem(tmpreg.W, r_meml, regs);
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AddCycles( 23 ); break;
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case RRC_xIXY : RRC(r_meml); Z80WriteMem(tmpreg.W, r_meml, regs);
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AddCycles( 23 ); break;
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case RL_xIXY : RL(r_meml); Z80WriteMem(tmpreg.W, r_meml, regs);
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AddCycles( 23 ); break;
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case RR_xIXY : RR(r_meml); Z80WriteMem(tmpreg.W, r_meml, regs);
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AddCycles( 23 ); break;
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case SLA_xIXY : SLA(r_meml); Z80WriteMem(tmpreg.W, r_meml, regs);
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AddCycles( 23 ); break;
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case SRA_xIXY : SRA(r_meml); Z80WriteMem(tmpreg.W, r_meml, regs);
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AddCycles( 23 ); break;
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case SLL_xIXY : SLL(r_meml); Z80WriteMem(tmpreg.W, r_meml, regs);
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AddCycles( 23 ); break;
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case SRL_xIXY : SRL(r_meml); Z80WriteMem(tmpreg.W, r_meml, regs);
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AddCycles( 23 ); break;
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case 0x40:
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case 0x41:
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case 0x42:
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case 0x43:
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case 0x44:
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case 0x45:
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case 0x47:
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case BIT_0_xIXY : BIT_BIT(0, r_meml); AddCycles( 15+5 ); break;
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case 0x48:
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case 0x49:
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case 0x4a:
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case 0x4b:
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case 0x4c:
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case 0x4d:
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case 0x4f:
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case BIT_1_xIXY :
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BIT_BIT(1, r_meml); AddCycles( 15+5 ); break;
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case 0x50:
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case 0x51:
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case 0x52:
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case 0x53:
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case 0x54:
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case 0x55:
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case 0x57:
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case BIT_2_xIXY : BIT_BIT(2, r_meml); AddCycles( 15+5 ); break;
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case 0x58:
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case 0x59:
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case 0x5a:
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case 0x5b:
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case 0x5c:
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case 0x5d:
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case 0x5f:
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case BIT_3_xIXY : BIT_BIT(3, r_meml); AddCycles( 15+5 ); break;
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case 0x60:
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case 0x61:
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case 0x62:
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case 0x63:
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case 0x64:
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case 0x65:
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case 0x67:
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case BIT_4_xIXY : BIT_BIT(4, r_meml); AddCycles( 15+5 ); break;
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case 0x68:
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case 0x69:
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case 0x6a:
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case 0x6b:
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case 0x6c:
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case 0x6d:
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case 0x6f:
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case BIT_5_xIXY : BIT_BIT(5, r_meml); AddCycles( 15+5 ); break;
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case 0x70:
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case 0x71:
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case 0x72:
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case 0x73:
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case 0x74:
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case 0x75:
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case 0x77:
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case BIT_6_xIXY : BIT_BIT(6, r_meml); AddCycles( 15+5 ); break;
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case 0x78:
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case 0x79:
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case 0x7a:
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case 0x7b:
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case 0x7c:
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case 0x7d:
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case 0x7f:
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case BIT_7_xIXY : BIT_BIT7(r_meml); AddCycles( 15+5 ); break;
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case RES_0_xIXY : BIT_RES_mem(0, tmpreg.W, r_meml );
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AddCycles( 15+5+3 ); break;
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case RES_1_xIXY : BIT_RES_mem(1, tmpreg.W, r_meml );
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AddCycles( 15+5+3 ); break;
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case RES_2_xIXY : BIT_RES_mem(2, tmpreg.W, r_meml );
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AddCycles( 15+5+3 ); break;
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case RES_3_xIXY : BIT_RES_mem(3, tmpreg.W, r_meml );
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AddCycles( 15+5+3 ); break;
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case RES_4_xIXY : BIT_RES_mem(4, tmpreg.W, r_meml );
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AddCycles( 15+5+3 ); break;
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case RES_5_xIXY : BIT_RES_mem(5, tmpreg.W, r_meml );
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AddCycles( 15+5+3 ); break;
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case RES_6_xIXY : BIT_RES_mem(6, tmpreg.W, r_meml );
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AddCycles( 15+5+3 ); break;
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case RES_7_xIXY : BIT_RES_mem(7, tmpreg.W, r_meml );
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AddCycles( 15+5+3 ); break;
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case SET_0_xIXY : BIT_SET_mem(0, tmpreg.W, r_meml );
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AddCycles( 15+5+3 ); break;
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case SET_1_xIXY : BIT_SET_mem(1, tmpreg.W, r_meml );
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AddCycles( 15+5+3 ); break;
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case SET_2_xIXY : BIT_SET_mem(2, tmpreg.W, r_meml );
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AddCycles( 15+5+3 ); break;
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case SET_3_xIXY : BIT_SET_mem(3, tmpreg.W, r_meml );
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AddCycles( 15+5+3 ); break;
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case SET_4_xIXY : BIT_SET_mem(4, tmpreg.W, r_meml );
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AddCycles( 15+5+3 ); break;
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case SET_5_xIXY : BIT_SET_mem(5, tmpreg.W, r_meml );
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AddCycles( 15+5+3 ); break;
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case SET_6_xIXY : BIT_SET_mem(6, tmpreg.W, r_meml );
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AddCycles( 15+5+3 ); break;
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case SET_7_xIXY : BIT_SET_mem(7, tmpreg.W, r_meml );
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AddCycles( 15+5+3 ); break;
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/*
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I must still include the undocumented opcodes such as:
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LD B, RLC(REGISTER+dd) and so on ...
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*/
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default:
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AddCycles( 15 );
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// exit(1);
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///!!! if(regs->DecodingErrors)
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///!!! {
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///!!! printf("z80 core: Unknown instruction: ");
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///!!! if( regs->we_are_on_ddfd == WE_ARE_ON_DD )
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///!!! printf("DD");
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///!!! else
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///!!! printf("FD");
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///!!! printf("CB %02Xh %02Xh at PC=%04Xh.\n",
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///!!! Z80ReadMem(r_PC-2), Z80ReadMem(r_PC-1), r_PC-4 );
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///!!! }
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break;
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}
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