604 lines
16 KiB
C
604 lines
16 KiB
C
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#include <drm/drmP.h>
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#include <drm.h>
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#include <drm_mm.h>
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#include "radeon_drm.h"
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#include "radeon.h"
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#include "radeon_object.h"
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#include "display.h"
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#include "drm_fb_helper.h"
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struct radeon_fbdev {
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struct drm_fb_helper helper;
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struct radeon_framebuffer rfb;
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struct list_head fbdev_list;
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struct radeon_device *rdev;
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};
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struct radeon_fbdev *kos_rfbdev;
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static cursor_t* __stdcall select_cursor_kms(cursor_t *cursor);
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static void __stdcall move_cursor_kms(cursor_t *cursor, int x, int y);
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int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled);
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void disable_mouse(void);
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static void radeon_show_cursor_kms(struct drm_crtc *crtc)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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struct radeon_device *rdev = crtc->dev->dev_private;
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if (ASIC_IS_AVIVO(rdev)) {
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WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset);
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WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN |
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(AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
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} else {
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switch (radeon_crtc->crtc_id) {
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case 0:
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WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL);
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break;
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case 1:
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WREG32(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL);
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break;
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default:
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return;
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}
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WREG32_P(RADEON_MM_DATA, (RADEON_CRTC_CUR_EN |
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(RADEON_CRTC_CUR_MODE_24BPP << RADEON_CRTC_CUR_MODE_SHIFT)),
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~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK));
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}
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}
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static void radeon_lock_cursor_kms(struct drm_crtc *crtc, bool lock)
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{
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struct radeon_device *rdev = crtc->dev->dev_private;
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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uint32_t cur_lock;
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if (ASIC_IS_AVIVO(rdev)) {
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cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset);
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if (lock)
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cur_lock |= AVIVO_D1CURSOR_UPDATE_LOCK;
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else
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cur_lock &= ~AVIVO_D1CURSOR_UPDATE_LOCK;
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WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);
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} else {
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cur_lock = RREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset);
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if (lock)
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cur_lock |= RADEON_CUR_LOCK;
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else
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cur_lock &= ~RADEON_CUR_LOCK;
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WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock);
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}
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}
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cursor_t* __stdcall select_cursor_kms(cursor_t *cursor)
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{
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struct radeon_device *rdev;
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struct radeon_crtc *radeon_crtc;
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cursor_t *old;
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uint32_t gpu_addr;
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rdev = (struct radeon_device *)rdisplay->ddev->dev_private;
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radeon_crtc = to_radeon_crtc(rdisplay->crtc);
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old = rdisplay->cursor;
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rdisplay->cursor = cursor;
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gpu_addr = radeon_bo_gpu_offset(cursor->robj);
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if (ASIC_IS_AVIVO(rdev))
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WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, gpu_addr);
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else {
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radeon_crtc->legacy_cursor_offset = gpu_addr - rdev->mc.vram_start;
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/* offset is from DISP(2)_BASE_ADDRESS */
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WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, radeon_crtc->legacy_cursor_offset);
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}
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return old;
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};
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void __stdcall move_cursor_kms(cursor_t *cursor, int x, int y)
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{
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struct radeon_device *rdev;
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rdev = (struct radeon_device *)rdisplay->ddev->dev_private;
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struct drm_crtc *crtc = rdisplay->crtc;
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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int hot_x = cursor->hot_x;
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int hot_y = cursor->hot_y;
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radeon_lock_cursor_kms(crtc, true);
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if (ASIC_IS_AVIVO(rdev))
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{
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int w = 32;
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int i = 0;
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struct drm_crtc *crtc_p;
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/* avivo cursor are offset into the total surface */
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// x += crtc->x;
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// y += crtc->y;
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// DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
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#if 0
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/* avivo cursor image can't end on 128 pixel boundry or
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* go past the end of the frame if both crtcs are enabled
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*/
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list_for_each_entry(crtc_p, &crtc->dev->mode_config.crtc_list, head) {
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if (crtc_p->enabled)
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i++;
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}
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if (i > 1) {
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int cursor_end, frame_end;
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cursor_end = x + w;
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frame_end = crtc->x + crtc->mode.crtc_hdisplay;
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if (cursor_end >= frame_end) {
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w = w - (cursor_end - frame_end);
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if (!(frame_end & 0x7f))
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w--;
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} else {
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if (!(cursor_end & 0x7f))
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w--;
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}
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if (w <= 0)
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w = 1;
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}
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#endif
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WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset,
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(x << 16) | y);
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WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset,
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(hot_x << 16) | hot_y);
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WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset,
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((w - 1) << 16) | 31);
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} else {
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if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)
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y *= 2;
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uint32_t gpu_addr;
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int xorg =0, yorg=0;
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x = x - hot_x;
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y = y - hot_y;
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if( x < 0 )
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{
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xorg = -x + 1;
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x = 0;
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}
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if( y < 0 )
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{
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yorg = -hot_y + 1;
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y = 0;
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};
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WREG32(RADEON_CUR_HORZ_VERT_OFF,
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(RADEON_CUR_LOCK | (xorg << 16) | yorg ));
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WREG32(RADEON_CUR_HORZ_VERT_POSN,
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(RADEON_CUR_LOCK | (x << 16) | y));
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gpu_addr = radeon_bo_gpu_offset(cursor->robj);
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/* offset is from DISP(2)_BASE_ADDRESS */
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WREG32(RADEON_CUR_OFFSET,
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(gpu_addr - rdev->mc.vram_start + (yorg * 256)));
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}
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radeon_lock_cursor_kms(crtc, false);
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}
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static char *manufacturer_name(unsigned char *x)
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{
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static char name[4];
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name[0] = ((x[0] & 0x7C) >> 2) + '@';
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name[1] = ((x[0] & 0x03) << 3) + ((x[1] & 0xE0) >> 5) + '@';
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name[2] = (x[1] & 0x1F) + '@';
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name[3] = 0;
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return name;
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}
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bool set_mode(struct drm_device *dev, struct drm_connector *connector,
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videomode_t *reqmode, bool strict)
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{
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struct drm_display_mode *mode = NULL, *tmpmode;
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struct drm_fb_helper *fb_helper;
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fb_helper = &kos_rfbdev->helper;
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bool ret = false;
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ENTER();
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dbgprintf("width %d height %d vrefresh %d\n",
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reqmode->width, reqmode->height, reqmode->freq);
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list_for_each_entry(tmpmode, &connector->modes, head)
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{
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if( (drm_mode_width(tmpmode) == reqmode->width) &&
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(drm_mode_height(tmpmode) == reqmode->height) &&
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(drm_mode_vrefresh(tmpmode) == reqmode->freq) )
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{
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mode = tmpmode;
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goto do_set;
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}
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};
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if( (mode == NULL) && (strict == false) )
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{
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list_for_each_entry(tmpmode, &connector->modes, head)
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{
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if( (drm_mode_width(tmpmode) == reqmode->width) &&
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(drm_mode_height(tmpmode) == reqmode->height) )
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{
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mode = tmpmode;
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goto do_set;
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}
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};
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};
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do_set:
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if( mode != NULL )
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{
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struct drm_framebuffer *fb;
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struct drm_encoder *encoder;
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struct drm_crtc *crtc;
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// char con_edid[128];
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char *con_name;
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char *enc_name;
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encoder = connector->encoder;
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crtc = encoder->crtc;
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// fb = list_first_entry(&dev->mode_config.fb_kernel_list,
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// struct drm_framebuffer, filp_head);
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// memcpy(con_edid, connector->edid_blob_ptr->data, 128);
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// dbgprintf("Manufacturer: %s Model %x Serial Number %u\n",
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// manufacturer_name(con_edid + 0x08),
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// (unsigned short)(con_edid[0x0A] + (con_edid[0x0B] << 8)),
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// (unsigned int)(con_edid[0x0C] + (con_edid[0x0D] << 8)
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// + (con_edid[0x0E] << 16) + (con_edid[0x0F] << 24)));
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con_name = drm_get_connector_name(connector);
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enc_name = drm_get_encoder_name(encoder);
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dbgprintf("set mode %d %d connector %s encoder %s\n",
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reqmode->width, reqmode->height, con_name, enc_name);
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fb = fb_helper->fb;
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fb->width = reqmode->width;
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fb->height = reqmode->height;
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fb->pitch = radeon_align_pitch(dev->dev_private, reqmode->width, 32, false) * ((32 + 1) / 8);
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fb->bits_per_pixel = 32;
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crtc->fb = fb;
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crtc->enabled = true;
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rdisplay->crtc = crtc;
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ret = drm_crtc_helper_set_mode(crtc, mode, 0, 0, fb);
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select_cursor_kms(rdisplay->cursor);
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radeon_show_cursor_kms(crtc);
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if (ret == true)
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{
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rdisplay->width = fb->width;
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rdisplay->height = fb->height;
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rdisplay->pitch = fb->pitch;
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rdisplay->vrefresh = drm_mode_vrefresh(mode);
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sysSetScreen(fb->width, fb->height, fb->pitch);
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dbgprintf("new mode %d x %d pitch %d\n",
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fb->width, fb->height, fb->pitch);
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}
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else
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DRM_ERROR("failed to set mode %d_%d on crtc %p\n",
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fb->width, fb->height, crtc);
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}
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LEAVE();
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return ret;
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};
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static int count_connector_modes(struct drm_connector* connector)
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{
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struct drm_display_mode *mode;
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int count = 0;
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list_for_each_entry(mode, &connector->modes, head)
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{
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count++;
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};
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return count;
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};
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static struct drm_connector* get_def_connector(struct drm_device *dev)
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{
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struct drm_connector *connector;
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struct drm_connector_helper_funcs *connector_funcs;
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struct drm_connector *def_connector = NULL;
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list_for_each_entry(connector, &dev->mode_config.connector_list, head)
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{
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struct drm_encoder *encoder;
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struct drm_crtc *crtc;
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if( connector->status != connector_status_connected)
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continue;
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connector_funcs = connector->helper_private;
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encoder = connector_funcs->best_encoder(connector);
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if( encoder == NULL)
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continue;
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connector->encoder = encoder;
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crtc = encoder->crtc;
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dbgprintf("CONNECTOR %x ID: %d status %d encoder %x\n crtc %x",
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connector, connector->base.id,
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connector->status, connector->encoder,
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crtc);
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// if (crtc == NULL)
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// continue;
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def_connector = connector;
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break;
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};
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return def_connector;
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};
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bool init_display_kms(struct radeon_device *rdev, videomode_t *usermode)
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{
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struct drm_device *dev;
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cursor_t *cursor;
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bool retval = false;
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u32_t ifl;
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struct radeon_fbdev *rfbdev;
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struct drm_fb_helper *fb_helper;
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int i;
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ENTER();
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rdisplay = GetDisplay();
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dev = rdisplay->ddev = rdev->ddev;
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ifl = safe_cli();
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{
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list_for_each_entry(cursor, &rdisplay->cursors, list)
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{
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init_cursor(cursor);
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};
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};
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safe_sti(ifl);
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rfbdev = rdev->mode_info.rfbdev;
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fb_helper = &rfbdev->helper;
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// for (i = 0; i < fb_helper->crtc_count; i++)
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// {
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struct drm_mode_set *mode_set = &fb_helper->crtc_info[0].mode_set;
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struct drm_crtc *crtc;
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struct drm_display_mode *mode;
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crtc = mode_set->crtc;
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// if (!crtc->enabled)
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// continue;
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mode = mode_set->mode;
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dbgprintf("crtc %d width %d height %d vrefresh %d\n",
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crtc->base.id,
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drm_mode_width(mode), drm_mode_height(mode),
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drm_mode_vrefresh(mode));
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// }
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rdisplay->connector = get_def_connector(dev);
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if( rdisplay->connector == 0 )
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{
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dbgprintf("no active connectors\n");
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return false;
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};
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rdisplay->crtc = rdisplay->connector->encoder->crtc = crtc;
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rdisplay->supported_modes = count_connector_modes(rdisplay->connector);
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dbgprintf("current mode %d x %d x %d\n",
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rdisplay->width, rdisplay->height, rdisplay->vrefresh);
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dbgprintf("user mode mode %d x %d x %d\n",
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usermode->width, usermode->height, usermode->freq);
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if( (usermode->width != 0) &&
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(usermode->height != 0) &&
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( (usermode->width != rdisplay->width) ||
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(usermode->height != rdisplay->height) ||
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(usermode->freq != rdisplay->vrefresh) ) )
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{
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retval = set_mode(dev, rdisplay->connector, usermode, false);
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}
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ifl = safe_cli();
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{
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rdisplay->restore_cursor(0,0);
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rdisplay->init_cursor = init_cursor;
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rdisplay->select_cursor = select_cursor_kms;
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rdisplay->show_cursor = NULL;
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rdisplay->move_cursor = move_cursor_kms;
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rdisplay->restore_cursor = restore_cursor;
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rdisplay->disable_mouse = disable_mouse;
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select_cursor_kms(rdisplay->cursor);
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radeon_show_cursor_kms(rdisplay->crtc);
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};
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safe_sti(ifl);
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LEAVE();
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return retval;
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};
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int get_modes(videomode_t *mode, int *count)
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{
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int err = -1;
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ENTER();
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dbgprintf("mode %x count %d\n", mode, *count);
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if( *count == 0 )
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{
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*count = rdisplay->supported_modes;
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err = 0;
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}
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else if( mode != NULL )
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{
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struct drm_display_mode *drmmode;
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int i = 0;
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if( *count > rdisplay->supported_modes)
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*count = rdisplay->supported_modes;
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list_for_each_entry(drmmode, &rdisplay->connector->modes, head)
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{
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if( i < *count)
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{
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mode->width = drm_mode_width(drmmode);
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mode->height = drm_mode_height(drmmode);
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mode->bpp = 32;
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mode->freq = drm_mode_vrefresh(drmmode);
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i++;
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mode++;
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}
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else break;
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};
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*count = i;
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err = 0;
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};
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LEAVE();
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return err;
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}
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int set_user_mode(videomode_t *mode)
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{
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int err = -1;
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ENTER();
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dbgprintf("width %d height %d vrefresh %d\n",
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mode->width, mode->height, mode->freq);
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if( (mode->width != 0) &&
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(mode->height != 0) &&
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(mode->freq != 0 ) &&
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( (mode->width != rdisplay->width) ||
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(mode->height != rdisplay->height) ||
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(mode->freq != rdisplay->vrefresh) ) )
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{
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if( set_mode(rdisplay->ddev, rdisplay->connector, mode, true) )
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err = 0;
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};
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|
LEAVE();
|
|
return err;
|
|
};
|
|
|
|
|
|
|
|
int radeonfb_create_object(struct radeon_fbdev *rfbdev,
|
|
struct drm_mode_fb_cmd *mode_cmd,
|
|
struct drm_gem_object **gobj_p)
|
|
{
|
|
struct radeon_device *rdev = rfbdev->rdev;
|
|
struct drm_gem_object *gobj = NULL;
|
|
struct radeon_bo *rbo = NULL;
|
|
bool fb_tiled = false; /* useful for testing */
|
|
u32 tiling_flags = 0;
|
|
int ret;
|
|
int aligned_size, size;
|
|
int height = mode_cmd->height;
|
|
|
|
static struct radeon_bo kos_bo;
|
|
static struct drm_mm_node vm_node;
|
|
|
|
/* need to align pitch with crtc limits */
|
|
mode_cmd->pitch = radeon_align_pitch(rdev, mode_cmd->width, mode_cmd->bpp, fb_tiled) * ((mode_cmd->bpp + 1) / 8);
|
|
|
|
if (rdev->family >= CHIP_R600)
|
|
height = ALIGN(mode_cmd->height, 8);
|
|
size = mode_cmd->pitch * height;
|
|
aligned_size = ALIGN(size, PAGE_SIZE);
|
|
|
|
ret = drm_gem_object_init(rdev->ddev, &kos_bo.gem_base, aligned_size);
|
|
if (unlikely(ret)) {
|
|
return ret;
|
|
}
|
|
|
|
kos_bo.rdev = rdev;
|
|
kos_bo.gem_base.driver_private = NULL;
|
|
kos_bo.surface_reg = -1;
|
|
kos_bo.domain = RADEON_GEM_DOMAIN_VRAM;
|
|
|
|
INIT_LIST_HEAD(&kos_bo.list);
|
|
|
|
gobj = &kos_bo.gem_base;
|
|
rbo = gem_to_radeon_bo(gobj);
|
|
|
|
if (fb_tiled)
|
|
tiling_flags = RADEON_TILING_MACRO;
|
|
|
|
if (tiling_flags) {
|
|
rbo->tiling_flags = tiling_flags | RADEON_TILING_SURFACE;
|
|
rbo->pitch = mode_cmd->pitch;
|
|
}
|
|
|
|
vm_node.size = 0xC00000 >> 12;
|
|
vm_node.start = 0;
|
|
vm_node.mm = NULL;
|
|
|
|
rbo->tbo.vm_node = &vm_node;
|
|
rbo->tbo.offset = rbo->tbo.vm_node->start << PAGE_SHIFT;
|
|
rbo->tbo.offset += (u64)rbo->rdev->mc.vram_start;
|
|
rbo->kptr = (void*)0xFE000000;
|
|
rbo->pin_count = 1;
|
|
|
|
// if (fb_tiled)
|
|
// radeon_bo_check_tiling(rbo, 0, 0);
|
|
|
|
*gobj_p = gobj;
|
|
return 0;
|
|
}
|
|
|
|
|
|
|
|
|