464 lines
14 KiB
C
464 lines
14 KiB
C
/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <linux/kernel.h>
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#include <drm/drmP.h>
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#include <drm/drm_edid.h>
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#include "intel_drv.h"
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#include "i915_drv.h"
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/**
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* DOC: High Definition Audio over HDMI and Display Port
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*
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* The graphics and audio drivers together support High Definition Audio over
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* HDMI and Display Port. The audio programming sequences are divided into audio
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* codec and controller enable and disable sequences. The graphics driver
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* handles the audio codec sequences, while the audio driver handles the audio
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* controller sequences.
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*
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* The disable sequences must be performed before disabling the transcoder or
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* port. The enable sequences may only be performed after enabling the
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* transcoder and port, and after completed link training.
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*
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* The codec and controller sequences could be done either parallel or serial,
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* but generally the ELDV/PD change in the codec sequence indicates to the audio
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* driver that the controller sequence should start. Indeed, most of the
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* co-operation between the graphics and audio drivers is handled via audio
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* related registers. (The notable exception is the power management, not
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* covered here.)
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*/
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static const struct {
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int clock;
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u32 config;
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} hdmi_audio_clock[] = {
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{ DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
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{ 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
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{ 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
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{ 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
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{ 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
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{ 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
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{ DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
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{ 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
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{ DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
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{ 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
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};
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/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
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static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
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if (mode->clock == hdmi_audio_clock[i].clock)
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break;
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}
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if (i == ARRAY_SIZE(hdmi_audio_clock)) {
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DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
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i = 1;
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}
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DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
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hdmi_audio_clock[i].clock,
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hdmi_audio_clock[i].config);
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return hdmi_audio_clock[i].config;
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}
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static bool intel_eld_uptodate(struct drm_connector *connector,
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int reg_eldv, uint32_t bits_eldv,
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int reg_elda, uint32_t bits_elda,
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int reg_edid)
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{
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struct drm_i915_private *dev_priv = connector->dev->dev_private;
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uint8_t *eld = connector->eld;
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uint32_t tmp;
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int i;
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tmp = I915_READ(reg_eldv);
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tmp &= bits_eldv;
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if (!tmp)
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return false;
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tmp = I915_READ(reg_elda);
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tmp &= ~bits_elda;
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I915_WRITE(reg_elda, tmp);
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for (i = 0; i < drm_eld_size(eld) / 4; i++)
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if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
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return false;
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return true;
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}
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static void g4x_audio_codec_disable(struct intel_encoder *encoder)
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{
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struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
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uint32_t eldv, tmp;
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DRM_DEBUG_KMS("Disable audio codec\n");
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tmp = I915_READ(G4X_AUD_VID_DID);
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if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
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eldv = G4X_ELDV_DEVCL_DEVBLC;
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else
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eldv = G4X_ELDV_DEVCTG;
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/* Invalidate ELD */
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tmp = I915_READ(G4X_AUD_CNTL_ST);
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tmp &= ~eldv;
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I915_WRITE(G4X_AUD_CNTL_ST, tmp);
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}
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static void g4x_audio_codec_enable(struct drm_connector *connector,
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struct intel_encoder *encoder,
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struct drm_display_mode *mode)
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{
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struct drm_i915_private *dev_priv = connector->dev->dev_private;
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uint8_t *eld = connector->eld;
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uint32_t eldv;
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uint32_t tmp;
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int len, i;
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DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", eld[2]);
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tmp = I915_READ(G4X_AUD_VID_DID);
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if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
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eldv = G4X_ELDV_DEVCL_DEVBLC;
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else
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eldv = G4X_ELDV_DEVCTG;
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if (intel_eld_uptodate(connector,
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G4X_AUD_CNTL_ST, eldv,
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G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK,
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G4X_HDMIW_HDMIEDID))
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return;
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tmp = I915_READ(G4X_AUD_CNTL_ST);
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tmp &= ~(eldv | G4X_ELD_ADDR_MASK);
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len = (tmp >> 9) & 0x1f; /* ELD buffer size */
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I915_WRITE(G4X_AUD_CNTL_ST, tmp);
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len = min(drm_eld_size(eld) / 4, len);
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DRM_DEBUG_DRIVER("ELD size %d\n", len);
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for (i = 0; i < len; i++)
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I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
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tmp = I915_READ(G4X_AUD_CNTL_ST);
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tmp |= eldv;
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I915_WRITE(G4X_AUD_CNTL_ST, tmp);
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}
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static void hsw_audio_codec_disable(struct intel_encoder *encoder)
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{
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struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
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enum pipe pipe = intel_crtc->pipe;
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uint32_t tmp;
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DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe));
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/* Disable timestamps */
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tmp = I915_READ(HSW_AUD_CFG(pipe));
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tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
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tmp |= AUD_CONFIG_N_PROG_ENABLE;
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tmp &= ~AUD_CONFIG_UPPER_N_MASK;
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tmp &= ~AUD_CONFIG_LOWER_N_MASK;
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if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
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tmp |= AUD_CONFIG_N_VALUE_INDEX;
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I915_WRITE(HSW_AUD_CFG(pipe), tmp);
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/* Invalidate ELD */
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tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
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tmp &= ~AUDIO_ELD_VALID(pipe);
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tmp &= ~AUDIO_OUTPUT_ENABLE(pipe);
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I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
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}
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static void hsw_audio_codec_enable(struct drm_connector *connector,
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struct intel_encoder *encoder,
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struct drm_display_mode *mode)
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{
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struct drm_i915_private *dev_priv = connector->dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
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enum pipe pipe = intel_crtc->pipe;
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const uint8_t *eld = connector->eld;
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uint32_t tmp;
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int len, i;
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DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n",
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pipe_name(pipe), drm_eld_size(eld));
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/* Enable audio presence detect, invalidate ELD */
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tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
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tmp |= AUDIO_OUTPUT_ENABLE(pipe);
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tmp &= ~AUDIO_ELD_VALID(pipe);
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I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
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/*
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* FIXME: We're supposed to wait for vblank here, but we have vblanks
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* disabled during the mode set. The proper fix would be to push the
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* rest of the setup into a vblank work item, queued here, but the
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* infrastructure is not there yet.
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*/
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/* Reset ELD write address */
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tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe));
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tmp &= ~IBX_ELD_ADDRESS_MASK;
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I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp);
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/* Up to 84 bytes of hw ELD buffer */
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len = min(drm_eld_size(eld), 84);
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for (i = 0; i < len / 4; i++)
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I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((uint32_t *)eld + i));
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/* ELD valid */
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tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
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tmp |= AUDIO_ELD_VALID(pipe);
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I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
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/* Enable timestamps */
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tmp = I915_READ(HSW_AUD_CFG(pipe));
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tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
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tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
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tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
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if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
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tmp |= AUD_CONFIG_N_VALUE_INDEX;
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else
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tmp |= audio_config_hdmi_pixel_clock(mode);
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I915_WRITE(HSW_AUD_CFG(pipe), tmp);
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}
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static void ilk_audio_codec_disable(struct intel_encoder *encoder)
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{
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struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
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struct intel_digital_port *intel_dig_port =
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enc_to_dig_port(&encoder->base);
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enum port port = intel_dig_port->port;
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enum pipe pipe = intel_crtc->pipe;
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uint32_t tmp, eldv;
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int aud_config;
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int aud_cntrl_st2;
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DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n",
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port_name(port), pipe_name(pipe));
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if (HAS_PCH_IBX(dev_priv->dev)) {
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aud_config = IBX_AUD_CFG(pipe);
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aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
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} else if (IS_VALLEYVIEW(dev_priv)) {
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aud_config = VLV_AUD_CFG(pipe);
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aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
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} else {
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aud_config = CPT_AUD_CFG(pipe);
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aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
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}
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/* Disable timestamps */
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tmp = I915_READ(aud_config);
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tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
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tmp |= AUD_CONFIG_N_PROG_ENABLE;
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tmp &= ~AUD_CONFIG_UPPER_N_MASK;
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tmp &= ~AUD_CONFIG_LOWER_N_MASK;
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if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
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tmp |= AUD_CONFIG_N_VALUE_INDEX;
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I915_WRITE(aud_config, tmp);
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if (WARN_ON(!port)) {
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eldv = IBX_ELD_VALID(PORT_B) | IBX_ELD_VALID(PORT_C) |
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IBX_ELD_VALID(PORT_D);
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} else {
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eldv = IBX_ELD_VALID(port);
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}
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/* Invalidate ELD */
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tmp = I915_READ(aud_cntrl_st2);
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tmp &= ~eldv;
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I915_WRITE(aud_cntrl_st2, tmp);
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}
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static void ilk_audio_codec_enable(struct drm_connector *connector,
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struct intel_encoder *encoder,
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struct drm_display_mode *mode)
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{
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struct drm_i915_private *dev_priv = connector->dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
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struct intel_digital_port *intel_dig_port =
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enc_to_dig_port(&encoder->base);
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enum port port = intel_dig_port->port;
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enum pipe pipe = intel_crtc->pipe;
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uint8_t *eld = connector->eld;
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uint32_t eldv;
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uint32_t tmp;
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int len, i;
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int hdmiw_hdmiedid;
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int aud_config;
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int aud_cntl_st;
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int aud_cntrl_st2;
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DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n",
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port_name(port), pipe_name(pipe), drm_eld_size(eld));
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/*
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* FIXME: We're supposed to wait for vblank here, but we have vblanks
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* disabled during the mode set. The proper fix would be to push the
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* rest of the setup into a vblank work item, queued here, but the
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* infrastructure is not there yet.
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*/
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if (HAS_PCH_IBX(connector->dev)) {
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hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
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aud_config = IBX_AUD_CFG(pipe);
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aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
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aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
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} else if (IS_VALLEYVIEW(connector->dev)) {
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hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
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aud_config = VLV_AUD_CFG(pipe);
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aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
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aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
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} else {
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hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
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aud_config = CPT_AUD_CFG(pipe);
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aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
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aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
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}
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if (WARN_ON(!port)) {
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eldv = IBX_ELD_VALID(PORT_B) | IBX_ELD_VALID(PORT_C) |
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IBX_ELD_VALID(PORT_D);
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} else {
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eldv = IBX_ELD_VALID(port);
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}
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/* Invalidate ELD */
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tmp = I915_READ(aud_cntrl_st2);
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tmp &= ~eldv;
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I915_WRITE(aud_cntrl_st2, tmp);
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/* Reset ELD write address */
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tmp = I915_READ(aud_cntl_st);
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tmp &= ~IBX_ELD_ADDRESS_MASK;
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I915_WRITE(aud_cntl_st, tmp);
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/* Up to 84 bytes of hw ELD buffer */
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len = min(drm_eld_size(eld), 84);
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for (i = 0; i < len / 4; i++)
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I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
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/* ELD valid */
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tmp = I915_READ(aud_cntrl_st2);
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tmp |= eldv;
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I915_WRITE(aud_cntrl_st2, tmp);
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/* Enable timestamps */
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tmp = I915_READ(aud_config);
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tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
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tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
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tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
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if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
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tmp |= AUD_CONFIG_N_VALUE_INDEX;
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else
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tmp |= audio_config_hdmi_pixel_clock(mode);
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I915_WRITE(aud_config, tmp);
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}
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/**
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* intel_audio_codec_enable - Enable the audio codec for HD audio
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* @intel_encoder: encoder on which to enable audio
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*
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* The enable sequences may only be performed after enabling the transcoder and
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* port, and after completed link training.
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*/
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void intel_audio_codec_enable(struct intel_encoder *intel_encoder)
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{
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struct drm_encoder *encoder = &intel_encoder->base;
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struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
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struct drm_display_mode *mode = &crtc->config.adjusted_mode;
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struct drm_connector *connector;
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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connector = drm_select_eld(encoder, mode);
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if (!connector)
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return;
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DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
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connector->base.id,
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connector->name,
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connector->encoder->base.id,
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connector->encoder->name);
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/* ELD Conn_Type */
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connector->eld[5] &= ~(3 << 2);
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if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
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connector->eld[5] |= (1 << 2);
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connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
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if (dev_priv->display.audio_codec_enable)
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dev_priv->display.audio_codec_enable(connector, intel_encoder, mode);
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}
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/**
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* intel_audio_codec_disable - Disable the audio codec for HD audio
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* @encoder: encoder on which to disable audio
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*
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* The disable sequences must be performed before disabling the transcoder or
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* port.
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*/
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void intel_audio_codec_disable(struct intel_encoder *encoder)
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{
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struct drm_device *dev = encoder->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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if (dev_priv->display.audio_codec_disable)
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dev_priv->display.audio_codec_disable(encoder);
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}
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/**
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* intel_init_audio - Set up chip specific audio functions
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* @dev: drm device
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*/
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void intel_init_audio(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
if (IS_G4X(dev)) {
|
|
dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
|
|
dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
|
|
} else if (IS_VALLEYVIEW(dev)) {
|
|
dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
|
|
dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
|
|
} else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) {
|
|
dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
|
|
dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
|
|
} else if (HAS_PCH_SPLIT(dev)) {
|
|
dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
|
|
dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
|
|
}
|
|
}
|