289 lines
6.9 KiB
C
289 lines
6.9 KiB
C
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#include "ati_pciids_gen.h"
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#include "radeon_chipset_gen.h"
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#include "radeon_chipinfo_gen.h"
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const char *
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xf86TokenToString(SymTabPtr table, int token)
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{
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int i;
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for (i = 0; table[i].token >= 0 && table[i].token != token; i++){};
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if (table[i].token < 0)
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return NULL;
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else
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return(table[i].name);
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}
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const RADEONCardInfo *RadeonDevMatch(u16_t dev,const RADEONCardInfo *list)
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{
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while(list->pci_device_id)
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{
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if(dev == list->pci_device_id)
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return list;
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list++;
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}
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return 0;
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}
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RHDPtr FindPciDevice()
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{
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const RADEONCardInfo *dev;
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u32_t bus, last_bus;
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if( (last_bus = PciApi(1))==-1)
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return 0;
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for(bus=0;bus<=last_bus;bus++)
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{
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u32_t devfn;
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for(devfn=0;devfn<256;devfn++)
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{
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u32_t id;
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id = PciRead32(bus,devfn, 0);
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if( (u16_t)id != VENDOR_ATI)
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continue;
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rhd.PciDeviceID = (id>>16);
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if( (dev = RadeonDevMatch(rhd.PciDeviceID, RADEONCards))!=NULL)
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{
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u32_t reg2C;
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int i;
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rhd.chipset = (char*)xf86TokenToString(RADEONChipsets, rhd.PciDeviceID);
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if (!rhd.chipset){
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dbgprintf("ChipID 0x%04x is not recognized\n", rhd.PciDeviceID);
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return FALSE;
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}
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dbgprintf("Chipset: \"%s\" (ChipID = 0x%04x)\n",
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rhd.chipset,rhd.PciDeviceID);
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rhd.bus = bus;
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rhd.devfn = devfn;
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rhd.PciTag = pciTag(bus,(devfn>>3)&0x1F,devfn&0x7);
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rhd.ChipFamily = dev->chip_family;
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rhd.IsMobility = dev->mobility;
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rhd.IsIGP = dev->igp;
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rhd.HasCRTC2 = !dev->nocrtc2;
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reg2C = PciRead32(bus,devfn, 0x2C);
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rhd.subvendor_id = reg2C & 0xFFFF;;
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rhd.subdevice_id = reg2C >> 16;
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if (rhd.ChipFamily >= CHIP_FAMILY_R600)
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dbgprintf("R600 unsupported yet.\nExit\n");
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if( rhd.ChipFamily >= CHIP_FAMILY_R420)
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rhd.gart_type = RADEON_IS_PCIE;
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else
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rhd.gart_type = RADEON_IS_PCI;
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for (i = 0; i < 6; i++)
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{
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u32_t base;
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Bool validSize;
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base = PciRead32(bus,devfn, PCI_MAP_REG_START + (i << 2));
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if(base)
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{
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if (base & PCI_MAP_IO){
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rhd.ioBase[i] = (u32_t)PCIGETIO(base);
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rhd.memtype[i] = base & PCI_MAP_IO_ATTR_MASK;
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}
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else{
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rhd.memBase[i] = (u32_t)PCIGETMEMORY(base);
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rhd.memtype[i] = base & PCI_MAP_MEMORY_ATTR_MASK;
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}
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}
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rhd.memsize[i] = pciGetBaseSize(bus,devfn, i, TRUE, &validSize);
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}
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return &rhd;
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}
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}
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};
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return NULL;
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}
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u32_t pciGetBaseSize(int bus, int devfn, int index, Bool destructive, Bool *min)
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{
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int offset;
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u32_t addr1;
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u32_t addr2;
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u32_t mask1;
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u32_t mask2;
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int bits = 0;
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/*
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* silently ignore bogus index values. Valid values are 0-6. 0-5 are
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* the 6 base address registers, and 6 is the ROM base address register.
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*/
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if (index < 0 || index > 6)
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return 0;
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if (min)
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*min = destructive;
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/* Get the PCI offset */
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if (index == 6)
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offset = PCI_MAP_ROM_REG;
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else
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offset = PCI_MAP_REG_START + (index << 2);
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addr1 = PciRead32(bus, devfn, offset);
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/*
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* Check if this is the second part of a 64 bit address.
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* XXX need to check how endianness affects 64 bit addresses.
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*/
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if (index > 0 && index < 6) {
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addr2 = PciRead32(bus, devfn, offset - 4);
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if (PCI_MAP_IS_MEM(addr2) && PCI_MAP_IS64BITMEM(addr2))
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return 0;
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}
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if (destructive) {
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PciWrite32(bus, devfn, offset, 0xffffffff);
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mask1 = PciRead32(bus, devfn, offset);
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PciWrite32(bus, devfn, offset, addr1);
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} else {
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mask1 = addr1;
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}
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/* Check if this is the first part of a 64 bit address. */
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if (index < 5 && PCI_MAP_IS_MEM(mask1) && PCI_MAP_IS64BITMEM(mask1))
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{
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if (PCIGETMEMORY(mask1) == 0)
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{
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addr2 = PciRead32(bus, devfn, offset + 4);
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if (destructive)
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{
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PciWrite32(bus, devfn, offset + 4, 0xffffffff);
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mask2 = PciRead32(bus, devfn, offset + 4);
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PciWrite32(bus, devfn, offset + 4, addr2);
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}
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else
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{
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mask2 = addr2;
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}
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if (mask2 == 0)
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return 0;
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bits = 32;
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while ((mask2 & 1) == 0)
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{
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bits++;
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mask2 >>= 1;
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}
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if (bits > 32)
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return bits;
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}
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}
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if (index < 6)
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if (PCI_MAP_IS_MEM(mask1))
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mask1 = PCIGETMEMORY(mask1);
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else
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mask1 = PCIGETIO(mask1);
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else
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mask1 = PCIGETROM(mask1);
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if (mask1 == 0)
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return 0;
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bits = 0;
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while ((mask1 & 1) == 0) {
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bits++;
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mask1 >>= 1;
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}
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/* I/O maps can be no larger than 8 bits */
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if ((index < 6) && PCI_MAP_IS_IO(addr1) && bits > 8)
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bits = 8;
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/* ROM maps can be no larger than 24 bits */
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if (index == 6 && bits > 24)
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bits = 24;
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return bits;
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}
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#define PCI_FIND_CAP_TTL 48
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static int __pci_find_next_cap_ttl(PCITAG pciTag, u8_t pos,
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int cap, int *ttl)
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{
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u8_t id;
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while ((*ttl)--)
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{
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pos = pciReadByte(pciTag, pos);
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if (pos < 0x40)
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break;
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pos &= ~3;
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id = pciReadByte(pciTag, pos + PCI_CAP_LIST_ID);
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if (id == 0xff)
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break;
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if (id == cap)
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return pos;
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pos += PCI_CAP_LIST_NEXT;
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}
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return 0;
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}
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static int __pci_find_next_cap(PCITAG pciTag, u8_t pos, int cap)
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{
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int ttl = PCI_FIND_CAP_TTL;
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return __pci_find_next_cap_ttl(pciTag, pos, cap, &ttl);
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}
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static int __pci_bus_find_cap_start(PCITAG pciTag)
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{
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u16_t status;
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u8_t hdr_type;
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status = pciReadWord(pciTag, PCI_STATUS);
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if (!(status & PCI_STATUS_CAP_LIST))
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return 0;
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hdr_type = pciReadByte(pciTag, 0x0E);
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switch (hdr_type)
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{
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case PCI_HEADER_TYPE_NORMAL:
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case PCI_HEADER_TYPE_BRIDGE:
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return PCI_CAPABILITY_LIST;
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case PCI_HEADER_TYPE_CARDBUS:
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return PCI_CB_CAPABILITY_LIST;
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default:
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return 0;
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}
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return 0;
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}
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int pci_find_capability(PCITAG pciTag, int cap)
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{
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int pos;
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pos = __pci_bus_find_cap_start(pciTag);
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if (pos)
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pos = __pci_find_next_cap(pciTag, pos, cap);
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return pos;
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}
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static __inline__ int drm_device_is_pcie(PCITAG pciTag)
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{
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return pci_find_capability(pciTag, PCI_CAP_ID_EXP);
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}
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