443 lines
11 KiB
C
443 lines
11 KiB
C
#include <drm/drmP.h>
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#include <drm.h>
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#include <drm/i915_drm.h>
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#include "i915_drv.h"
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//#include "intel_drv.h"
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mod_devicetable.h>
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#include <errno-base.h>
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#include <linux/pci.h>
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#include <syscall.h>
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#include "bitmap.h"
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struct pci_device {
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uint16_t domain;
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uint8_t bus;
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uint8_t dev;
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uint8_t func;
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uint16_t vendor_id;
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uint16_t device_id;
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uint16_t subvendor_id;
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uint16_t subdevice_id;
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uint32_t device_class;
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uint8_t revision;
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};
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extern struct drm_device *main_device;
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extern struct drm_file *drm_file_handlers[256];
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void cpu_detect();
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void parse_cmdline(char *cmdline, char *log);
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int _stdcall display_handler(ioctl_t *io);
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int init_agp(void);
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int srv_blit_bitmap(u32 hbitmap, int dst_x, int dst_y,
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int src_x, int src_y, u32 w, u32 h);
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int blit_textured(u32 hbitmap, int dst_x, int dst_y,
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int src_x, int src_y, u32 w, u32 h);
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int blit_tex(u32 hbitmap, int dst_x, int dst_y,
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int src_x, int src_y, u32 w, u32 h);
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void get_pci_info(struct pci_device *dev);
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int gem_getparam(struct drm_device *dev, void *data);
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int i915_mask_update(struct drm_device *dev, void *data,
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struct drm_file *file);
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static char log[256];
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struct workqueue_struct *system_wq;
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int driver_wq_state;
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int x86_clflush_size;
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unsigned int tsc_khz;
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int i915_modeset = 1;
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u32_t __attribute__((externally_visible)) drvEntry(int action, char *cmdline)
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{
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int err = 0;
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if(action != 1)
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{
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driver_wq_state = 0;
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return 0;
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};
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if( GetService("DISPLAY") != 0 )
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return 0;
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if( cmdline && *cmdline )
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parse_cmdline(cmdline, log);
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if(!dbg_open(log))
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{
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strcpy(log, "/tmp1/1/i915.log");
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// strcpy(log, "/RD/1/DRIVERS/i915.log");
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if(!dbg_open(log))
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{
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printf("Can't open %s\nExit\n", log);
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return 0;
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};
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}
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dbgprintf(" i915 v3.10\n cmdline: %s\n", cmdline);
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cpu_detect();
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// dbgprintf("\ncache line size %d\n", x86_clflush_size);
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enum_pci_devices();
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err = i915_init();
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if(err)
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{
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dbgprintf("Epic Fail :(\n");
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return 0;
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};
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err = RegService("DISPLAY", display_handler);
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if( err != 0)
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dbgprintf("Set DISPLAY handler\n");
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struct drm_i915_private *dev_priv = main_device->dev_private;
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driver_wq_state = 1;
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run_workqueue(dev_priv->wq);
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return err;
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};
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#define CURRENT_API 0x0200 /* 2.00 */
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#define COMPATIBLE_API 0x0100 /* 1.00 */
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#define API_VERSION (COMPATIBLE_API << 16) | CURRENT_API
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#define DISPLAY_VERSION API_VERSION
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#define SRV_GETVERSION 0
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#define SRV_ENUM_MODES 1
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#define SRV_SET_MODE 2
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#define SRV_GET_CAPS 3
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#define SRV_CREATE_SURFACE 10
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#define SRV_DESTROY_SURFACE 11
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#define SRV_LOCK_SURFACE 12
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#define SRV_UNLOCK_SURFACE 13
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#define SRV_RESIZE_SURFACE 14
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#define SRV_BLIT_BITMAP 15
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#define SRV_BLIT_TEXTURE 16
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#define SRV_BLIT_VIDEO 17
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#define SRV_GET_PCI_INFO 20
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#define SRV_GET_PARAM 21
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#define SRV_I915_GEM_CREATE 22
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#define SRV_DRM_GEM_CLOSE 23
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#define SRV_I915_GEM_PIN 24
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#define SRV_I915_GEM_SET_CACHEING 25
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#define SRV_I915_GEM_GET_APERTURE 26
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#define SRV_I915_GEM_PWRITE 27
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#define SRV_I915_GEM_BUSY 28
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#define SRV_I915_GEM_SET_DOMAIN 29
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#define SRV_I915_GEM_MMAP 30
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#define SRV_I915_GEM_MMAP_GTT 31
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#define SRV_I915_GEM_THROTTLE 32
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#define SRV_FBINFO 33
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#define SRV_I915_GEM_EXECBUFFER2 34
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#define SRV_MASK_UPDATE 35
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#define check_input(size) \
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if( unlikely((inp==NULL)||(io->inp_size != (size))) ) \
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break;
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#define check_output(size) \
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if( unlikely((outp==NULL)||(io->out_size != (size))) ) \
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break;
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int _stdcall display_handler(ioctl_t *io)
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{
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struct drm_file *file;
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int retval = -1;
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u32_t *inp;
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u32_t *outp;
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inp = io->input;
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outp = io->output;
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file = drm_file_handlers[0];
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switch(io->io_code)
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{
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case SRV_GETVERSION:
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check_output(4);
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*outp = DISPLAY_VERSION;
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retval = 0;
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break;
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case SRV_ENUM_MODES:
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// dbgprintf("SRV_ENUM_MODES inp %x inp_size %x out_size %x\n",
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// inp, io->inp_size, io->out_size );
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check_output(4);
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// check_input(*outp * sizeof(videomode_t));
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if( i915_modeset)
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retval = get_videomodes((videomode_t*)inp, outp);
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break;
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case SRV_SET_MODE:
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// dbgprintf("SRV_SET_MODE inp %x inp_size %x\n",
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// inp, io->inp_size);
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check_input(sizeof(videomode_t));
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if( i915_modeset )
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retval = set_user_mode((videomode_t*)inp);
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break;
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case SRV_GET_CAPS:
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retval = get_driver_caps((hwcaps_t*)inp);
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break;
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case SRV_CREATE_SURFACE:
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// check_input(8);
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// retval = create_surface(main_device, (struct io_call_10*)inp);
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break;
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case SRV_LOCK_SURFACE:
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// retval = lock_surface((struct io_call_12*)inp);
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break;
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case SRV_RESIZE_SURFACE:
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// retval = resize_surface((struct io_call_14*)inp);
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break;
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case SRV_BLIT_BITMAP:
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// srv_blit_bitmap( inp[0], inp[1], inp[2],
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// inp[3], inp[4], inp[5], inp[6]);
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// blit_tex( inp[0], inp[1], inp[2],
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// inp[3], inp[4], inp[5], inp[6]);
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break;
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case SRV_GET_PCI_INFO:
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get_pci_info((struct pci_device *)inp);
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retval = 0;
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break;
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case SRV_GET_PARAM:
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retval = gem_getparam(main_device, inp);
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break;
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case SRV_I915_GEM_CREATE:
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retval = i915_gem_create_ioctl(main_device, inp, file);
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break;
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case SRV_DRM_GEM_CLOSE:
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retval = drm_gem_close_ioctl(main_device, inp, file);
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break;
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case SRV_I915_GEM_PIN:
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retval = i915_gem_pin_ioctl(main_device, inp, file);
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break;
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case SRV_I915_GEM_SET_CACHEING:
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retval = i915_gem_set_caching_ioctl(main_device, inp, file);
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break;
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case SRV_I915_GEM_GET_APERTURE:
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retval = i915_gem_get_aperture_ioctl(main_device, inp, file);
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break;
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case SRV_I915_GEM_PWRITE:
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retval = i915_gem_pwrite_ioctl(main_device, inp, file);
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break;
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case SRV_I915_GEM_BUSY:
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retval = i915_gem_busy_ioctl(main_device, inp, file);
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break;
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case SRV_I915_GEM_SET_DOMAIN:
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retval = i915_gem_set_domain_ioctl(main_device, inp, file);
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break;
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case SRV_I915_GEM_THROTTLE:
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retval = i915_gem_throttle_ioctl(main_device, inp, file);
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break;
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case SRV_I915_GEM_MMAP:
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retval = i915_gem_mmap_ioctl(main_device, inp, file);
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break;
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case SRV_I915_GEM_MMAP_GTT:
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retval = i915_gem_mmap_gtt_ioctl(main_device, inp, file);
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break;
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case SRV_FBINFO:
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retval = i915_fbinfo(inp);
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break;
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case SRV_I915_GEM_EXECBUFFER2:
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retval = i915_gem_execbuffer2(main_device, inp, file);
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break;
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case SRV_MASK_UPDATE:
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retval = i915_mask_update(main_device, inp, file);
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break;
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};
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return retval;
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}
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#define PCI_CLASS_REVISION 0x08
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#define PCI_CLASS_DISPLAY_VGA 0x0300
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#define PCI_CLASS_BRIDGE_HOST 0x0600
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#define PCI_CLASS_BRIDGE_ISA 0x0601
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int pci_scan_filter(u32_t id, u32_t busnr, u32_t devfn)
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{
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u16_t vendor, device;
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u32_t class;
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int ret = 0;
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vendor = id & 0xffff;
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device = (id >> 16) & 0xffff;
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if(vendor == 0x8086)
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{
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class = PciRead32(busnr, devfn, PCI_CLASS_REVISION);
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class >>= 16;
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if( (class == PCI_CLASS_DISPLAY_VGA) ||
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(class == PCI_CLASS_BRIDGE_HOST) ||
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(class == PCI_CLASS_BRIDGE_ISA))
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ret = 1;
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}
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return ret;
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};
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static char* parse_path(char *p, char *log)
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{
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char c;
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while( (c = *p++) == ' ');
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p--;
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while( (c = *log++ = *p++) && (c != ' '));
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*log = 0;
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return p;
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};
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void parse_cmdline(char *cmdline, char *log)
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{
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char *p = cmdline;
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char c = *p++;
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while( c )
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{
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if( c == '-')
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{
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switch(*p++)
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{
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case 'l':
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p = parse_path(p, log);
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break;
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};
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};
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c = *p++;
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};
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};
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static inline void __cpuid(unsigned int *eax, unsigned int *ebx,
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unsigned int *ecx, unsigned int *edx)
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{
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/* ecx is often an input as well as an output. */
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asm volatile("cpuid"
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: "=a" (*eax),
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"=b" (*ebx),
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"=c" (*ecx),
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"=d" (*edx)
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: "0" (*eax), "2" (*ecx)
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: "memory");
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}
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static inline void cpuid(unsigned int op,
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unsigned int *eax, unsigned int *ebx,
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unsigned int *ecx, unsigned int *edx)
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{
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*eax = op;
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*ecx = 0;
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__cpuid(eax, ebx, ecx, edx);
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}
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void cpu_detect()
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{
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u32 junk, tfms, cap0, misc;
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cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
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if (cap0 & (1<<19))
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{
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x86_clflush_size = ((misc >> 8) & 0xff) * 8;
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}
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tsc_khz = (unsigned int)(GetCpuFreq()/1000);
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}
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int get_driver_caps(hwcaps_t *caps)
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{
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int ret = 0;
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switch(caps->idx)
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{
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case 0:
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caps->opt[0] = 0;
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caps->opt[1] = 0;
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break;
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case 1:
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caps->cap1.max_tex_width = 4096;
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caps->cap1.max_tex_height = 4096;
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break;
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default:
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ret = 1;
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};
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caps->idx = 1;
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return ret;
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}
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void get_pci_info(struct pci_device *dev)
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{
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struct pci_dev *pdev = main_device->pdev;
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memset(dev, sizeof(*dev), 0);
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dev->domain = 0;
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dev->bus = pdev->busnr;
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dev->dev = pdev->devfn >> 3;
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dev->func = pdev->devfn & 7;
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dev->vendor_id = pdev->vendor;
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dev->device_id = pdev->device;
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dev->revision = pdev->revision;
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};
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