733 lines
23 KiB
C
733 lines
23 KiB
C
/*
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* Copyright 2010 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Alex Deucher <alexander.deucher@amd.com>
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*/
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#include <drm/drmP.h>
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#include <drm/radeon_drm.h>
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#include "radeon.h"
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#include "evergreend.h"
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#include "evergreen_blit_shaders.h"
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#include "cayman_blit_shaders.h"
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#include "radeon_blit_common.h"
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/* emits 17 */
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static void
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set_render_target(struct radeon_device *rdev, int format,
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int w, int h, u64 gpu_addr)
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{
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struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
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u32 cb_color_info;
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int pitch, slice;
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h = ALIGN(h, 8);
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if (h < 8)
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h = 8;
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cb_color_info = CB_FORMAT(format) |
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CB_SOURCE_FORMAT(CB_SF_EXPORT_NORM) |
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CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
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pitch = (w / 8) - 1;
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slice = ((w * h) / 64) - 1;
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radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 15));
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radeon_ring_write(ring, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_START) >> 2);
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radeon_ring_write(ring, gpu_addr >> 8);
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radeon_ring_write(ring, pitch);
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radeon_ring_write(ring, slice);
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, cb_color_info);
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, (w - 1) | ((h - 1) << 16));
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, 0);
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}
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/* emits 5dw */
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static void
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cp_set_surface_sync(struct radeon_device *rdev,
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u32 sync_type, u32 size,
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u64 mc_addr)
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{
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struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
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u32 cp_coher_size;
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if (size == 0xffffffff)
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cp_coher_size = 0xffffffff;
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else
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cp_coher_size = ((size + 255) >> 8);
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if (rdev->family >= CHIP_CAYMAN) {
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/* CP_COHER_CNTL2 has to be set manually when submitting a surface_sync
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* to the RB directly. For IBs, the CP programs this as part of the
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* surface_sync packet.
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*/
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radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
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radeon_ring_write(ring, (0x85e8 - PACKET3_SET_CONFIG_REG_START) >> 2);
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radeon_ring_write(ring, 0); /* CP_COHER_CNTL2 */
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}
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radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
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radeon_ring_write(ring, sync_type);
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radeon_ring_write(ring, cp_coher_size);
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radeon_ring_write(ring, mc_addr >> 8);
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radeon_ring_write(ring, 10); /* poll interval */
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}
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/* emits 11dw + 1 surface sync = 16dw */
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static void
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set_shaders(struct radeon_device *rdev)
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{
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struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
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u64 gpu_addr;
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/* VS */
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gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
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radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 3));
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radeon_ring_write(ring, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_START) >> 2);
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radeon_ring_write(ring, gpu_addr >> 8);
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radeon_ring_write(ring, 2);
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radeon_ring_write(ring, 0);
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/* PS */
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gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset;
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radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 4));
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radeon_ring_write(ring, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_START) >> 2);
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radeon_ring_write(ring, gpu_addr >> 8);
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radeon_ring_write(ring, 1);
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, 2);
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gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
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cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);
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}
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/* emits 10 + 1 sync (5) = 15 */
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static void
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set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
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{
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struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
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u32 sq_vtx_constant_word2, sq_vtx_constant_word3;
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/* high addr, stride */
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sq_vtx_constant_word2 = SQ_VTXC_BASE_ADDR_HI(upper_32_bits(gpu_addr) & 0xff) |
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SQ_VTXC_STRIDE(16);
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#ifdef __BIG_ENDIAN
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sq_vtx_constant_word2 |= SQ_VTXC_ENDIAN_SWAP(SQ_ENDIAN_8IN32);
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#endif
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/* xyzw swizzles */
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sq_vtx_constant_word3 = SQ_VTCX_SEL_X(SQ_SEL_X) |
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SQ_VTCX_SEL_Y(SQ_SEL_Y) |
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SQ_VTCX_SEL_Z(SQ_SEL_Z) |
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SQ_VTCX_SEL_W(SQ_SEL_W);
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radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 8));
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radeon_ring_write(ring, 0x580);
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radeon_ring_write(ring, gpu_addr & 0xffffffff);
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radeon_ring_write(ring, 48 - 1); /* size */
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radeon_ring_write(ring, sq_vtx_constant_word2);
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radeon_ring_write(ring, sq_vtx_constant_word3);
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, S__SQ_CONSTANT_TYPE(SQ_TEX_VTX_VALID_BUFFER));
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if ((rdev->family == CHIP_CEDAR) ||
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(rdev->family == CHIP_PALM) ||
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(rdev->family == CHIP_SUMO) ||
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(rdev->family == CHIP_SUMO2) ||
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(rdev->family == CHIP_CAICOS))
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cp_set_surface_sync(rdev,
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PACKET3_TC_ACTION_ENA, 48, gpu_addr);
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else
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cp_set_surface_sync(rdev,
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PACKET3_VC_ACTION_ENA, 48, gpu_addr);
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}
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/* emits 10 */
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static void
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set_tex_resource(struct radeon_device *rdev,
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int format, int w, int h, int pitch,
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u64 gpu_addr, u32 size)
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{
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struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
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u32 sq_tex_resource_word0, sq_tex_resource_word1;
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u32 sq_tex_resource_word4, sq_tex_resource_word7;
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if (h < 1)
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h = 1;
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sq_tex_resource_word0 = TEX_DIM(SQ_TEX_DIM_2D);
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sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 6) |
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((w - 1) << 18));
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sq_tex_resource_word1 = ((h - 1) << 0) |
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TEX_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
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/* xyzw swizzles */
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sq_tex_resource_word4 = TEX_DST_SEL_X(SQ_SEL_X) |
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TEX_DST_SEL_Y(SQ_SEL_Y) |
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TEX_DST_SEL_Z(SQ_SEL_Z) |
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TEX_DST_SEL_W(SQ_SEL_W);
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sq_tex_resource_word7 = format |
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S__SQ_CONSTANT_TYPE(SQ_TEX_VTX_VALID_TEXTURE);
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cp_set_surface_sync(rdev,
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PACKET3_TC_ACTION_ENA, size, gpu_addr);
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radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 8));
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, sq_tex_resource_word0);
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radeon_ring_write(ring, sq_tex_resource_word1);
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radeon_ring_write(ring, gpu_addr >> 8);
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radeon_ring_write(ring, gpu_addr >> 8);
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radeon_ring_write(ring, sq_tex_resource_word4);
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, sq_tex_resource_word7);
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}
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/* emits 12 */
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static void
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set_scissors(struct radeon_device *rdev, int x1, int y1,
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int x2, int y2)
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{
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struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
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/* workaround some hw bugs */
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if (x2 == 0)
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x1 = 1;
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if (y2 == 0)
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y1 = 1;
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if (rdev->family >= CHIP_CAYMAN) {
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if ((x2 == 1) && (y2 == 1))
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x2 = 2;
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}
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radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
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radeon_ring_write(ring, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
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radeon_ring_write(ring, (x1 << 0) | (y1 << 16));
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radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
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radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
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radeon_ring_write(ring, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
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radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31));
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radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
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radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
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radeon_ring_write(ring, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
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radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31));
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radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
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}
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/* emits 10 */
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static void
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draw_auto(struct radeon_device *rdev)
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{
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struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
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radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
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radeon_ring_write(ring, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_START) >> 2);
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radeon_ring_write(ring, DI_PT_RECTLIST);
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radeon_ring_write(ring, PACKET3(PACKET3_INDEX_TYPE, 0));
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radeon_ring_write(ring,
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#ifdef __BIG_ENDIAN
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(2 << 2) |
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#endif
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DI_INDEX_SIZE_16_BIT);
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radeon_ring_write(ring, PACKET3(PACKET3_NUM_INSTANCES, 0));
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radeon_ring_write(ring, 1);
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radeon_ring_write(ring, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));
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radeon_ring_write(ring, 3);
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radeon_ring_write(ring, DI_SRC_SEL_AUTO_INDEX);
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}
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/* emits 39 */
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static void
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set_default_state(struct radeon_device *rdev)
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{
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struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
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u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2, sq_gpr_resource_mgmt_3;
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u32 sq_thread_resource_mgmt, sq_thread_resource_mgmt_2;
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u32 sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2, sq_stack_resource_mgmt_3;
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int num_ps_gprs, num_vs_gprs, num_temp_gprs;
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int num_gs_gprs, num_es_gprs, num_hs_gprs, num_ls_gprs;
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int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;
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int num_hs_threads, num_ls_threads;
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int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
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int num_hs_stack_entries, num_ls_stack_entries;
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u64 gpu_addr;
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int dwords;
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/* set clear context state */
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radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
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radeon_ring_write(ring, 0);
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if (rdev->family < CHIP_CAYMAN) {
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switch (rdev->family) {
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case CHIP_CEDAR:
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default:
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num_ps_gprs = 93;
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num_vs_gprs = 46;
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num_temp_gprs = 4;
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num_gs_gprs = 31;
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num_es_gprs = 31;
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num_hs_gprs = 23;
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num_ls_gprs = 23;
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num_ps_threads = 96;
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num_vs_threads = 16;
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num_gs_threads = 16;
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num_es_threads = 16;
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num_hs_threads = 16;
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num_ls_threads = 16;
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num_ps_stack_entries = 42;
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num_vs_stack_entries = 42;
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num_gs_stack_entries = 42;
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num_es_stack_entries = 42;
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num_hs_stack_entries = 42;
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num_ls_stack_entries = 42;
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break;
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case CHIP_REDWOOD:
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num_ps_gprs = 93;
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num_vs_gprs = 46;
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num_temp_gprs = 4;
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num_gs_gprs = 31;
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num_es_gprs = 31;
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num_hs_gprs = 23;
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num_ls_gprs = 23;
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num_ps_threads = 128;
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num_vs_threads = 20;
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num_gs_threads = 20;
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num_es_threads = 20;
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num_hs_threads = 20;
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num_ls_threads = 20;
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num_ps_stack_entries = 42;
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num_vs_stack_entries = 42;
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num_gs_stack_entries = 42;
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num_es_stack_entries = 42;
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num_hs_stack_entries = 42;
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num_ls_stack_entries = 42;
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break;
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case CHIP_JUNIPER:
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num_ps_gprs = 93;
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num_vs_gprs = 46;
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num_temp_gprs = 4;
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num_gs_gprs = 31;
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num_es_gprs = 31;
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num_hs_gprs = 23;
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num_ls_gprs = 23;
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num_ps_threads = 128;
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num_vs_threads = 20;
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num_gs_threads = 20;
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num_es_threads = 20;
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num_hs_threads = 20;
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num_ls_threads = 20;
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num_ps_stack_entries = 85;
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num_vs_stack_entries = 85;
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num_gs_stack_entries = 85;
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num_es_stack_entries = 85;
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num_hs_stack_entries = 85;
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num_ls_stack_entries = 85;
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break;
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case CHIP_CYPRESS:
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case CHIP_HEMLOCK:
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num_ps_gprs = 93;
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num_vs_gprs = 46;
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num_temp_gprs = 4;
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num_gs_gprs = 31;
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num_es_gprs = 31;
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num_hs_gprs = 23;
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num_ls_gprs = 23;
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num_ps_threads = 128;
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num_vs_threads = 20;
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num_gs_threads = 20;
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num_es_threads = 20;
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num_hs_threads = 20;
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num_ls_threads = 20;
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num_ps_stack_entries = 85;
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num_vs_stack_entries = 85;
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num_gs_stack_entries = 85;
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num_es_stack_entries = 85;
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num_hs_stack_entries = 85;
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num_ls_stack_entries = 85;
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break;
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case CHIP_PALM:
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num_ps_gprs = 93;
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num_vs_gprs = 46;
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num_temp_gprs = 4;
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num_gs_gprs = 31;
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num_es_gprs = 31;
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num_hs_gprs = 23;
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num_ls_gprs = 23;
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num_ps_threads = 96;
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num_vs_threads = 16;
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num_gs_threads = 16;
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num_es_threads = 16;
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num_hs_threads = 16;
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num_ls_threads = 16;
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num_ps_stack_entries = 42;
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num_vs_stack_entries = 42;
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num_gs_stack_entries = 42;
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num_es_stack_entries = 42;
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num_hs_stack_entries = 42;
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num_ls_stack_entries = 42;
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break;
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case CHIP_SUMO:
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num_ps_gprs = 93;
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num_vs_gprs = 46;
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num_temp_gprs = 4;
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num_gs_gprs = 31;
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num_es_gprs = 31;
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num_hs_gprs = 23;
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num_ls_gprs = 23;
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num_ps_threads = 96;
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num_vs_threads = 25;
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num_gs_threads = 25;
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num_es_threads = 25;
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num_hs_threads = 25;
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num_ls_threads = 25;
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num_ps_stack_entries = 42;
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num_vs_stack_entries = 42;
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num_gs_stack_entries = 42;
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num_es_stack_entries = 42;
|
|
num_hs_stack_entries = 42;
|
|
num_ls_stack_entries = 42;
|
|
break;
|
|
case CHIP_SUMO2:
|
|
num_ps_gprs = 93;
|
|
num_vs_gprs = 46;
|
|
num_temp_gprs = 4;
|
|
num_gs_gprs = 31;
|
|
num_es_gprs = 31;
|
|
num_hs_gprs = 23;
|
|
num_ls_gprs = 23;
|
|
num_ps_threads = 96;
|
|
num_vs_threads = 25;
|
|
num_gs_threads = 25;
|
|
num_es_threads = 25;
|
|
num_hs_threads = 25;
|
|
num_ls_threads = 25;
|
|
num_ps_stack_entries = 85;
|
|
num_vs_stack_entries = 85;
|
|
num_gs_stack_entries = 85;
|
|
num_es_stack_entries = 85;
|
|
num_hs_stack_entries = 85;
|
|
num_ls_stack_entries = 85;
|
|
break;
|
|
case CHIP_BARTS:
|
|
num_ps_gprs = 93;
|
|
num_vs_gprs = 46;
|
|
num_temp_gprs = 4;
|
|
num_gs_gprs = 31;
|
|
num_es_gprs = 31;
|
|
num_hs_gprs = 23;
|
|
num_ls_gprs = 23;
|
|
num_ps_threads = 128;
|
|
num_vs_threads = 20;
|
|
num_gs_threads = 20;
|
|
num_es_threads = 20;
|
|
num_hs_threads = 20;
|
|
num_ls_threads = 20;
|
|
num_ps_stack_entries = 85;
|
|
num_vs_stack_entries = 85;
|
|
num_gs_stack_entries = 85;
|
|
num_es_stack_entries = 85;
|
|
num_hs_stack_entries = 85;
|
|
num_ls_stack_entries = 85;
|
|
break;
|
|
case CHIP_TURKS:
|
|
num_ps_gprs = 93;
|
|
num_vs_gprs = 46;
|
|
num_temp_gprs = 4;
|
|
num_gs_gprs = 31;
|
|
num_es_gprs = 31;
|
|
num_hs_gprs = 23;
|
|
num_ls_gprs = 23;
|
|
num_ps_threads = 128;
|
|
num_vs_threads = 20;
|
|
num_gs_threads = 20;
|
|
num_es_threads = 20;
|
|
num_hs_threads = 20;
|
|
num_ls_threads = 20;
|
|
num_ps_stack_entries = 42;
|
|
num_vs_stack_entries = 42;
|
|
num_gs_stack_entries = 42;
|
|
num_es_stack_entries = 42;
|
|
num_hs_stack_entries = 42;
|
|
num_ls_stack_entries = 42;
|
|
break;
|
|
case CHIP_CAICOS:
|
|
num_ps_gprs = 93;
|
|
num_vs_gprs = 46;
|
|
num_temp_gprs = 4;
|
|
num_gs_gprs = 31;
|
|
num_es_gprs = 31;
|
|
num_hs_gprs = 23;
|
|
num_ls_gprs = 23;
|
|
num_ps_threads = 128;
|
|
num_vs_threads = 10;
|
|
num_gs_threads = 10;
|
|
num_es_threads = 10;
|
|
num_hs_threads = 10;
|
|
num_ls_threads = 10;
|
|
num_ps_stack_entries = 42;
|
|
num_vs_stack_entries = 42;
|
|
num_gs_stack_entries = 42;
|
|
num_es_stack_entries = 42;
|
|
num_hs_stack_entries = 42;
|
|
num_ls_stack_entries = 42;
|
|
break;
|
|
}
|
|
|
|
if ((rdev->family == CHIP_CEDAR) ||
|
|
(rdev->family == CHIP_PALM) ||
|
|
(rdev->family == CHIP_SUMO) ||
|
|
(rdev->family == CHIP_SUMO2) ||
|
|
(rdev->family == CHIP_CAICOS))
|
|
sq_config = 0;
|
|
else
|
|
sq_config = VC_ENABLE;
|
|
|
|
sq_config |= (EXPORT_SRC_C |
|
|
CS_PRIO(0) |
|
|
LS_PRIO(0) |
|
|
HS_PRIO(0) |
|
|
PS_PRIO(0) |
|
|
VS_PRIO(1) |
|
|
GS_PRIO(2) |
|
|
ES_PRIO(3));
|
|
|
|
sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) |
|
|
NUM_VS_GPRS(num_vs_gprs) |
|
|
NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
|
|
sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) |
|
|
NUM_ES_GPRS(num_es_gprs));
|
|
sq_gpr_resource_mgmt_3 = (NUM_HS_GPRS(num_hs_gprs) |
|
|
NUM_LS_GPRS(num_ls_gprs));
|
|
sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) |
|
|
NUM_VS_THREADS(num_vs_threads) |
|
|
NUM_GS_THREADS(num_gs_threads) |
|
|
NUM_ES_THREADS(num_es_threads));
|
|
sq_thread_resource_mgmt_2 = (NUM_HS_THREADS(num_hs_threads) |
|
|
NUM_LS_THREADS(num_ls_threads));
|
|
sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
|
|
NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
|
|
sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
|
|
NUM_ES_STACK_ENTRIES(num_es_stack_entries));
|
|
sq_stack_resource_mgmt_3 = (NUM_HS_STACK_ENTRIES(num_hs_stack_entries) |
|
|
NUM_LS_STACK_ENTRIES(num_ls_stack_entries));
|
|
|
|
/* disable dyn gprs */
|
|
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
|
|
radeon_ring_write(ring, (SQ_DYN_GPR_CNTL_PS_FLUSH_REQ - PACKET3_SET_CONFIG_REG_START) >> 2);
|
|
radeon_ring_write(ring, 0);
|
|
|
|
/* setup LDS */
|
|
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
|
|
radeon_ring_write(ring, (SQ_LDS_RESOURCE_MGMT - PACKET3_SET_CONFIG_REG_START) >> 2);
|
|
radeon_ring_write(ring, 0x10001000);
|
|
|
|
/* SQ config */
|
|
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 11));
|
|
radeon_ring_write(ring, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_START) >> 2);
|
|
radeon_ring_write(ring, sq_config);
|
|
radeon_ring_write(ring, sq_gpr_resource_mgmt_1);
|
|
radeon_ring_write(ring, sq_gpr_resource_mgmt_2);
|
|
radeon_ring_write(ring, sq_gpr_resource_mgmt_3);
|
|
radeon_ring_write(ring, 0);
|
|
radeon_ring_write(ring, 0);
|
|
radeon_ring_write(ring, sq_thread_resource_mgmt);
|
|
radeon_ring_write(ring, sq_thread_resource_mgmt_2);
|
|
radeon_ring_write(ring, sq_stack_resource_mgmt_1);
|
|
radeon_ring_write(ring, sq_stack_resource_mgmt_2);
|
|
radeon_ring_write(ring, sq_stack_resource_mgmt_3);
|
|
}
|
|
|
|
/* CONTEXT_CONTROL */
|
|
radeon_ring_write(ring, 0xc0012800);
|
|
radeon_ring_write(ring, 0x80000000);
|
|
radeon_ring_write(ring, 0x80000000);
|
|
|
|
/* SQ_VTX_BASE_VTX_LOC */
|
|
radeon_ring_write(ring, 0xc0026f00);
|
|
radeon_ring_write(ring, 0x00000000);
|
|
radeon_ring_write(ring, 0x00000000);
|
|
radeon_ring_write(ring, 0x00000000);
|
|
|
|
/* SET_SAMPLER */
|
|
radeon_ring_write(ring, 0xc0036e00);
|
|
radeon_ring_write(ring, 0x00000000);
|
|
radeon_ring_write(ring, 0x00000012);
|
|
radeon_ring_write(ring, 0x00000000);
|
|
radeon_ring_write(ring, 0x00000000);
|
|
|
|
/* set to DX10/11 mode */
|
|
radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
|
|
radeon_ring_write(ring, 1);
|
|
|
|
/* emit an IB pointing at default state */
|
|
dwords = ALIGN(rdev->r600_blit.state_len, 0x10);
|
|
gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
|
|
radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
|
|
radeon_ring_write(ring, gpu_addr & 0xFFFFFFFC);
|
|
radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xFF);
|
|
radeon_ring_write(ring, dwords);
|
|
|
|
}
|
|
|
|
int evergreen_blit_init(struct radeon_device *rdev)
|
|
{
|
|
u32 obj_size;
|
|
int i, r, dwords;
|
|
void *ptr;
|
|
u32 packet2s[16];
|
|
int num_packet2s = 0;
|
|
#if 0
|
|
rdev->r600_blit.primitives.set_render_target = set_render_target;
|
|
rdev->r600_blit.primitives.cp_set_surface_sync = cp_set_surface_sync;
|
|
rdev->r600_blit.primitives.set_shaders = set_shaders;
|
|
rdev->r600_blit.primitives.set_vtx_resource = set_vtx_resource;
|
|
rdev->r600_blit.primitives.set_tex_resource = set_tex_resource;
|
|
rdev->r600_blit.primitives.set_scissors = set_scissors;
|
|
rdev->r600_blit.primitives.draw_auto = draw_auto;
|
|
rdev->r600_blit.primitives.set_default_state = set_default_state;
|
|
|
|
rdev->r600_blit.ring_size_common = 8; /* sync semaphore */
|
|
rdev->r600_blit.ring_size_common += 55; /* shaders + def state */
|
|
rdev->r600_blit.ring_size_common += 16; /* fence emit for VB IB */
|
|
rdev->r600_blit.ring_size_common += 5; /* done copy */
|
|
rdev->r600_blit.ring_size_common += 16; /* fence emit for done copy */
|
|
|
|
rdev->r600_blit.ring_size_per_loop = 74;
|
|
if (rdev->family >= CHIP_CAYMAN)
|
|
rdev->r600_blit.ring_size_per_loop += 9; /* additional DWs for surface sync */
|
|
|
|
rdev->r600_blit.max_dim = 16384;
|
|
|
|
rdev->r600_blit.state_offset = 0;
|
|
|
|
if (rdev->family < CHIP_CAYMAN)
|
|
rdev->r600_blit.state_len = evergreen_default_size;
|
|
else
|
|
rdev->r600_blit.state_len = cayman_default_size;
|
|
|
|
dwords = rdev->r600_blit.state_len;
|
|
while (dwords & 0xf) {
|
|
packet2s[num_packet2s++] = cpu_to_le32(PACKET2(0));
|
|
dwords++;
|
|
}
|
|
|
|
obj_size = dwords * 4;
|
|
obj_size = ALIGN(obj_size, 256);
|
|
|
|
rdev->r600_blit.vs_offset = obj_size;
|
|
if (rdev->family < CHIP_CAYMAN)
|
|
obj_size += evergreen_vs_size * 4;
|
|
else
|
|
obj_size += cayman_vs_size * 4;
|
|
obj_size = ALIGN(obj_size, 256);
|
|
|
|
rdev->r600_blit.ps_offset = obj_size;
|
|
if (rdev->family < CHIP_CAYMAN)
|
|
obj_size += evergreen_ps_size * 4;
|
|
else
|
|
obj_size += cayman_ps_size * 4;
|
|
obj_size = ALIGN(obj_size, 256);
|
|
|
|
/* pin copy shader into vram if not already initialized */
|
|
if (!rdev->r600_blit.shader_obj) {
|
|
r = radeon_bo_create(rdev, obj_size, PAGE_SIZE, true,
|
|
RADEON_GEM_DOMAIN_VRAM,
|
|
NULL, &rdev->r600_blit.shader_obj);
|
|
if (r) {
|
|
DRM_ERROR("evergreen failed to allocate shader\n");
|
|
return r;
|
|
}
|
|
|
|
r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
|
|
if (unlikely(r != 0))
|
|
return r;
|
|
r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
|
|
&rdev->r600_blit.shader_gpu_addr);
|
|
radeon_bo_unreserve(rdev->r600_blit.shader_obj);
|
|
if (r) {
|
|
dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
|
|
return r;
|
|
}
|
|
}
|
|
|
|
DRM_DEBUG("evergreen blit allocated bo %08x vs %08x ps %08x\n",
|
|
obj_size,
|
|
rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset);
|
|
|
|
r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
|
|
if (unlikely(r != 0))
|
|
return r;
|
|
r = radeon_bo_kmap(rdev->r600_blit.shader_obj, &ptr);
|
|
if (r) {
|
|
DRM_ERROR("failed to map blit object %d\n", r);
|
|
return r;
|
|
}
|
|
|
|
if (rdev->family < CHIP_CAYMAN) {
|
|
memcpy(ptr + rdev->r600_blit.state_offset,
|
|
evergreen_default_state, rdev->r600_blit.state_len * 4);
|
|
|
|
if (num_packet2s)
|
|
memcpy(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4),
|
|
packet2s, num_packet2s * 4);
|
|
for (i = 0; i < evergreen_vs_size; i++)
|
|
*(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(evergreen_vs[i]);
|
|
for (i = 0; i < evergreen_ps_size; i++)
|
|
*(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(evergreen_ps[i]);
|
|
} else {
|
|
memcpy(ptr + rdev->r600_blit.state_offset,
|
|
cayman_default_state, rdev->r600_blit.state_len * 4);
|
|
|
|
if (num_packet2s)
|
|
memcpy(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4),
|
|
packet2s, num_packet2s * 4);
|
|
for (i = 0; i < cayman_vs_size; i++)
|
|
*(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(cayman_vs[i]);
|
|
for (i = 0; i < cayman_ps_size; i++)
|
|
*(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(cayman_ps[i]);
|
|
}
|
|
radeon_bo_kunmap(rdev->r600_blit.shader_obj);
|
|
radeon_bo_unreserve(rdev->r600_blit.shader_obj);
|
|
|
|
radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
|
|
|
|
#endif
|
|
|
|
return 0;
|
|
}
|