512 lines
13 KiB
C
512 lines
13 KiB
C
/*
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* Copyright © 2010 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Xiang Haihao <haihao.xiang@intel.com>
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*
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*/
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#ifndef __I965_POST_PROCESSING_H__
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#define __I965_POST_PROCESSING_H__
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#define MAX_PP_SURFACES 48
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#define I965_PP_FLAG_TOP_FIELD 1
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#define I965_PP_FLAG_BOTTOM_FIELD 2
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#define I965_PP_FLAG_AVS 4
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#define I965_PP_FLAG_DEINTERLACING 8
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enum
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{
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PP_NULL = 0,
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PP_NV12_LOAD_SAVE_N12,
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PP_NV12_LOAD_SAVE_PL3,
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PP_PL3_LOAD_SAVE_N12,
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PP_PL3_LOAD_SAVE_PL3,
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PP_NV12_SCALING,
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PP_NV12_AVS,
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PP_NV12_DNDI,
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PP_NV12_DN,
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PP_NV12_LOAD_SAVE_PA,
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PP_PL3_LOAD_SAVE_PA,
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PP_PA_LOAD_SAVE_NV12,
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NUM_PP_MODULES,
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};
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struct pp_load_save_context
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{
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int dest_x;
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int dest_y;
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int dest_w;
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int dest_h;
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};
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struct pp_scaling_context
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{
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int dest_x; /* in pixel */
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int dest_y; /* in pixel */
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int dest_w;
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int dest_h;
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int src_normalized_x;
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int src_normalized_y;
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};
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struct pp_avs_context
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{
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int dest_x; /* in pixel */
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int dest_y; /* in pixel */
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int dest_w;
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int dest_h;
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int src_normalized_x;
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int src_normalized_y;
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int src_w;
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int src_h;
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};
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struct pp_dndi_context
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{
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int dest_w;
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int dest_h;
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};
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struct pp_dn_context
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{
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int dest_w;
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int dest_h;
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};
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struct i965_post_processing_context;
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struct pp_module
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{
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struct i965_kernel kernel;
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/* others */
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VAStatus (*initialize)(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
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const struct i965_surface *src_surface,
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const VARectangle *src_rect,
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struct i965_surface *dst_surface,
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const VARectangle *dst_rect,
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void *filter_param);
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};
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struct pp_static_parameter
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{
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struct {
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/* Procamp r1.0 */
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float procamp_constant_c0;
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/* Load and Same r1.1 */
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unsigned int source_packed_y_offset:8;
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unsigned int source_packed_u_offset:8;
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unsigned int source_packed_v_offset:8;
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unsigned int pad0:8;
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union {
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/* Load and Save r1.2 */
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struct {
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unsigned int destination_packed_y_offset:8;
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unsigned int destination_packed_u_offset:8;
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unsigned int destination_packed_v_offset:8;
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unsigned int pad0:8;
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} load_and_save;
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/* CSC r1.2 */
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struct {
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unsigned int destination_rgb_format:8;
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unsigned int pad0:24;
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} csc;
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} r1_2;
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/* Procamp r1.3 */
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float procamp_constant_c1;
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/* Procamp r1.4 */
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float procamp_constant_c2;
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/* DI r1.5 */
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unsigned int statistics_surface_picth:16; /* Devided by 2 */
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unsigned int pad1:16;
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union {
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/* DI r1.6 */
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struct {
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unsigned int pad0:24;
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unsigned int top_field_first:8;
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} di;
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/* AVS/Scaling r1.6 */
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float normalized_video_y_scaling_step;
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} r1_6;
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/* Procamp r1.7 */
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float procamp_constant_c5;
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} grf1;
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struct {
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/* Procamp r2.0 */
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float procamp_constant_c3;
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/* MBZ r2.1*/
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unsigned int pad0;
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/* WG+CSC r2.2 */
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float wg_csc_constant_c4;
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/* WG+CSC r2.3 */
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float wg_csc_constant_c8;
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/* Procamp r2.4 */
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float procamp_constant_c4;
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/* MBZ r2.5 */
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unsigned int pad1;
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/* MBZ r2.6 */
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unsigned int pad2;
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/* WG+CSC r2.7 */
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float wg_csc_constant_c9;
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} grf2;
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struct {
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/* WG+CSC r3.0 */
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float wg_csc_constant_c0;
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/* Blending r3.1 */
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float scaling_step_ratio;
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/* Blending r3.2 */
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float normalized_alpha_y_scaling;
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/* WG+CSC r3.3 */
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float wg_csc_constant_c4;
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/* WG+CSC r3.4 */
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float wg_csc_constant_c1;
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/* ALL r3.5 */
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int horizontal_origin_offset:16;
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int vertical_origin_offset:16;
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/* Shared r3.6*/
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union {
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/* Color filll */
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unsigned int color_pixel;
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/* WG+CSC */
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float wg_csc_constant_c2;
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} r3_6;
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/* WG+CSC r3.7 */
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float wg_csc_constant_c3;
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} grf3;
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struct {
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/* WG+CSC r4.0 */
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float wg_csc_constant_c6;
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/* ALL r4.1 MBZ ???*/
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unsigned int pad0;
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/* Shared r4.2 */
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union {
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/* AVS */
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struct {
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unsigned int pad1:15;
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unsigned int nlas:1;
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unsigned int pad2:16;
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} avs;
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/* DI */
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struct {
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unsigned int motion_history_coefficient_m2:8;
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unsigned int motion_history_coefficient_m1:8;
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unsigned int pad0:16;
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} di;
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} r4_2;
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/* WG+CSC r4.3 */
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float wg_csc_constant_c7;
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/* WG+CSC r4.4 */
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float wg_csc_constant_c10;
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/* AVS r4.5 */
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float source_video_frame_normalized_horizontal_origin;
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/* MBZ r4.6 */
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unsigned int pad1;
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/* WG+CSC r4.7 */
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float wg_csc_constant_c11;
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} grf4;
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};
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struct pp_inline_parameter
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{
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struct {
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/* ALL r5.0 */
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int destination_block_horizontal_origin:16;
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int destination_block_vertical_origin:16;
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/* Shared r5.1 */
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union {
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/* AVS/Scaling */
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float source_surface_block_normalized_horizontal_origin;
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/* FMD */
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struct {
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unsigned int variance_surface_vertical_origin:16;
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unsigned int pad0:16;
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} fmd;
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} r5_1;
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/* AVS/Scaling r5.2 */
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float source_surface_block_normalized_vertical_origin;
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/* Alpha r5.3 */
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float alpha_surface_block_normalized_horizontal_origin;
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/* Alpha r5.4 */
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float alpha_surface_block_normalized_vertical_origin;
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/* Alpha r5.5 */
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unsigned int alpha_mask_x:16;
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unsigned int alpha_mask_y:8;
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unsigned int block_count_x:8;
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/* r5.6 */
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/* we only support M*1 or 1*N block partitation now.
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* -- it means asm code only need update this mask from grf6 for the last block
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*/
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unsigned int block_horizontal_mask:16;
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unsigned int block_vertical_mask:8;
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unsigned int number_blocks:8;
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/* AVS/Scaling r5.7 */
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float normalized_video_x_scaling_step;
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} grf5;
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struct {
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/* AVS r6.0 */
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float video_step_delta;
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/* r6.1 */ // sizeof(int) == 4?
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unsigned int block_horizontal_mask_right:16;
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unsigned int block_vertical_mask_bottom:8;
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unsigned int pad1:8;
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/* r6.2 */
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unsigned int block_horizontal_mask_middle:16;
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unsigned int pad2:16;
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/* r6.3-r6.7 */
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unsigned int padx[5];
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} grf6;
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};
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struct gen7_pp_static_parameter
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{
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struct {
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/* r1.0-r1.5 */
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unsigned int padx[6];
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/* r1.6 */
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unsigned int di_statistics_surface_pitch_div2:16;
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unsigned int di_statistics_surface_height_div4:16;
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/* r1.7 */
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unsigned int di_top_field_first:8;
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unsigned int pad0:16;
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unsigned int pointer_to_inline_parameter:8; /* value: 7 */
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} grf1;
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struct {
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/* r2.0 */
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unsigned int pad3;
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/* r2.1 */
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unsigned int pad2:16;
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unsigned int save_avs_rgb_swap:1; /* 0: RGB, 1: BGR */
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unsigned int avs_wa_enable:1; /* must enabled for GEN7 */
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unsigned int pad1:1;
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unsigned int avs_wa_width:13;
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/* 2.2 */
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float avs_wa_one_div_256_width;
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/* 2.3 */
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float avs_wa_five_div_256_width;
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/* 2.4 - 2.6 */
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unsigned int padx[3];
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/* r2.7 */
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unsigned int di_destination_packed_y_component_offset:8;
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unsigned int di_destination_packed_u_component_offset:8;
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unsigned int di_destination_packed_v_component_offset:8;
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unsigned int pad0:8;
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} grf2;
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struct {
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float sampler_load_horizontal_scaling_step_ratio;
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unsigned int padx[7];
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} grf3;
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struct {
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float sampler_load_vertical_scaling_step;
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unsigned int pad0;
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unsigned int di_hoffset_svf_from_dvf:16;
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unsigned int di_voffset_svf_from_dvf:16;
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unsigned int padx[5];
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} grf4;
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struct {
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float sampler_load_vertical_frame_origin;
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unsigned int padx[7];
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} grf5;
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struct {
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float sampler_load_horizontal_frame_origin;
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unsigned int padx[7];
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} grf6;
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};
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struct gen7_pp_inline_parameter
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{
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struct {
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/* r7.0 */
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unsigned int destination_block_horizontal_origin:16;
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unsigned int destination_block_vertical_origin:16;
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/* r7.1: 0xffffffff */
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unsigned int constant_0;
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/* r7.2 */
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unsigned int pad0;
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/* r7.3 */
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unsigned int pad1;
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/* r7.4 */
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float sampler_load_main_video_x_scaling_step;
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/* r7.5 */
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unsigned int pad2;
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/* r7.6: must be zero */
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unsigned int avs_vertical_block_number;
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/* r7.7: 0 */
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unsigned int group_id_number;
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} grf7;
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struct {
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unsigned int padx[8];
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} grf8;
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};
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struct i965_post_processing_context
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{
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int current_pp;
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struct pp_module pp_modules[NUM_PP_MODULES];
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void *pp_static_parameter;
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void *pp_inline_parameter;
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struct {
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dri_bo *bo;
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} surface_state_binding_table;
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struct {
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dri_bo *bo;
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} curbe;
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struct {
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dri_bo *bo;
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int num_interface_descriptors;
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} idrt;
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struct {
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dri_bo *bo;
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} vfe_state;
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struct {
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dri_bo *bo;
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dri_bo *bo_8x8;
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dri_bo *bo_8x8_uv;
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} sampler_state_table;
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struct {
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unsigned int size;
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unsigned int vfe_start;
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unsigned int cs_start;
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unsigned int num_vfe_entries;
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unsigned int num_cs_entries;
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unsigned int size_vfe_entry;
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unsigned int size_cs_entry;
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} urb;
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struct {
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dri_bo *bo;
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} stmm;
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union {
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struct pp_load_save_context pp_load_save_context;
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struct pp_scaling_context pp_scaling_context;
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struct pp_avs_context pp_avs_context;
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struct pp_dndi_context pp_dndi_context;
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struct pp_dn_context pp_dn_context;
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} private_context;
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int (*pp_x_steps)(void *private_context);
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int (*pp_y_steps)(void *private_context);
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int (*pp_set_block_parameter)(struct i965_post_processing_context *pp_context, int x, int y);
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struct intel_batchbuffer *batch;
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unsigned int block_horizontal_mask_left:16;
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unsigned int block_horizontal_mask_right:16;
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unsigned int block_vertical_mask_bottom:8;
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/* video process based on hsw vebox */
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struct intel_vebox_context *pp_vebox_context;
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};
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VASurfaceID
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i965_post_processing(
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VADriverContextP ctx,
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VASurfaceID surface,
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const VARectangle *src_rect,
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const VARectangle *dst_rect,
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unsigned int flags,
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int *has_done_scaling
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);
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VAStatus
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i965_image_processing(VADriverContextP ctx,
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const struct i965_surface *src_surface,
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const VARectangle *src_rect,
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struct i965_surface *dst_surface,
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const VARectangle *dst_rect);
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Bool
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i965_post_processing_terminate(VADriverContextP ctx);
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Bool
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i965_post_processing_init(VADriverContextP ctx);
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#endif /* __I965_POST_PROCESSING_H__ */
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