452 lines
12 KiB
C
452 lines
12 KiB
C
/* cr16.h -- Header file for CR16 opcode and register tables.
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Copyright (C) 2007-2015 Free Software Foundation, Inc.
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Contributed by M R Swami Reddy
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This file is part of GAS, GDB and the GNU binutils.
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GAS, GDB, and GNU binutils is free software; you can redistribute it
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and/or modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation; either version 3, or (at your
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option) any later version.
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GAS, GDB, and GNU binutils are distributed in the hope that they will be
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useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software Foundation,
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Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
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#ifndef _CR16_H_
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#define _CR16_H_
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/* CR16 core Registers :
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The enums are used as indices to CR16 registers table (cr16_regtab).
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Therefore, order MUST be preserved. */
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typedef enum
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{
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/* 16-bit general purpose registers. */
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r0, r1, r2, r3,
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r4, r5, r6, r7,
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r8, r9, r10, r11,
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r12_L = 12, r13_L = 13, ra = 14, sp_L = 15,
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/* 32-bit general purpose registers. */
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r12 = 12, r13 = 13, r14 = 14, r15 = 15,
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era = 14, sp = 15, RA,
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/* Not a register. */
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nullregister,
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MAX_REG
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}
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reg;
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/* CR16 processor registers and special registers :
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The enums are used as indices to CR16 processor registers table
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(cr16_pregtab). Therefore, order MUST be preserved. */
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typedef enum
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{
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/* processor registers. */
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dbs = MAX_REG,
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dsr, dcrl, dcrh,
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car0l, car0h, car1l, car1h,
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cfg, psr, intbasel, intbaseh,
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ispl, isph, uspl, usph,
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dcr = dcrl,
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car0 = car0l,
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car1 = car1l,
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intbase = intbasel,
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isp = ispl,
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usp = uspl,
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/* Not a processor register. */
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nullpregister = usph + 1,
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MAX_PREG
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}
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preg;
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/* CR16 Register types. */
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typedef enum
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{
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CR16_R_REGTYPE, /* r<N> */
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CR16_RP_REGTYPE, /* reg pair */
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CR16_P_REGTYPE /* Processor register */
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}
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reg_type;
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/* CR16 argument types :
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The argument types correspond to instructions operands
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Argument types :
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r - register
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rp - register pair
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c - constant
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i - immediate
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idxr - index with register
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idxrp - index with register pair
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rbase - register base
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rpbase - register pair base
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pr - processor register. */
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typedef enum
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{
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arg_r,
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arg_c,
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arg_cr,
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arg_crp,
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arg_ic,
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arg_icr,
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arg_idxr,
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arg_idxrp,
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arg_rbase,
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arg_rpbase,
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arg_rp,
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arg_pr,
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arg_prp,
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arg_cc,
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arg_ra,
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/* Not an argument. */
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nullargs
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}
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argtype;
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/* CR16 operand types:The operand types correspond to instructions operands. */
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typedef enum
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{
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dummy,
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/* N-bit signed immediate. */
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imm3, imm4, imm5, imm6, imm16, imm20, imm32,
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/* N-bit unsigned immediate. */
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uimm3, uimm3_1, uimm4, uimm4_1, uimm5, uimm16, uimm20, uimm32,
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/* N-bit signed displacement. */
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disps5, disps17, disps25,
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/* N-bit unsigned displacement. */
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dispe9,
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/* N-bit absolute address. */
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abs20, abs24,
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/* Register relative. */
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rra, rbase, rbase_disps20, rbase_dispe20,
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/* Register pair relative. */
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rpbase_disps0, rpbase_dispe4, rpbase_disps4, rpbase_disps16,
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rpbase_disps20, rpbase_dispe20,
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/* Register index. */
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rindex7_abs20, rindex8_abs20,
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/* Register pair index. */
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rpindex_disps0, rpindex_disps14, rpindex_disps20,
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/* register. */
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regr,
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/* register pair. */
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regp,
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/* processor register. */
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pregr,
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/* processor register 32 bit. */
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pregrp,
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/* condition code - 4 bit. */
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cc,
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/* Not an operand. */
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nulloperand,
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/* Maximum supported operand. */
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MAX_OPRD
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}
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operand_type;
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/* CR16 instruction types. */
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#define NO_TYPE_INS 0
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#define ARITH_INS 1
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#define LD_STOR_INS 2
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#define BRANCH_INS 3
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#define ARITH_BYTE_INS 4
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#define SHIFT_INS 5
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#define BRANCH_NEQ_INS 6
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#define LD_STOR_INS_INC 7
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#define STOR_IMM_INS 8
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#define CSTBIT_INS 9
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/* Maximum value supported for instruction types. */
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#define CR16_INS_MAX (1 << 4)
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/* Mask to record an instruction type. */
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#define CR16_INS_MASK (CR16_INS_MAX - 1)
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/* Return instruction type, given instruction's attributes. */
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#define CR16_INS_TYPE(attr) ((attr) & CR16_INS_MASK)
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/* Indicates whether this instruction has a register list as parameter. */
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#define REG_LIST CR16_INS_MAX
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/* The operands in binary and assembly are placed in reverse order.
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load - (REVERSE_MATCH)/store - (! REVERSE_MATCH). */
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#define REVERSE_MATCH (1 << 5)
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/* Printing formats, where the instruction prefix isn't consecutive. */
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#define FMT_1 (1 << 9) /* 0xF0F00000 */
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#define FMT_2 (1 << 10) /* 0xFFF0FF00 */
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#define FMT_3 (1 << 11) /* 0xFFF00F00 */
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#define FMT_4 (1 << 12) /* 0xFFF0F000 */
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#define FMT_5 (1 << 13) /* 0xFFF0FFF0 */
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#define FMT_CR16 (FMT_1 | FMT_2 | FMT_3 | FMT_4 | FMT_5)
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/* Indicates whether this instruction can be relaxed. */
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#define RELAXABLE (1 << 14)
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/* Indicates that instruction uses user registers (and not
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general-purpose registers) as operands. */
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#define USER_REG (1 << 15)
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/* Instruction shouldn't allow 'sp' usage. */
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#define NO_SP (1 << 17)
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/* Instruction shouldn't allow to push a register which is used as a rptr. */
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#define NO_RPTR (1 << 18)
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/* Maximum operands per instruction. */
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#define MAX_OPERANDS 5
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/* Maximum register name length. */
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#define MAX_REGNAME_LEN 10
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/* Maximum instruction length. */
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#define MAX_INST_LEN 256
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/* Values defined for the flags field of a struct operand_entry. */
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/* Operand must be an unsigned number. */
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#define OP_UNSIGNED (1 << 0)
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/* Operand must be a signed number. */
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#define OP_SIGNED (1 << 1)
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/* Operand must be a negative number. */
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#define OP_NEG (1 << 2)
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/* A special load/stor 4-bit unsigned displacement operand. */
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#define OP_DEC (1 << 3)
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/* Operand must be an even number. */
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#define OP_EVEN (1 << 4)
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/* Operand is shifted right. */
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#define OP_SHIFT (1 << 5)
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/* Operand is shifted right and decremented. */
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#define OP_SHIFT_DEC (1 << 6)
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/* Operand has reserved escape sequences. */
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#define OP_ESC (1 << 7)
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/* Operand must be a ABS20 number. */
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#define OP_ABS20 (1 << 8)
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/* Operand must be a ABS24 number. */
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#define OP_ABS24 (1 << 9)
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/* Operand has reserved escape sequences type 1. */
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#define OP_ESC1 (1 << 10)
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/* Single operand description. */
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typedef struct
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{
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/* Operand type. */
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operand_type op_type;
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/* Operand location within the opcode. */
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unsigned int shift;
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}
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operand_desc;
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/* Instruction data structure used in instruction table. */
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typedef struct
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{
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/* Name. */
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const char *mnemonic;
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/* Size (in words). */
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unsigned int size;
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/* Constant prefix (matched by the disassembler). */
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unsigned long match; /* ie opcode */
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/* Match size (in bits). */
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/* MASK: if( (i & match_bits) == match ) then match */
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int match_bits;
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/* Attributes. */
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unsigned int flags;
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/* Operands (always last, so unreferenced operands are initialized). */
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operand_desc operands[MAX_OPERANDS];
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}
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inst;
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/* Data structure for a single instruction's arguments (Operands). */
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typedef struct
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{
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/* Register or base register. */
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reg r;
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/* Register pair register. */
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reg rp;
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/* Index register. */
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reg i_r;
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/* Processor register. */
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preg pr;
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/* Processor register. 32 bit */
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preg prp;
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/* Constant/immediate/absolute value. */
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long constant;
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/* CC code. */
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unsigned int cc;
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/* Scaled index mode. */
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unsigned int scale;
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/* Argument type. */
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argtype type;
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/* Size of the argument (in bits) required to represent. */
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int size;
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/* The type of the expression. */
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unsigned char X_op;
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}
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argument;
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/* Internal structure to hold the various entities
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corresponding to the current assembling instruction. */
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typedef struct
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{
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/* Number of arguments. */
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int nargs;
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/* The argument data structure for storing args (operands). */
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argument arg[MAX_OPERANDS];
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/* The following fields are required only by CR16-assembler. */
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#ifdef TC_CR16
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/* Expression used for setting the fixups (if any). */
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expressionS exp;
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bfd_reloc_code_real_type rtype;
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#endif /* TC_CR16 */
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/* Instruction size (in bytes). */
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int size;
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}
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ins;
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/* Structure to hold information about predefined operands. */
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typedef struct
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{
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/* Size (in bits). */
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unsigned int bit_size;
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/* Argument type. */
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argtype arg_type;
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/* One bit syntax flags. */
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int flags;
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}
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operand_entry;
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/* Structure to hold trap handler information. */
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typedef struct
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{
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/* Trap name. */
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char *name;
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/* Index in dispatch table. */
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unsigned int entry;
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}
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trap_entry;
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/* Structure to hold information about predefined registers. */
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typedef struct
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{
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/* Name (string representation). */
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char *name;
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/* Value (enum representation). */
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union
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{
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/* Register. */
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reg reg_val;
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/* processor register. */
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preg preg_val;
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} value;
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/* Register image. */
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int image;
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/* Register type. */
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reg_type type;
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}
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reg_entry;
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/* CR16 opcode table. */
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extern const inst cr16_instruction[];
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extern const unsigned int cr16_num_opcodes;
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#define NUMOPCODES cr16_num_opcodes
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/* CR16 operands table. */
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extern const operand_entry cr16_optab[];
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extern const unsigned int cr16_num_optab;
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/* CR16 registers table. */
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extern const reg_entry cr16_regtab[];
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extern const unsigned int cr16_num_regs;
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#define NUMREGS cr16_num_regs
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/* CR16 register pair table. */
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extern const reg_entry cr16_regptab[];
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extern const unsigned int cr16_num_regps;
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#define NUMREGPS cr16_num_regps
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/* CR16 processor registers table. */
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extern const reg_entry cr16_pregtab[];
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extern const unsigned int cr16_num_pregs;
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#define NUMPREGS cr16_num_pregs
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/* CR16 processor registers - 32 bit table. */
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extern const reg_entry cr16_pregptab[];
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extern const unsigned int cr16_num_pregps;
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#define NUMPREGPS cr16_num_pregps
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/* CR16 trap/interrupt table. */
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extern const trap_entry cr16_traps[];
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extern const unsigned int cr16_num_traps;
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#define NUMTRAPS cr16_num_traps
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/* CR16 CC - codes bit table. */
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extern const char * cr16_b_cond_tab[];
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extern const unsigned int cr16_num_cc;
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#define NUMCC cr16_num_cc;
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/* Table of instructions with no operands. */
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extern const char * cr16_no_op_insn[];
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/* Current instruction we're assembling. */
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extern const inst *instruction;
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/* A macro for representing the instruction "constant" opcode, that is,
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the FIXED part of the instruction. The "constant" opcode is represented
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as a 32-bit unsigned long, where OPC is expanded (by a left SHIFT)
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over that range. */
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#define BIN(OPC,SHIFT) (OPC << SHIFT)
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/* Is the current instruction type is TYPE ? */
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#define IS_INSN_TYPE(TYPE) \
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(CR16_INS_TYPE (instruction->flags) == TYPE)
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/* Is the current instruction mnemonic is MNEMONIC ? */
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#define IS_INSN_MNEMONIC(MNEMONIC) \
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(strcmp (instruction->mnemonic, MNEMONIC) == 0)
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/* Does the current instruction has register list ? */
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#define INST_HAS_REG_LIST \
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(instruction->flags & REG_LIST)
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/* Utility macros for string comparison. */
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#define streq(a, b) (strcmp (a, b) == 0)
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#define strneq(a, b, c) (strncmp (a, b, c) == 0)
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/* Long long type handling. */
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/* Replace all appearances of 'long long int' with LONGLONG. */
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typedef long long int LONGLONG;
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typedef unsigned long long ULONGLONG;
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/* Data types for opcode handling. */
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typedef unsigned long dwordU;
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typedef unsigned short wordU;
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/* Globals to store opcode data and build the instruction. */
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extern wordU cr16_words[3];
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extern ULONGLONG cr16_allWords;
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extern ins cr16_currInsn;
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/* Prototypes for function in cr16-dis.c. */
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extern void cr16_make_instruction (void);
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extern int cr16_match_opcode (void);
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#endif /* _CR16_H_ */
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