880 lines
19 KiB
NASM
880 lines
19 KiB
NASM
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;OS_BASE equ 0x80000000
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;new_app_base equ 0x60400000
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;PROC_BASE equ OS_BASE+0x0080000
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struc IOCTL
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{ .handle dd ?
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.io_code dd ?
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.input dd ?
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.inp_size dd ?
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.output dd ?
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.out_size dd ?
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}
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;public START
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;public service_proc
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;public version
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DEBUG equ 1
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DRV_ENTRY equ 1
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DRV_EXIT equ -1
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THR_REG equ 0; x3f8 ;transtitter/reciever
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IER_REG equ 1; x3f9 ;interrupt enable
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IIR_REG equ 2; x3fA ;interrupt info
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LCR_REG equ 3; x3FB ;line control
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MCR_REG equ 4; x3FC ;modem control
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LSR_REG equ 5; x3FD ;line status
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MSR_REG equ 6; x3FE ;modem status
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LCR_5BIT equ 0x00
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LCR_6BIT equ 0x01
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LCR_7BIT equ 0x02
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LCR_8BIT equ 0x03
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LCR_STOP_1 equ 0x00
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LCR_STOP_2 equ 0x04
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LCR_PARITY equ 0x08
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LCR_EVEN equ 0x10
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LCR_STICK equ 0x20
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LCR_BREAK equ 0x40
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LCR_DLAB equ 0x80
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LSR_DR equ 0x01 ;data ready
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LSR_OE equ 0x02 ;overrun error
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LSR_PE equ 0x04 ;parity error
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LSR_FE equ 0x08 ;framing error
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LSR_BI equ 0x10 ;break interrupt
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LSR_THRE equ 0x20 ;transmitter holding empty
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LSR_TEMT equ 0x40 ;transmitter empty
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LSR_FER equ 0x80 ;FIFO error
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FCR_EFIFO equ 0x01 ;enable FIFO
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FCR_CRB equ 0x02 ;clear reciever FIFO
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FCR_CXMIT equ 0x04 ;clear transmitter FIFO
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FCR_RDY equ 0x08 ;set RXRDY and TXRDY pins
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FCR_FIFO_1 equ 0x00 ;1 byte trigger
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FCR_FIFO_4 equ 0x40 ;4 bytes trigger
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FCR_FIFO_8 equ 0x80 ;8 bytes trigger
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FCR_FIFO_14 equ 0xC0 ;14 bytes trigger
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IIR_INTR equ 0x01 ;1= no interrupts
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IER_RDAI equ 0x01 ;reciever data interrupt
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IER_THRI equ 0x02 ;transmitter empty interrupt
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IER_LSI equ 0x04 ;line status interrupt
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IER_MSI equ 0x08 ;modem status interrupt
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MCR_DTR equ 0x01 ;0-> DTR=1, 1-> DTR=0
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MCR_RTS equ 0x02 ;0-> RTS=1, 1-> RTS=0
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MCR_OUT_1 equ 0x04 ;0-> OUT1=1, 1-> OUT1=0
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MCR_OUT_2 equ 0x08 ;0-> OUT2=1, 1-> OUT2=0; enable intr
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MCR_LOOP equ 0x10 ;lopback mode
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MSR_DCTS equ 0x01 ;delta clear to send
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MSR_DDSR equ 0x02 ;delta data set redy
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MSR_TERI equ 0x04 ;trailinh edge of ring
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MSR_DDCD equ 0x08 ;delta carrier detect
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RATE_50 equ 0
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RATE_75 equ 1
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RATE_110 equ 2
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RATE_134 equ 3
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RATE_150 equ 4
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RATE_300 equ 5
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RATE_600 equ 6
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RATE_1200 equ 7
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RATE_1800 equ 8
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RATE_2000 equ 9
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RATE_2400 equ 10
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RATE_3600 equ 11
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RATE_4800 equ 12
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RATE_7200 equ 13
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RATE_9600 equ 14
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RATE_19200 equ 15
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RATE_38400 equ 16
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RATE_57600 equ 17
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RATE_115200 equ 18
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COM_1 equ 1
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COM_2 equ 2
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COM_3 equ 3
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COM_4 equ 4
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COM_MAX equ 2 ;only two port supported
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COM_1_BASE equ 0x3F8
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COM_2_BASE equ 0x2F8
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COM_1_IRQ equ 4
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COM_2_IRQ equ 3
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UART_CLOSED equ 0
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UART_TRANSMIT equ 1
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UART_STOP equ 2
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struc UART
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{
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.lock dd ?
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.base dd ?
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.lcr_reg dd ?
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.mcr_reg dd ?
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.rate dd ?
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.mode dd ?
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.state dd ?
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.rcvr_rp dd ?
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.rcvr_wp dd ?
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.rcvr_cnt dd ?
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.xmit_buff dd ?
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.xmit_rp dd ?
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.xmit_wp dd ?
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.xmit_count dd ?
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.xmit_free dd ?
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.xmit_top dd ?
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}
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virtual at 0
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UART UART
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end virtual
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UART_SIZE equ 16*4
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struc CONNECTION
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{
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.magic dd ? ;'CNCT'
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.destroy dd ? ;internal destructor
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.fd dd ? ;next object in list
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.bk dd ? ;prev object in list
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.pid dd ? ;owner id
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.id dd ? ;reserved
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.uart dd ? ;uart pointer
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}
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virtual at 0
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CONNECTION CONNECTION
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end virtual
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CONNECTION_SIZE equ 7*4
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UART_VERSION equ 0x12345678 ;debug
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init_uart_service:
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mov eax, UART_SIZE
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call malloc
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test eax, eax
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jz .fail
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mov [com1], eax
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mov edi, eax
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mov ecx, UART_SIZE/4
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xor eax, eax
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cld
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rep stosd
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mov eax, [com1]
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mov [eax+UART.base], COM_1_BASE
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stdcall alloc_kernel_space, 16384
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mov edi, [com1]
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mov edx, eax
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mov [edi+UART.xmit_buff], eax
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add eax, 8192
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mov [edi+UART.xmit_top], eax
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call alloc_page
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test eax, eax
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jz .fail
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shr edx, 12
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or eax, PG_SW
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mov [page_tabs+edx*4], eax
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mov [page_tabs+edx*4+8], eax
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call alloc_page
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test eax, eax
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jz .fail
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or eax, PG_SW
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mov [page_tabs+edx*4+4], eax
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mov [page_tabs+edx*4+12], eax
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mov eax, [edi+UART.xmit_buff]
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invlpg [eax]
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invlpg [eax+0x1000]
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invlpg [eax+0x2000]
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invlpg [eax+0x3000]
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mov eax, edi
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call uart_reset.internal ;eax= uart
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stdcall attach_int_handler, COM_1_IRQ, com_1_isr
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stdcall reg_service, sz_uart_srv, uart_proc
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ret
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.fail:
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xor eax, eax
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ret
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handle equ IOCTL.handle
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io_code equ IOCTL.io_code
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input equ IOCTL.input
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inp_size equ IOCTL.inp_size
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output equ IOCTL.output
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out_size equ IOCTL.out_size
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SRV_GETVERSION equ 0
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PORT_OPEN equ 1
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PORT_CLOSE equ 2
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PORT_RESET equ 3
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PORT_SETMODE equ 4
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PORT_GETMODE equ 5
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PORT_SETMCR equ 6
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PORT_GETMCR equ 7
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PORT_READ equ 8
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PORT_WRITE equ 9
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align 4
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proc uart_proc stdcall, ioctl:dword
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mov ebx, [ioctl]
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mov eax, [ebx+io_code]
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cmp eax, PORT_WRITE
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ja .fail
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cmp eax, SRV_GETVERSION
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jne @F
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mov eax, [ebx+output]
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mov [eax], dword UART_VERSION
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xor eax, eax
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ret
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@@:
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cmp eax, PORT_OPEN
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jne @F
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mov ebx, [ebx+input]
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mov eax, [ebx]
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call uart_open
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mov ebx, [ioctl]
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mov ebx, [ebx+output]
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mov [ebx], ecx
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ret
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@@:
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mov esi, [ebx+input] ;input buffer
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mov edi, [ebx+output]
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call [uart_func+eax*4]
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ret
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.fail:
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or eax, -1
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ret
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endp
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|
|
restore handle
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restore io_code
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restore input
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restore inp_size
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restore output
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|
restore out_size
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|
; param
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; esi= input buffer
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; +0 connection
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;
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; retval
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; eax= error code
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|
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align 4
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uart_reset:
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|
mov eax, [esi]
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cmp [eax+APPOBJ.magic], 'CNCT'
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jne .fail
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cmp [eax+APPOBJ.destroy], uart_close.destroy
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jne .fail
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mov eax, [eax+CONNECTION.uart]
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test eax, eax
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jz .fail
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|
|
|
; set mode 2400 bod 8-bit
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|
; disable DTR & RTS
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|
; clear FIFO
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|
; clear pending interrupts
|
|
;
|
|
; param
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|
; eax= uart
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|
|
|
align 4
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.internal:
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|
mov esi, eax
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|
mov [eax+UART.state], UART_CLOSED
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|
mov edx, [eax+UART.base]
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add edx, MCR_REG
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|
xor eax, eax
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|
out dx, al ;clear DTR & RTS
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|
|
mov eax, esi
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|
mov ebx, RATE_2400
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mov ecx, LCR_8BIT+LCR_STOP_1
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|
call uart_set_mode.internal
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|
|
|
mov edx, [esi+UART.base]
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|
add edx, IIR_REG
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|
mov eax,FCR_EFIFO+FCR_CRB+FCR_CXMIT+FCR_FIFO_14
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out dx, al
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|
.clear_RB:
|
|
mov edx, [esi+UART.base]
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|
add edx, LSR_REG
|
|
in al, dx
|
|
test eax, LSR_DR
|
|
jz @F
|
|
|
|
mov edx, [esi+UART.base]
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|
in al, dx
|
|
jmp .clear_RB
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@@:
|
|
mov edx, [esi+UART.base]
|
|
add edx, IER_REG
|
|
mov eax,IER_RDAI+IER_THRI+IER_LSI
|
|
out dx, al
|
|
.clear_IIR:
|
|
mov edx, [esi+UART.base]
|
|
add edx, IIR_REG
|
|
in al, dx
|
|
test al, IIR_INTR
|
|
jnz .done
|
|
|
|
shr eax, 1
|
|
and eax, 3
|
|
jnz @F
|
|
|
|
mov edx, [esi+UART.base]
|
|
add edx, MSR_REG
|
|
in al, dx
|
|
jmp .clear_IIR
|
|
@@:
|
|
cmp eax, 1
|
|
je .clear_IIR
|
|
|
|
cmp eax, 2
|
|
jne @F
|
|
|
|
mov edx, [esi+UART.base]
|
|
in al, dx
|
|
jmp .clear_IIR
|
|
@@:
|
|
mov edx, [esi+UART.base]
|
|
add edx, LSR_REG
|
|
in al, dx
|
|
jmp .clear_IIR
|
|
.done:
|
|
mov edi, [esi+UART.xmit_buff]
|
|
mov ecx, 8192/4
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|
xor eax, eax
|
|
|
|
mov [esi+UART.xmit_rp], edi
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|
mov [esi+UART.xmit_wp], edi
|
|
mov [esi+UART.xmit_count], eax
|
|
mov [esi+UART.xmit_free], 8192
|
|
|
|
cld
|
|
rep stosd
|
|
|
|
|
|
; mov [esi+UART.rcvr_rp], eax
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|
; mov [esi+UART.rcvr_wp], eax
|
|
; mov [esi+UART.rcvr_cnt], eax
|
|
|
|
ret
|
|
.fail:
|
|
or eax, -1
|
|
ret
|
|
|
|
; param
|
|
; esi= input buffer
|
|
; +0 connection
|
|
; +4 rate
|
|
; +8 mode
|
|
;
|
|
; retval
|
|
; eax= error code
|
|
|
|
align 4
|
|
uart_set_mode:
|
|
mov eax, [esi]
|
|
cmp [eax+APPOBJ.magic], 'CNCT'
|
|
jne .fail
|
|
|
|
cmp [eax+APPOBJ.destroy], uart_close.destroy
|
|
jne .fail
|
|
|
|
mov eax, [eax+CONNECTION.uart]
|
|
test eax, eax
|
|
jz .fail
|
|
|
|
mov ebx, [esi+4]
|
|
mov ecx, [esi+8]
|
|
|
|
; param
|
|
; eax= uart
|
|
; ebx= baud rate
|
|
; ecx= mode
|
|
|
|
align 4
|
|
.internal:
|
|
cmp ebx, RATE_115200
|
|
ja .fail
|
|
|
|
cmp ecx, LCR_BREAK
|
|
jae .fail
|
|
|
|
mov [eax+UART.rate], ebx
|
|
mov [eax+UART.mode], ecx
|
|
|
|
mov esi, eax
|
|
mov bx, [divisor+ebx*2]
|
|
|
|
mov edx, [esi+UART.base]
|
|
push edx
|
|
add edx, LCR_REG
|
|
in al, dx
|
|
or al, 0x80
|
|
out dx, al
|
|
|
|
pop edx
|
|
mov al, bl
|
|
out dx, al
|
|
|
|
inc dx
|
|
mov al, bh
|
|
out dx, al
|
|
|
|
add edx, LCR_REG-1
|
|
mov eax, ecx
|
|
out dx, al
|
|
xor eax, eax
|
|
ret
|
|
.fail:
|
|
or eax, -1
|
|
ret
|
|
|
|
; param
|
|
; esi= input buffer
|
|
; +0 connection
|
|
; +4 modem control reg valie
|
|
;
|
|
; retval
|
|
; eax= error code
|
|
|
|
align 4
|
|
uart_set_mcr:
|
|
|
|
mov eax, [esi]
|
|
cmp [eax+APPOBJ.magic], 'CNCT'
|
|
jne .fail
|
|
|
|
cmp [eax+APPOBJ.destroy], uart_close.destroy
|
|
jne .fail
|
|
|
|
mov eax, [eax+CONNECTION.uart]
|
|
test eax, eax
|
|
jz .fail
|
|
|
|
mov ebx, [esi+4]
|
|
|
|
mov [eax+UART.mcr_reg], ebx
|
|
mov edx, [eax+UART.base]
|
|
add edx, MCR_REG
|
|
mov al, bl
|
|
out dx, al
|
|
xor eax, eax
|
|
ret
|
|
.fail:
|
|
or eax, -1
|
|
ret
|
|
|
|
; param
|
|
; eax= port
|
|
;
|
|
; retval
|
|
; ecx= connection
|
|
; eax= error code
|
|
|
|
align 4
|
|
uart_open:
|
|
dec eax
|
|
cmp eax, COM_MAX
|
|
jae .fail
|
|
|
|
mov esi, [com1+eax*4] ;uart
|
|
push esi
|
|
.do_wait:
|
|
cmp dword [esi+UART.lock],0
|
|
je .get_lock
|
|
call change_task
|
|
jmp .do_wait
|
|
.get_lock:
|
|
mov eax, 1
|
|
xchg eax, [esi+UART.lock]
|
|
test eax, eax
|
|
jnz .do_wait
|
|
|
|
mov eax, esi ;uart
|
|
call uart_reset.internal
|
|
|
|
mov ebx, [CURRENT_TASK]
|
|
shl ebx, 5
|
|
mov ebx, [CURRENT_TASK+ebx+4]
|
|
mov eax, CONNECTION_SIZE
|
|
call create_kernel_object
|
|
pop esi ;uart
|
|
test eax, eax
|
|
jz .fail
|
|
|
|
mov [eax+APPOBJ.magic], 'CNCT'
|
|
mov [eax+APPOBJ.destroy], uart_close.destroy
|
|
mov [eax+CONNECTION.uart], esi
|
|
mov ecx, eax
|
|
xor eax, eax
|
|
ret
|
|
.fail:
|
|
or eax, -1
|
|
ret
|
|
restore .uart
|
|
|
|
; param
|
|
; esi= input buffer
|
|
|
|
align 4
|
|
uart_close:
|
|
mov eax, [esi]
|
|
cmp [eax+APPOBJ.magic], 'CNCT'
|
|
jne .fail
|
|
|
|
cmp [eax+APPOBJ.destroy], uart_close.destroy
|
|
jne .fail
|
|
.destroy:
|
|
push [eax+CONNECTION.uart]
|
|
call destroy_kernel_object ;eax= object
|
|
pop eax ;eax= uart
|
|
test eax, eax
|
|
jz .fail
|
|
|
|
mov [eax+UART.state], UART_CLOSED
|
|
mov [eax+UART.lock], 0 ;release port
|
|
xor eax, eax
|
|
ret
|
|
.fail:
|
|
or eax, -1
|
|
ret
|
|
|
|
|
|
; param
|
|
; eax= uart
|
|
; ebx= baud rate
|
|
|
|
align 4
|
|
set_rate:
|
|
cmp ebx, RATE_115200
|
|
ja .fail
|
|
|
|
mov [eax+UART.rate], ebx
|
|
mov bx, [divisor+ebx*2]
|
|
|
|
mov edx, [eax+UART.base]
|
|
add edx, LCR_REG
|
|
in al, dx
|
|
push eax
|
|
or al, 0x80
|
|
out dx, al
|
|
|
|
sub edx, LCR_REG
|
|
mov al, bl
|
|
out dx, al
|
|
|
|
inc edx
|
|
mov al, bh
|
|
out dx, al
|
|
|
|
pop eax
|
|
add edx, LCR_REG-1
|
|
out dx, al
|
|
.fail:
|
|
ret
|
|
|
|
|
|
; param
|
|
; ebx= uart
|
|
|
|
align 4
|
|
transmit:
|
|
push esi
|
|
push edi
|
|
|
|
mov edx, [ebx+UART.base]
|
|
|
|
pushfd
|
|
cli
|
|
|
|
mov esi, [ebx+UART.xmit_rp]
|
|
mov ecx, [ebx+UART.xmit_count]
|
|
test ecx, ecx
|
|
je .stop
|
|
|
|
cmp ecx, 16
|
|
jbe @F
|
|
mov ecx, 16
|
|
@@:
|
|
sub [ebx+UART.xmit_count], ecx
|
|
add [ebx+UART.xmit_free], ecx
|
|
cld
|
|
@@:
|
|
lodsb
|
|
out dx, al
|
|
dec ecx
|
|
jnz @B
|
|
|
|
cmp esi,[ebx+UART.xmit_top]
|
|
jb @F
|
|
sub esi, 8192
|
|
@@:
|
|
mov [ebx+UART.xmit_rp], esi
|
|
|
|
cmp [ebx+UART.xmit_count], 0
|
|
je .stop
|
|
|
|
mov [ebx+UART.state], UART_TRANSMIT
|
|
jmp @F
|
|
.stop:
|
|
mov [ebx+UART.state], UART_STOP
|
|
@@:
|
|
popfd
|
|
pop edi
|
|
pop esi
|
|
ret
|
|
|
|
|
|
; param
|
|
; esi= input buffer
|
|
; +0 connection
|
|
; +4 dst buffer
|
|
; +8 dst size
|
|
; edi= output buffer
|
|
; +0 bytes read
|
|
|
|
; retval
|
|
; eax= error code
|
|
|
|
align 4
|
|
uart_read:
|
|
mov eax, [esi]
|
|
cmp [eax+APPOBJ.magic], 'CNCT'
|
|
jne .fail
|
|
|
|
cmp [eax+APPOBJ.destroy], uart_close.destroy
|
|
jne .fail
|
|
|
|
mov eax, [eax+CONNECTION.uart]
|
|
test eax, eax
|
|
jz .fail
|
|
|
|
mov ebx, [esi+8] ;dst size
|
|
mov ecx, [eax+UART.rcvr_cnt]
|
|
cmp ecx, ebx
|
|
jbe @F
|
|
mov ecx, ebx
|
|
@@:
|
|
mov [edi], ecx ;bytes read
|
|
test ecx, ecx
|
|
jz .done
|
|
|
|
sub [eax+UART.rcvr_cnt], ecx
|
|
|
|
push eax
|
|
mov edi, [esi+4] ;dst
|
|
; lea esi, [eax+RCVR_OFFSET]
|
|
mov ebx, [eax+UART.rcvr_rp]
|
|
cld
|
|
@@:
|
|
and ebx, 127
|
|
mov al, [esi+ebx]
|
|
stosb
|
|
inc ebx
|
|
dec ecx
|
|
jnz @B
|
|
|
|
pop eax
|
|
mov [eax+UART.rcvr_rp], ebx
|
|
.done:
|
|
xor eax, eax
|
|
rep
|
|
.fail:
|
|
or eax, -1
|
|
ret
|
|
|
|
; param
|
|
; esi= input buffer
|
|
; +0 connection
|
|
; +4 src buffer
|
|
; +8 src size
|
|
;
|
|
; retval
|
|
; eax= error code
|
|
|
|
align 4
|
|
uart_write:
|
|
mov eax, [esi]
|
|
cmp [eax+APPOBJ.magic], 'CNCT'
|
|
jne .fail
|
|
|
|
cmp [eax+APPOBJ.destroy], uart_close.destroy
|
|
jne .fail
|
|
|
|
mov eax, [eax+CONNECTION.uart]
|
|
test eax, eax
|
|
jz .fail
|
|
|
|
mov ebx, [esi+4]
|
|
mov edx, [esi+8]
|
|
|
|
; param
|
|
; eax= uart
|
|
; ebx= src
|
|
; edx= count
|
|
|
|
align 4
|
|
.internal:
|
|
mov esi, ebx
|
|
mov edi, [eax+UART.xmit_wp]
|
|
.write:
|
|
test edx, edx
|
|
jz .fail
|
|
.wait:
|
|
cmp [eax+UART.xmit_free], 0
|
|
jne .fill
|
|
|
|
cmp [eax+UART.state], UART_TRANSMIT
|
|
je .wait
|
|
|
|
mov ebx, eax
|
|
push edx
|
|
call transmit
|
|
pop edx
|
|
mov eax, ebx
|
|
jmp .write
|
|
.fill:
|
|
mov ecx, [eax+UART.xmit_free]
|
|
cmp ecx, edx
|
|
jbe @F
|
|
mov ecx, edx
|
|
@@:
|
|
push ecx
|
|
cld
|
|
rep movsb
|
|
pop ecx
|
|
sub [eax+UART.xmit_free], ecx
|
|
add [eax+UART.xmit_count], ecx
|
|
sub edx, ecx
|
|
jnz .wait
|
|
.done:
|
|
cmp edi, [eax+UART.xmit_top]
|
|
jb @F
|
|
sub edi, 8192
|
|
@@:
|
|
mov [eax+UART.xmit_wp], edi
|
|
cmp [eax+UART.state], UART_TRANSMIT
|
|
je @F
|
|
mov ebx, eax
|
|
call transmit
|
|
@@:
|
|
xor eax, eax
|
|
ret
|
|
.fail:
|
|
or eax, -1
|
|
ret
|
|
|
|
|
|
align 4
|
|
com_2_isr:
|
|
mov ebx, [com2]
|
|
jmp com_1_isr.get_info
|
|
align 4
|
|
com_1_isr:
|
|
mov ebx, [com1]
|
|
.get_info:
|
|
mov edx, [ebx+UART.base]
|
|
add edx, IIR_REG
|
|
in al, dx
|
|
|
|
test al, IIR_INTR
|
|
jnz .done
|
|
|
|
shr eax, 1
|
|
and eax, 3
|
|
|
|
call [isr_action+eax*4]
|
|
jmp .get_info
|
|
.done:
|
|
ret
|
|
|
|
align 4
|
|
isr_line:
|
|
mov edx, [ebx+UART.base]
|
|
add edx, LSR_REG
|
|
in al, dx
|
|
ret
|
|
|
|
align 4
|
|
isr_recieve:
|
|
mov edx, [ebx+UART.base]
|
|
in al, dx
|
|
ret
|
|
|
|
align 4
|
|
isr_modem:
|
|
mov edx, [ebx+UART.base]
|
|
add edx, MSR_REG
|
|
in al, dx
|
|
ret
|
|
|
|
|
|
align 4
|
|
com1 dd 0
|
|
com2 dd 0
|
|
|
|
align 4
|
|
uart_func dd 0 ;SRV_GETVERSION
|
|
dd 0 ;PORT_OPEN
|
|
dd uart_close ;PORT_CLOSE
|
|
dd uart_reset ;PORT_RESET
|
|
dd uart_set_mode ;PORT_SETMODE
|
|
dd 0 ;PORT_GETMODE
|
|
dd uart_set_mcr ;PORT_SETMODEM
|
|
dd 0 ;PORT_GETMODEM
|
|
dd uart_read ;PORT_READ
|
|
dd uart_write ;PORT_WRITE
|
|
|
|
isr_action dd isr_modem
|
|
dd transmit
|
|
dd isr_recieve
|
|
dd isr_line
|
|
|
|
;version dd 0x00040000
|
|
|
|
divisor dw 2304, 1536, 1047, 857, 768, 384
|
|
dw 192, 96, 64, 58, 48, 32
|
|
dw 24, 16, 12, 6, 3, 2, 1
|
|
|
|
|
|
|
|
sz_uart_srv db 'UART',0
|
|
|
|
|
|
|