289 lines
8.4 KiB
C
289 lines
8.4 KiB
C
#ifndef INTEL_DRIVER_H
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#define INTEL_DRIVER_H
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#define INTEL_VERSION 4000
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#define INTEL_NAME "intel"
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#define INTEL_DRIVER_NAME "intel"
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#define INTEL_VERSION_MAJOR PACKAGE_VERSION_MAJOR
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#define INTEL_VERSION_MINOR PACKAGE_VERSION_MINOR
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#define INTEL_VERSION_PATCH PACKAGE_VERSION_PATCHLEVEL
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#ifndef PCI_CHIP_I810
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#define PCI_CHIP_I810 0x7121
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#define PCI_CHIP_I810_DC100 0x7123
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#define PCI_CHIP_I810_E 0x7125
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#define PCI_CHIP_I815 0x1132
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#define PCI_CHIP_I810_BRIDGE 0x7120
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#define PCI_CHIP_I810_DC100_BRIDGE 0x7122
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#define PCI_CHIP_I810_E_BRIDGE 0x7124
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#define PCI_CHIP_I815_BRIDGE 0x1130
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#endif
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#ifndef PCI_CHIP_I830_M
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#define PCI_CHIP_I830_M 0x3577
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#define PCI_CHIP_I830_M_BRIDGE 0x3575
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#endif
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#ifndef PCI_CHIP_845_G
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#define PCI_CHIP_845_G 0x2562
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#define PCI_CHIP_845_G_BRIDGE 0x2560
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#endif
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#ifndef PCI_CHIP_I854
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#define PCI_CHIP_I854 0x358E
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#define PCI_CHIP_I854_BRIDGE 0x358C
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#endif
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#ifndef PCI_CHIP_I855_GM
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#define PCI_CHIP_I855_GM 0x3582
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#define PCI_CHIP_I855_GM_BRIDGE 0x3580
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#endif
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#ifndef PCI_CHIP_I865_G
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#define PCI_CHIP_I865_G 0x2572
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#define PCI_CHIP_I865_G_BRIDGE 0x2570
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#endif
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#ifndef PCI_CHIP_I915_G
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#define PCI_CHIP_I915_G 0x2582
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#define PCI_CHIP_I915_G_BRIDGE 0x2580
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#endif
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#ifndef PCI_CHIP_I915_GM
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#define PCI_CHIP_I915_GM 0x2592
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#define PCI_CHIP_I915_GM_BRIDGE 0x2590
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#endif
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#ifndef PCI_CHIP_E7221_G
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#define PCI_CHIP_E7221_G 0x258A
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/* Same as I915_G_BRIDGE */
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#define PCI_CHIP_E7221_G_BRIDGE 0x2580
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#endif
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#ifndef PCI_CHIP_I945_G
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#define PCI_CHIP_I945_G 0x2772
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#define PCI_CHIP_I945_G_BRIDGE 0x2770
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#endif
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#ifndef PCI_CHIP_I945_GM
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#define PCI_CHIP_I945_GM 0x27A2
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#define PCI_CHIP_I945_GM_BRIDGE 0x27A0
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#endif
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#ifndef PCI_CHIP_I945_GME
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#define PCI_CHIP_I945_GME 0x27AE
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#define PCI_CHIP_I945_GME_BRIDGE 0x27AC
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#endif
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#ifndef PCI_CHIP_PINEVIEW_M
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#define PCI_CHIP_PINEVIEW_M 0xA011
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#define PCI_CHIP_PINEVIEW_M_BRIDGE 0xA010
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#define PCI_CHIP_PINEVIEW_G 0xA001
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#define PCI_CHIP_PINEVIEW_G_BRIDGE 0xA000
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#endif
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#ifndef PCI_CHIP_G35_G
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#define PCI_CHIP_G35_G 0x2982
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#define PCI_CHIP_G35_G_BRIDGE 0x2980
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#endif
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#ifndef PCI_CHIP_I965_Q
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#define PCI_CHIP_I965_Q 0x2992
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#define PCI_CHIP_I965_Q_BRIDGE 0x2990
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#endif
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#ifndef PCI_CHIP_I965_G
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#define PCI_CHIP_I965_G 0x29A2
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#define PCI_CHIP_I965_G_BRIDGE 0x29A0
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#endif
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#ifndef PCI_CHIP_I946_GZ
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#define PCI_CHIP_I946_GZ 0x2972
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#define PCI_CHIP_I946_GZ_BRIDGE 0x2970
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#endif
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#ifndef PCI_CHIP_I965_GM
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#define PCI_CHIP_I965_GM 0x2A02
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#define PCI_CHIP_I965_GM_BRIDGE 0x2A00
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#endif
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#ifndef PCI_CHIP_I965_GME
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#define PCI_CHIP_I965_GME 0x2A12
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#define PCI_CHIP_I965_GME_BRIDGE 0x2A10
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#endif
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#ifndef PCI_CHIP_G33_G
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#define PCI_CHIP_G33_G 0x29C2
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#define PCI_CHIP_G33_G_BRIDGE 0x29C0
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#endif
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#ifndef PCI_CHIP_Q35_G
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#define PCI_CHIP_Q35_G 0x29B2
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#define PCI_CHIP_Q35_G_BRIDGE 0x29B0
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#endif
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#ifndef PCI_CHIP_Q33_G
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#define PCI_CHIP_Q33_G 0x29D2
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#define PCI_CHIP_Q33_G_BRIDGE 0x29D0
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#endif
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#ifndef PCI_CHIP_GM45_GM
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#define PCI_CHIP_GM45_GM 0x2A42
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#define PCI_CHIP_GM45_BRIDGE 0x2A40
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#endif
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#ifndef PCI_CHIP_G45_E_G
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#define PCI_CHIP_G45_E_G 0x2E02
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#define PCI_CHIP_G45_E_G_BRIDGE 0x2E00
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#endif
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#ifndef PCI_CHIP_G45_G
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#define PCI_CHIP_G45_G 0x2E22
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#define PCI_CHIP_G45_G_BRIDGE 0x2E20
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#endif
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#ifndef PCI_CHIP_Q45_G
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#define PCI_CHIP_Q45_G 0x2E12
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#define PCI_CHIP_Q45_G_BRIDGE 0x2E10
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#endif
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#ifndef PCI_CHIP_G41_G
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#define PCI_CHIP_G41_G 0x2E32
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#define PCI_CHIP_G41_G_BRIDGE 0x2E30
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#endif
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#ifndef PCI_CHIP_B43_G
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#define PCI_CHIP_B43_G 0x2E42
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#define PCI_CHIP_B43_G_BRIDGE 0x2E40
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#endif
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#ifndef PCI_CHIP_B43_G1
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#define PCI_CHIP_B43_G1 0x2E92
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#define PCI_CHIP_B43_G1_BRIDGE 0x2E90
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#endif
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#ifndef PCI_CHIP_IRONLAKE_D_G
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#define PCI_CHIP_IRONLAKE_D_G 0x0042
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#define PCI_CHIP_IRONLAKE_D_G_BRIDGE 0x0040
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#endif
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#ifndef PCI_CHIP_IRONLAKE_M_G
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#define PCI_CHIP_IRONLAKE_M_G 0x0046
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#define PCI_CHIP_IRONLAKE_M_G_BRIDGE 0x0044
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#endif
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#ifndef PCI_CHIP_SANDYBRIDGE_BRIDGE
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#define PCI_CHIP_SANDYBRIDGE_BRIDGE 0x0100 /* Desktop */
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#define PCI_CHIP_SANDYBRIDGE_GT1 0x0102
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#define PCI_CHIP_SANDYBRIDGE_GT2 0x0112
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#define PCI_CHIP_SANDYBRIDGE_GT2_PLUS 0x0122
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#define PCI_CHIP_SANDYBRIDGE_BRIDGE_M 0x0104 /* Mobile */
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#define PCI_CHIP_SANDYBRIDGE_M_GT1 0x0106
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#define PCI_CHIP_SANDYBRIDGE_M_GT2 0x0116
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#define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS 0x0126
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#define PCI_CHIP_SANDYBRIDGE_BRIDGE_S 0x0108 /* Server */
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#define PCI_CHIP_SANDYBRIDGE_S_GT 0x010A
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#define PCI_CHIP_IVYBRIDGE_M_GT1 0x0156
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#define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166
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#define PCI_CHIP_IVYBRIDGE_D_GT1 0x0152
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#define PCI_CHIP_IVYBRIDGE_D_GT2 0x0162
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#define PCI_CHIP_IVYBRIDGE_S_GT1 0x015a
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#define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a
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#define PCI_CHIP_HASWELL_D_GT1 0x0402
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#define PCI_CHIP_HASWELL_D_GT2 0x0412
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#define PCI_CHIP_HASWELL_D_GT2_PLUS 0x0422
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#define PCI_CHIP_HASWELL_M_GT1 0x0406
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#define PCI_CHIP_HASWELL_M_GT2 0x0416
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#define PCI_CHIP_HASWELL_M_GT2_PLUS 0x0426
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#define PCI_CHIP_HASWELL_S_GT1 0x040A
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#define PCI_CHIP_HASWELL_S_GT2 0x041A
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#define PCI_CHIP_HASWELL_S_GT2_PLUS 0x042A
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#define PCI_CHIP_HASWELL_SDV_D_GT1 0x0C02
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#define PCI_CHIP_HASWELL_SDV_D_GT2 0x0C12
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#define PCI_CHIP_HASWELL_SDV_D_GT2_PLUS 0x0C22
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#define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06
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#define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16
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#define PCI_CHIP_HASWELL_SDV_M_GT2_PLUS 0x0C26
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#define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A
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#define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A
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#define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS 0x0C2A
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#define PCI_CHIP_HASWELL_ULT_D_GT1 0x0A02
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#define PCI_CHIP_HASWELL_ULT_D_GT2 0x0A12
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#define PCI_CHIP_HASWELL_ULT_D_GT2_PLUS 0x0A22
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#define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06
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#define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16
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#define PCI_CHIP_HASWELL_ULT_M_GT2_PLUS 0x0A26
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#define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A
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#define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A
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#define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A
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#define PCI_CHIP_HASWELL_CRW_D_GT1 0x0D12
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#define PCI_CHIP_HASWELL_CRW_D_GT2 0x0D22
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#define PCI_CHIP_HASWELL_CRW_D_GT2_PLUS 0x0D32
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#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D16
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#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D26
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#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D36
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#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D1A
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#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D2A
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#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D3A
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#define PCI_CHIP_VALLEYVIEW_PO 0x0f30
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#define PCI_CHIP_VALLEYVIEW_1 0x0f31
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#define PCI_CHIP_VALLEYVIEW_2 0x0f32
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#define PCI_CHIP_VALLEYVIEW_3 0x0f33
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#endif
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#define I85X_CAPID 0x44
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#define I85X_VARIANT_MASK 0x7
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#define I85X_VARIANT_SHIFT 5
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#define I855_GME 0x0
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#define I855_GM 0x4
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#define I852_GME 0x2
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#define I852_GM 0x5
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#define I810_MEMBASE(p,n) (p)->regions[(n)].base_addr
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#define VENDOR_ID(p) (p)->vendor_id
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#define DEVICE_ID(p) (p)->device_id
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#define SUBVENDOR_ID(p) (p)->subvendor_id
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#define SUBSYS_ID(p) (p)->subdevice_id
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#define CHIP_REVISION(p) (p)->revision
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#define INTEL_INFO(intel) ((intel)->info)
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#define IS_GENx(intel, X) (INTEL_INFO(intel)->gen >= 8*(X) && INTEL_INFO(intel)->gen < 8*((X)+1))
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#define IS_GEN1(intel) IS_GENx(intel, 1)
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#define IS_GEN2(intel) IS_GENx(intel, 2)
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#define IS_GEN3(intel) IS_GENx(intel, 3)
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#define IS_GEN4(intel) IS_GENx(intel, 4)
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#define IS_GEN5(intel) IS_GENx(intel, 5)
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#define IS_GEN6(intel) IS_GENx(intel, 6)
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#define IS_GEN7(intel) IS_GENx(intel, 7)
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#define IS_HSW(intel) (INTEL_INFO(intel)->gen == 075)
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/* Some chips have specific errata (or limits) that we need to workaround. */
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#define IS_I830(intel) (DEVICE_ID((intel)->PciInfo) == PCI_CHIP_I830_M)
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#define IS_845G(intel) (DEVICE_ID((intel)->PciInfo) == PCI_CHIP_845_G)
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#define IS_I865G(intel) (DEVICE_ID((intel)->PciInfo) == PCI_CHIP_I865_G)
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#define IS_I915G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I915_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_E7221_G)
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#define IS_I915GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I915_GM)
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#define IS_965_Q(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q)
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/* supports Y tiled surfaces (pre-965 Mesa isn't ready yet) */
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#define SUPPORTS_YTILING(pI810) (INTEL_INFO(intel)->gen >= 040)
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#define HAS_BLT(pI810) (INTEL_INFO(intel)->gen >= 060)
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struct intel_device_info {
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int gen;
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};
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//void intel_detect_chipset(ScrnInfoPtr scrn,
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// EntityInfoPtr ent,
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// struct pci_device *pci);
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#endif /* INTEL_DRIVER_H */
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