995 lines
25 KiB
C
995 lines
25 KiB
C
/*
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* Copyright © 2006 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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*
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*/
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#ifndef _INTEL_BIOS_H_
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#define _INTEL_BIOS_H_
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/**
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* struct vbt_header - VBT Header structure
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* @signature: VBT signature, always starts with "$VBT"
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* @version: Version of this structure
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* @header_size: Size of this structure
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* @vbt_size: Size of VBT (VBT Header, BDB Header and data blocks)
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* @vbt_checksum: Checksum
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* @reserved0: Reserved
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* @bdb_offset: Offset of &struct bdb_header from beginning of VBT
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* @aim_offset: Offsets of add-in data blocks from beginning of VBT
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*/
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struct vbt_header {
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u8 signature[20];
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u16 version;
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u16 header_size;
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u16 vbt_size;
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u8 vbt_checksum;
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u8 reserved0;
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u32 bdb_offset;
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u32 aim_offset[4];
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} __packed;
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/**
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* struct bdb_header - BDB Header structure
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* @signature: BDB signature "BIOS_DATA_BLOCK"
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* @version: Version of the data block definitions
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* @header_size: Size of this structure
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* @bdb_size: Size of BDB (BDB Header and data blocks)
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*/
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struct bdb_header {
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u8 signature[16];
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u16 version;
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u16 header_size;
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u16 bdb_size;
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} __packed;
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/* strictly speaking, this is a "skip" block, but it has interesting info */
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struct vbios_data {
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u8 type; /* 0 == desktop, 1 == mobile */
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u8 relstage;
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u8 chipset;
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u8 lvds_present:1;
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u8 tv_present:1;
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u8 rsvd2:6; /* finish byte */
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u8 rsvd3[4];
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u8 signon[155];
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u8 copyright[61];
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u16 code_segment;
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u8 dos_boot_mode;
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u8 bandwidth_percent;
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u8 rsvd4; /* popup memory size */
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u8 resize_pci_bios;
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u8 rsvd5; /* is crt already on ddc2 */
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} __packed;
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/*
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* There are several types of BIOS data blocks (BDBs), each block has
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* an ID and size in the first 3 bytes (ID in first, size in next 2).
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* Known types are listed below.
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*/
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#define BDB_GENERAL_FEATURES 1
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#define BDB_GENERAL_DEFINITIONS 2
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#define BDB_OLD_TOGGLE_LIST 3
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#define BDB_MODE_SUPPORT_LIST 4
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#define BDB_GENERIC_MODE_TABLE 5
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#define BDB_EXT_MMIO_REGS 6
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#define BDB_SWF_IO 7
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#define BDB_SWF_MMIO 8
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#define BDB_PSR 9
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#define BDB_MODE_REMOVAL_TABLE 10
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#define BDB_CHILD_DEVICE_TABLE 11
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#define BDB_DRIVER_FEATURES 12
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#define BDB_DRIVER_PERSISTENCE 13
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#define BDB_EXT_TABLE_PTRS 14
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#define BDB_DOT_CLOCK_OVERRIDE 15
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#define BDB_DISPLAY_SELECT 16
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/* 17 rsvd */
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#define BDB_DRIVER_ROTATION 18
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#define BDB_DISPLAY_REMOVE 19
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#define BDB_OEM_CUSTOM 20
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#define BDB_EFP_LIST 21 /* workarounds for VGA hsync/vsync */
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#define BDB_SDVO_LVDS_OPTIONS 22
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#define BDB_SDVO_PANEL_DTDS 23
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#define BDB_SDVO_LVDS_PNP_IDS 24
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#define BDB_SDVO_LVDS_POWER_SEQ 25
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#define BDB_TV_OPTIONS 26
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#define BDB_EDP 27
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#define BDB_LVDS_OPTIONS 40
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#define BDB_LVDS_LFP_DATA_PTRS 41
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#define BDB_LVDS_LFP_DATA 42
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#define BDB_LVDS_BACKLIGHT 43
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#define BDB_LVDS_POWER 44
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#define BDB_MIPI_CONFIG 52
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#define BDB_MIPI_SEQUENCE 53
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#define BDB_SKIP 254 /* VBIOS private block, ignore */
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struct bdb_general_features {
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/* bits 1 */
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u8 panel_fitting:2;
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u8 flexaim:1;
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u8 msg_enable:1;
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u8 clear_screen:3;
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u8 color_flip:1;
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/* bits 2 */
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u8 download_ext_vbt:1;
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u8 enable_ssc:1;
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u8 ssc_freq:1;
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u8 enable_lfp_on_override:1;
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u8 disable_ssc_ddt:1;
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u8 rsvd7:1;
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u8 display_clock_mode:1;
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u8 rsvd8:1; /* finish byte */
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/* bits 3 */
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u8 disable_smooth_vision:1;
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u8 single_dvi:1;
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u8 rsvd9:1;
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u8 fdi_rx_polarity_inverted:1;
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u8 rsvd10:4; /* finish byte */
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/* bits 4 */
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u8 legacy_monitor_detect;
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/* bits 5 */
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u8 int_crt_support:1;
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u8 int_tv_support:1;
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u8 int_efp_support:1;
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u8 dp_ssc_enb:1; /* PCH attached eDP supports SSC */
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u8 dp_ssc_freq:1; /* SSC freq for PCH attached eDP */
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u8 rsvd11:3; /* finish byte */
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} __packed;
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/* pre-915 */
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#define GPIO_PIN_DVI_LVDS 0x03 /* "DVI/LVDS DDC GPIO pins" */
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#define GPIO_PIN_ADD_I2C 0x05 /* "ADDCARD I2C GPIO pins" */
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#define GPIO_PIN_ADD_DDC 0x04 /* "ADDCARD DDC GPIO pins" */
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#define GPIO_PIN_ADD_DDC_I2C 0x06 /* "ADDCARD DDC/I2C GPIO pins" */
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/* Pre 915 */
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#define DEVICE_TYPE_NONE 0x00
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#define DEVICE_TYPE_CRT 0x01
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#define DEVICE_TYPE_TV 0x09
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#define DEVICE_TYPE_EFP 0x12
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#define DEVICE_TYPE_LFP 0x22
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/* On 915+ */
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#define DEVICE_TYPE_CRT_DPMS 0x6001
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#define DEVICE_TYPE_CRT_DPMS_HOTPLUG 0x4001
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#define DEVICE_TYPE_TV_COMPOSITE 0x0209
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#define DEVICE_TYPE_TV_MACROVISION 0x0289
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#define DEVICE_TYPE_TV_RF_COMPOSITE 0x020c
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#define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609
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#define DEVICE_TYPE_TV_SCART 0x0209
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#define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009
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#define DEVICE_TYPE_EFP_HOTPLUG_PWR 0x6012
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#define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052
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#define DEVICE_TYPE_EFP_DVI_I 0x6053
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#define DEVICE_TYPE_EFP_DVI_D_DUAL 0x6152
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#define DEVICE_TYPE_EFP_DVI_D_HDCP 0x60d2
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#define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062
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#define DEVICE_TYPE_OPENLDI_DUALPIX 0x6162
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#define DEVICE_TYPE_LFP_PANELLINK 0x5012
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#define DEVICE_TYPE_LFP_CMOS_PWR 0x5042
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#define DEVICE_TYPE_LFP_LVDS_PWR 0x5062
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#define DEVICE_TYPE_LFP_LVDS_DUAL 0x5162
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#define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP 0x51e2
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#define DEVICE_CFG_NONE 0x00
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#define DEVICE_CFG_12BIT_DVOB 0x01
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#define DEVICE_CFG_12BIT_DVOC 0x02
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#define DEVICE_CFG_24BIT_DVOBC 0x09
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#define DEVICE_CFG_24BIT_DVOCB 0x0a
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#define DEVICE_CFG_DUAL_DVOB 0x11
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#define DEVICE_CFG_DUAL_DVOC 0x12
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#define DEVICE_CFG_DUAL_DVOBC 0x13
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#define DEVICE_CFG_DUAL_LINK_DVOBC 0x19
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#define DEVICE_CFG_DUAL_LINK_DVOCB 0x1a
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#define DEVICE_WIRE_NONE 0x00
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#define DEVICE_WIRE_DVOB 0x01
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#define DEVICE_WIRE_DVOC 0x02
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#define DEVICE_WIRE_DVOBC 0x03
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#define DEVICE_WIRE_DVOBB 0x05
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#define DEVICE_WIRE_DVOCC 0x06
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#define DEVICE_WIRE_DVOB_MASTER 0x0d
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#define DEVICE_WIRE_DVOC_MASTER 0x0e
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#define DEVICE_PORT_DVOA 0x00 /* none on 845+ */
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#define DEVICE_PORT_DVOB 0x01
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#define DEVICE_PORT_DVOC 0x02
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/*
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* We used to keep this struct but without any version control. We should avoid
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* using it in the future, but it should be safe to keep using it in the old
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* code. Do not change; we rely on its size.
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*/
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struct old_child_dev_config {
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u16 handle;
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u16 device_type;
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u8 device_id[10]; /* ascii string */
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u16 addin_offset;
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u8 dvo_port; /* See Device_PORT_* above */
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u8 i2c_pin;
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u8 slave_addr;
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u8 ddc_pin;
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u16 edid_ptr;
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u8 dvo_cfg; /* See DEVICE_CFG_* above */
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u8 dvo2_port;
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u8 i2c2_pin;
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u8 slave2_addr;
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u8 ddc2_pin;
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u8 capabilities;
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u8 dvo_wiring;/* See DEVICE_WIRE_* above */
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u8 dvo2_wiring;
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u16 extended_type;
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u8 dvo_function;
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} __packed;
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/* This one contains field offsets that are known to be common for all BDB
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* versions. Notice that the meaning of the contents contents may still change,
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* but at least the offsets are consistent. */
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/* Definitions for flags_1 */
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#define IBOOST_ENABLE (1<<3)
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struct common_child_dev_config {
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u16 handle;
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u16 device_type;
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u8 not_common1[12];
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u8 dvo_port;
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u8 not_common2[2];
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u8 ddc_pin;
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u16 edid_ptr;
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u8 obsolete;
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u8 flags_1;
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u8 not_common3[13];
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u8 iboost_level;
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} __packed;
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/* This field changes depending on the BDB version, so the most reliable way to
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* read it is by checking the BDB version and reading the raw pointer. */
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union child_device_config {
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/* This one is safe to be used anywhere, but the code should still check
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* the BDB version. */
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u8 raw[33];
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/* This one should only be kept for legacy code. */
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struct old_child_dev_config old;
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/* This one should also be safe to use anywhere, even without version
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* checks. */
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struct common_child_dev_config common;
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} __packed;
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struct bdb_general_definitions {
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/* DDC GPIO */
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u8 crt_ddc_gmbus_pin;
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/* DPMS bits */
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u8 dpms_acpi:1;
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u8 skip_boot_crt_detect:1;
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u8 dpms_aim:1;
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u8 rsvd1:5; /* finish byte */
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/* boot device bits */
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u8 boot_display[2];
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u8 child_dev_size;
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/*
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* Device info:
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* If TV is present, it'll be at devices[0].
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* LVDS will be next, either devices[0] or [1], if present.
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* On some platforms the number of device is 6. But could be as few as
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* 4 if both TV and LVDS are missing.
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* And the device num is related with the size of general definition
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* block. It is obtained by using the following formula:
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* number = (block_size - sizeof(bdb_general_definitions))/
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* defs->child_dev_size;
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*/
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uint8_t devices[0];
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} __packed;
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/* Mask for DRRS / Panel Channel / SSC / BLT control bits extraction */
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#define MODE_MASK 0x3
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struct bdb_lvds_options {
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u8 panel_type;
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u8 rsvd1;
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/* LVDS capabilities, stored in a dword */
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u8 pfit_mode:2;
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u8 pfit_text_mode_enhanced:1;
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u8 pfit_gfx_mode_enhanced:1;
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u8 pfit_ratio_auto:1;
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u8 pixel_dither:1;
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u8 lvds_edid:1;
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u8 rsvd2:1;
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u8 rsvd4;
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/* LVDS Panel channel bits stored here */
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u32 lvds_panel_channel_bits;
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/* LVDS SSC (Spread Spectrum Clock) bits stored here. */
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u16 ssc_bits;
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u16 ssc_freq;
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u16 ssc_ddt;
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/* Panel color depth defined here */
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u16 panel_color_depth;
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/* LVDS panel type bits stored here */
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u32 dps_panel_type_bits;
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/* LVDS backlight control type bits stored here */
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u32 blt_control_type_bits;
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} __packed;
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/* LFP pointer table contains entries to the struct below */
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struct bdb_lvds_lfp_data_ptr {
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u16 fp_timing_offset; /* offsets are from start of bdb */
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u8 fp_table_size;
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u16 dvo_timing_offset;
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u8 dvo_table_size;
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u16 panel_pnp_id_offset;
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u8 pnp_table_size;
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} __packed;
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struct bdb_lvds_lfp_data_ptrs {
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u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */
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struct bdb_lvds_lfp_data_ptr ptr[16];
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} __packed;
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/* LFP data has 3 blocks per entry */
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struct lvds_fp_timing {
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u16 x_res;
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u16 y_res;
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u32 lvds_reg;
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u32 lvds_reg_val;
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u32 pp_on_reg;
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u32 pp_on_reg_val;
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u32 pp_off_reg;
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u32 pp_off_reg_val;
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u32 pp_cycle_reg;
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u32 pp_cycle_reg_val;
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u32 pfit_reg;
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u32 pfit_reg_val;
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u16 terminator;
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} __packed;
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struct lvds_dvo_timing {
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u16 clock; /**< In 10khz */
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u8 hactive_lo;
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u8 hblank_lo;
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u8 hblank_hi:4;
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u8 hactive_hi:4;
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u8 vactive_lo;
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u8 vblank_lo;
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u8 vblank_hi:4;
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u8 vactive_hi:4;
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u8 hsync_off_lo;
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u8 hsync_pulse_width;
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u8 vsync_pulse_width:4;
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u8 vsync_off:4;
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u8 rsvd0:6;
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u8 hsync_off_hi:2;
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u8 h_image;
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u8 v_image;
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u8 max_hv;
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u8 h_border;
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u8 v_border;
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u8 rsvd1:3;
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u8 digital:2;
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u8 vsync_positive:1;
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u8 hsync_positive:1;
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u8 rsvd2:1;
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} __packed;
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struct lvds_pnp_id {
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u16 mfg_name;
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u16 product_code;
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u32 serial;
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u8 mfg_week;
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u8 mfg_year;
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} __packed;
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struct bdb_lvds_lfp_data_entry {
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struct lvds_fp_timing fp_timing;
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struct lvds_dvo_timing dvo_timing;
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struct lvds_pnp_id pnp_id;
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} __packed;
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struct bdb_lvds_lfp_data {
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struct bdb_lvds_lfp_data_entry data[16];
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} __packed;
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#define BDB_BACKLIGHT_TYPE_NONE 0
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#define BDB_BACKLIGHT_TYPE_PWM 2
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struct bdb_lfp_backlight_data_entry {
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u8 type:2;
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u8 active_low_pwm:1;
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u8 obsolete1:5;
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u16 pwm_freq_hz;
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u8 min_brightness;
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u8 obsolete2;
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u8 obsolete3;
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} __packed;
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struct bdb_lfp_backlight_data {
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u8 entry_size;
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struct bdb_lfp_backlight_data_entry data[16];
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u8 level[16];
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} __packed;
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struct aimdb_header {
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char signature[16];
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char oem_device[20];
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u16 aimdb_version;
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u16 aimdb_header_size;
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u16 aimdb_size;
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} __packed;
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struct aimdb_block {
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u8 aimdb_id;
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u16 aimdb_size;
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} __packed;
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struct vch_panel_data {
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u16 fp_timing_offset;
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u8 fp_timing_size;
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u16 dvo_timing_offset;
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u8 dvo_timing_size;
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u16 text_fitting_offset;
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u8 text_fitting_size;
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u16 graphics_fitting_offset;
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u8 graphics_fitting_size;
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} __packed;
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struct vch_bdb_22 {
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struct aimdb_block aimdb_block;
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struct vch_panel_data panels[16];
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} __packed;
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struct bdb_sdvo_lvds_options {
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u8 panel_backlight;
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u8 h40_set_panel_type;
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u8 panel_type;
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u8 ssc_clk_freq;
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u16 als_low_trip;
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u16 als_high_trip;
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u8 sclalarcoeff_tab_row_num;
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|
u8 sclalarcoeff_tab_row_size;
|
|
u8 coefficient[8];
|
|
u8 panel_misc_bits_1;
|
|
u8 panel_misc_bits_2;
|
|
u8 panel_misc_bits_3;
|
|
u8 panel_misc_bits_4;
|
|
} __packed;
|
|
|
|
|
|
#define BDB_DRIVER_FEATURE_NO_LVDS 0
|
|
#define BDB_DRIVER_FEATURE_INT_LVDS 1
|
|
#define BDB_DRIVER_FEATURE_SDVO_LVDS 2
|
|
#define BDB_DRIVER_FEATURE_EDP 3
|
|
|
|
struct bdb_driver_features {
|
|
u8 boot_dev_algorithm:1;
|
|
u8 block_display_switch:1;
|
|
u8 allow_display_switch:1;
|
|
u8 hotplug_dvo:1;
|
|
u8 dual_view_zoom:1;
|
|
u8 int15h_hook:1;
|
|
u8 sprite_in_clone:1;
|
|
u8 primary_lfp_id:1;
|
|
|
|
u16 boot_mode_x;
|
|
u16 boot_mode_y;
|
|
u8 boot_mode_bpp;
|
|
u8 boot_mode_refresh;
|
|
|
|
u16 enable_lfp_primary:1;
|
|
u16 selective_mode_pruning:1;
|
|
u16 dual_frequency:1;
|
|
u16 render_clock_freq:1; /* 0: high freq; 1: low freq */
|
|
u16 nt_clone_support:1;
|
|
u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */
|
|
u16 sprite_display_assign:1; /* 0: secondary; 1: primary */
|
|
u16 cui_aspect_scaling:1;
|
|
u16 preserve_aspect_ratio:1;
|
|
u16 sdvo_device_power_down:1;
|
|
u16 crt_hotplug:1;
|
|
u16 lvds_config:2;
|
|
u16 tv_hotplug:1;
|
|
u16 hdmi_config:2;
|
|
|
|
u8 static_display:1;
|
|
u8 reserved2:7;
|
|
u16 legacy_crt_max_x;
|
|
u16 legacy_crt_max_y;
|
|
u8 legacy_crt_max_refresh;
|
|
|
|
u8 hdmi_termination;
|
|
u8 custom_vbt_version;
|
|
/* Driver features data block */
|
|
u16 rmpm_enabled:1;
|
|
u16 s2ddt_enabled:1;
|
|
u16 dpst_enabled:1;
|
|
u16 bltclt_enabled:1;
|
|
u16 adb_enabled:1;
|
|
u16 drrs_enabled:1;
|
|
u16 grs_enabled:1;
|
|
u16 gpmt_enabled:1;
|
|
u16 tbt_enabled:1;
|
|
u16 psr_enabled:1;
|
|
u16 ips_enabled:1;
|
|
u16 reserved3:4;
|
|
u16 pc_feature_valid:1;
|
|
} __packed;
|
|
|
|
#define EDP_18BPP 0
|
|
#define EDP_24BPP 1
|
|
#define EDP_30BPP 2
|
|
#define EDP_RATE_1_62 0
|
|
#define EDP_RATE_2_7 1
|
|
#define EDP_LANE_1 0
|
|
#define EDP_LANE_2 1
|
|
#define EDP_LANE_4 3
|
|
#define EDP_PREEMPHASIS_NONE 0
|
|
#define EDP_PREEMPHASIS_3_5dB 1
|
|
#define EDP_PREEMPHASIS_6dB 2
|
|
#define EDP_PREEMPHASIS_9_5dB 3
|
|
#define EDP_VSWING_0_4V 0
|
|
#define EDP_VSWING_0_6V 1
|
|
#define EDP_VSWING_0_8V 2
|
|
#define EDP_VSWING_1_2V 3
|
|
|
|
struct edp_power_seq {
|
|
u16 t1_t3;
|
|
u16 t8;
|
|
u16 t9;
|
|
u16 t10;
|
|
u16 t11_t12;
|
|
} __packed;
|
|
|
|
struct edp_link_params {
|
|
u8 rate:4;
|
|
u8 lanes:4;
|
|
u8 preemphasis:4;
|
|
u8 vswing:4;
|
|
} __packed;
|
|
|
|
struct bdb_edp {
|
|
struct edp_power_seq power_seqs[16];
|
|
u32 color_depth;
|
|
struct edp_link_params link_params[16];
|
|
u32 sdrrs_msa_timing_delay;
|
|
|
|
/* ith bit indicates enabled/disabled for (i+1)th panel */
|
|
u16 edp_s3d_feature;
|
|
u16 edp_t3_optimization;
|
|
u64 edp_vswing_preemph; /* v173 */
|
|
} __packed;
|
|
|
|
struct psr_table {
|
|
/* Feature bits */
|
|
u8 full_link:1;
|
|
u8 require_aux_to_wakeup:1;
|
|
u8 feature_bits_rsvd:6;
|
|
|
|
/* Wait times */
|
|
u8 idle_frames:4;
|
|
u8 lines_to_wait:3;
|
|
u8 wait_times_rsvd:1;
|
|
|
|
/* TP wake up time in multiple of 100 */
|
|
u16 tp1_wakeup_time;
|
|
u16 tp2_tp3_wakeup_time;
|
|
} __packed;
|
|
|
|
struct bdb_psr {
|
|
struct psr_table psr_table[16];
|
|
} __packed;
|
|
|
|
/*
|
|
* Driver<->VBIOS interaction occurs through scratch bits in
|
|
* GR18 & SWF*.
|
|
*/
|
|
|
|
/* GR18 bits are set on display switch and hotkey events */
|
|
#define GR18_DRIVER_SWITCH_EN (1<<7) /* 0: VBIOS control, 1: driver control */
|
|
#define GR18_HOTKEY_MASK 0x78 /* See also SWF4 15:0 */
|
|
#define GR18_HK_NONE (0x0<<3)
|
|
#define GR18_HK_LFP_STRETCH (0x1<<3)
|
|
#define GR18_HK_TOGGLE_DISP (0x2<<3)
|
|
#define GR18_HK_DISP_SWITCH (0x4<<3) /* see SWF14 15:0 for what to enable */
|
|
#define GR18_HK_POPUP_DISABLED (0x6<<3)
|
|
#define GR18_HK_POPUP_ENABLED (0x7<<3)
|
|
#define GR18_HK_PFIT (0x8<<3)
|
|
#define GR18_HK_APM_CHANGE (0xa<<3)
|
|
#define GR18_HK_MULTIPLE (0xc<<3)
|
|
#define GR18_USER_INT_EN (1<<2)
|
|
#define GR18_A0000_FLUSH_EN (1<<1)
|
|
#define GR18_SMM_EN (1<<0)
|
|
|
|
/* Set by driver, cleared by VBIOS */
|
|
#define SWF00_YRES_SHIFT 16
|
|
#define SWF00_XRES_SHIFT 0
|
|
#define SWF00_RES_MASK 0xffff
|
|
|
|
/* Set by VBIOS at boot time and driver at runtime */
|
|
#define SWF01_TV2_FORMAT_SHIFT 8
|
|
#define SWF01_TV1_FORMAT_SHIFT 0
|
|
#define SWF01_TV_FORMAT_MASK 0xffff
|
|
|
|
#define SWF10_VBIOS_BLC_I2C_EN (1<<29)
|
|
#define SWF10_GTT_OVERRIDE_EN (1<<28)
|
|
#define SWF10_LFP_DPMS_OVR (1<<27) /* override DPMS on display switch */
|
|
#define SWF10_ACTIVE_TOGGLE_LIST_MASK (7<<24)
|
|
#define SWF10_OLD_TOGGLE 0x0
|
|
#define SWF10_TOGGLE_LIST_1 0x1
|
|
#define SWF10_TOGGLE_LIST_2 0x2
|
|
#define SWF10_TOGGLE_LIST_3 0x3
|
|
#define SWF10_TOGGLE_LIST_4 0x4
|
|
#define SWF10_PANNING_EN (1<<23)
|
|
#define SWF10_DRIVER_LOADED (1<<22)
|
|
#define SWF10_EXTENDED_DESKTOP (1<<21)
|
|
#define SWF10_EXCLUSIVE_MODE (1<<20)
|
|
#define SWF10_OVERLAY_EN (1<<19)
|
|
#define SWF10_PLANEB_HOLDOFF (1<<18)
|
|
#define SWF10_PLANEA_HOLDOFF (1<<17)
|
|
#define SWF10_VGA_HOLDOFF (1<<16)
|
|
#define SWF10_ACTIVE_DISP_MASK 0xffff
|
|
#define SWF10_PIPEB_LFP2 (1<<15)
|
|
#define SWF10_PIPEB_EFP2 (1<<14)
|
|
#define SWF10_PIPEB_TV2 (1<<13)
|
|
#define SWF10_PIPEB_CRT2 (1<<12)
|
|
#define SWF10_PIPEB_LFP (1<<11)
|
|
#define SWF10_PIPEB_EFP (1<<10)
|
|
#define SWF10_PIPEB_TV (1<<9)
|
|
#define SWF10_PIPEB_CRT (1<<8)
|
|
#define SWF10_PIPEA_LFP2 (1<<7)
|
|
#define SWF10_PIPEA_EFP2 (1<<6)
|
|
#define SWF10_PIPEA_TV2 (1<<5)
|
|
#define SWF10_PIPEA_CRT2 (1<<4)
|
|
#define SWF10_PIPEA_LFP (1<<3)
|
|
#define SWF10_PIPEA_EFP (1<<2)
|
|
#define SWF10_PIPEA_TV (1<<1)
|
|
#define SWF10_PIPEA_CRT (1<<0)
|
|
|
|
#define SWF11_MEMORY_SIZE_SHIFT 16
|
|
#define SWF11_SV_TEST_EN (1<<15)
|
|
#define SWF11_IS_AGP (1<<14)
|
|
#define SWF11_DISPLAY_HOLDOFF (1<<13)
|
|
#define SWF11_DPMS_REDUCED (1<<12)
|
|
#define SWF11_IS_VBE_MODE (1<<11)
|
|
#define SWF11_PIPEB_ACCESS (1<<10) /* 0 here means pipe a */
|
|
#define SWF11_DPMS_MASK 0x07
|
|
#define SWF11_DPMS_OFF (1<<2)
|
|
#define SWF11_DPMS_SUSPEND (1<<1)
|
|
#define SWF11_DPMS_STANDBY (1<<0)
|
|
#define SWF11_DPMS_ON 0
|
|
|
|
#define SWF14_GFX_PFIT_EN (1<<31)
|
|
#define SWF14_TEXT_PFIT_EN (1<<30)
|
|
#define SWF14_LID_STATUS_CLOSED (1<<29) /* 0 here means open */
|
|
#define SWF14_POPUP_EN (1<<28)
|
|
#define SWF14_DISPLAY_HOLDOFF (1<<27)
|
|
#define SWF14_DISP_DETECT_EN (1<<26)
|
|
#define SWF14_DOCKING_STATUS_DOCKED (1<<25) /* 0 here means undocked */
|
|
#define SWF14_DRIVER_STATUS (1<<24)
|
|
#define SWF14_OS_TYPE_WIN9X (1<<23)
|
|
#define SWF14_OS_TYPE_WINNT (1<<22)
|
|
/* 21:19 rsvd */
|
|
#define SWF14_PM_TYPE_MASK 0x00070000
|
|
#define SWF14_PM_ACPI_VIDEO (0x4 << 16)
|
|
#define SWF14_PM_ACPI (0x3 << 16)
|
|
#define SWF14_PM_APM_12 (0x2 << 16)
|
|
#define SWF14_PM_APM_11 (0x1 << 16)
|
|
#define SWF14_HK_REQUEST_MASK 0x0000ffff /* see GR18 6:3 for event type */
|
|
/* if GR18 indicates a display switch */
|
|
#define SWF14_DS_PIPEB_LFP2_EN (1<<15)
|
|
#define SWF14_DS_PIPEB_EFP2_EN (1<<14)
|
|
#define SWF14_DS_PIPEB_TV2_EN (1<<13)
|
|
#define SWF14_DS_PIPEB_CRT2_EN (1<<12)
|
|
#define SWF14_DS_PIPEB_LFP_EN (1<<11)
|
|
#define SWF14_DS_PIPEB_EFP_EN (1<<10)
|
|
#define SWF14_DS_PIPEB_TV_EN (1<<9)
|
|
#define SWF14_DS_PIPEB_CRT_EN (1<<8)
|
|
#define SWF14_DS_PIPEA_LFP2_EN (1<<7)
|
|
#define SWF14_DS_PIPEA_EFP2_EN (1<<6)
|
|
#define SWF14_DS_PIPEA_TV2_EN (1<<5)
|
|
#define SWF14_DS_PIPEA_CRT2_EN (1<<4)
|
|
#define SWF14_DS_PIPEA_LFP_EN (1<<3)
|
|
#define SWF14_DS_PIPEA_EFP_EN (1<<2)
|
|
#define SWF14_DS_PIPEA_TV_EN (1<<1)
|
|
#define SWF14_DS_PIPEA_CRT_EN (1<<0)
|
|
/* if GR18 indicates a panel fitting request */
|
|
#define SWF14_PFIT_EN (1<<0) /* 0 means disable */
|
|
/* if GR18 indicates an APM change request */
|
|
#define SWF14_APM_HIBERNATE 0x4
|
|
#define SWF14_APM_SUSPEND 0x3
|
|
#define SWF14_APM_STANDBY 0x1
|
|
#define SWF14_APM_RESTORE 0x0
|
|
|
|
/* Add the device class for LFP, TV, HDMI */
|
|
#define DEVICE_TYPE_INT_LFP 0x1022
|
|
#define DEVICE_TYPE_INT_TV 0x1009
|
|
#define DEVICE_TYPE_HDMI 0x60D2
|
|
#define DEVICE_TYPE_DP 0x68C6
|
|
#define DEVICE_TYPE_eDP 0x78C6
|
|
|
|
#define DEVICE_TYPE_CLASS_EXTENSION (1 << 15)
|
|
#define DEVICE_TYPE_POWER_MANAGEMENT (1 << 14)
|
|
#define DEVICE_TYPE_HOTPLUG_SIGNALING (1 << 13)
|
|
#define DEVICE_TYPE_INTERNAL_CONNECTOR (1 << 12)
|
|
#define DEVICE_TYPE_NOT_HDMI_OUTPUT (1 << 11)
|
|
#define DEVICE_TYPE_MIPI_OUTPUT (1 << 10)
|
|
#define DEVICE_TYPE_COMPOSITE_OUTPUT (1 << 9)
|
|
#define DEVICE_TYPE_DUAL_CHANNEL (1 << 8)
|
|
#define DEVICE_TYPE_HIGH_SPEED_LINK (1 << 6)
|
|
#define DEVICE_TYPE_LVDS_SINGALING (1 << 5)
|
|
#define DEVICE_TYPE_TMDS_DVI_SIGNALING (1 << 4)
|
|
#define DEVICE_TYPE_VIDEO_SIGNALING (1 << 3)
|
|
#define DEVICE_TYPE_DISPLAYPORT_OUTPUT (1 << 2)
|
|
#define DEVICE_TYPE_DIGITAL_OUTPUT (1 << 1)
|
|
#define DEVICE_TYPE_ANALOG_OUTPUT (1 << 0)
|
|
|
|
/*
|
|
* Bits we care about when checking for DEVICE_TYPE_eDP
|
|
* Depending on the system, the other bits may or may not
|
|
* be set for eDP outputs.
|
|
*/
|
|
#define DEVICE_TYPE_eDP_BITS \
|
|
(DEVICE_TYPE_INTERNAL_CONNECTOR | \
|
|
DEVICE_TYPE_MIPI_OUTPUT | \
|
|
DEVICE_TYPE_COMPOSITE_OUTPUT | \
|
|
DEVICE_TYPE_DUAL_CHANNEL | \
|
|
DEVICE_TYPE_LVDS_SINGALING | \
|
|
DEVICE_TYPE_TMDS_DVI_SIGNALING | \
|
|
DEVICE_TYPE_VIDEO_SIGNALING | \
|
|
DEVICE_TYPE_DISPLAYPORT_OUTPUT | \
|
|
DEVICE_TYPE_ANALOG_OUTPUT)
|
|
|
|
/* define the DVO port for HDMI output type */
|
|
#define DVO_B 1
|
|
#define DVO_C 2
|
|
#define DVO_D 3
|
|
|
|
/* Possible values for the "DVO Port" field for versions >= 155: */
|
|
#define DVO_PORT_HDMIA 0
|
|
#define DVO_PORT_HDMIB 1
|
|
#define DVO_PORT_HDMIC 2
|
|
#define DVO_PORT_HDMID 3
|
|
#define DVO_PORT_LVDS 4
|
|
#define DVO_PORT_TV 5
|
|
#define DVO_PORT_CRT 6
|
|
#define DVO_PORT_DPB 7
|
|
#define DVO_PORT_DPC 8
|
|
#define DVO_PORT_DPD 9
|
|
#define DVO_PORT_DPA 10
|
|
#define DVO_PORT_DPE 11
|
|
#define DVO_PORT_HDMIE 12
|
|
#define DVO_PORT_MIPIA 21
|
|
#define DVO_PORT_MIPIB 22
|
|
#define DVO_PORT_MIPIC 23
|
|
#define DVO_PORT_MIPID 24
|
|
|
|
/* Block 52 contains MIPI Panel info
|
|
* 6 such enteries will there. Index into correct
|
|
* entery is based on the panel_index in #40 LFP
|
|
*/
|
|
#define MAX_MIPI_CONFIGURATIONS 6
|
|
|
|
#define MIPI_DSI_UNDEFINED_PANEL_ID 0
|
|
#define MIPI_DSI_GENERIC_PANEL_ID 1
|
|
|
|
/*
|
|
* PMIC vs SoC Backlight support specified in pwm_blc
|
|
* field in mipi_config block below.
|
|
*/
|
|
#define PPS_BLC_PMIC 0
|
|
#define PPS_BLC_SOC 1
|
|
|
|
struct mipi_config {
|
|
u16 panel_id;
|
|
|
|
/* General Params */
|
|
u32 enable_dithering:1;
|
|
u32 rsvd1:1;
|
|
u32 is_bridge:1;
|
|
|
|
u32 panel_arch_type:2;
|
|
u32 is_cmd_mode:1;
|
|
|
|
#define NON_BURST_SYNC_PULSE 0x1
|
|
#define NON_BURST_SYNC_EVENTS 0x2
|
|
#define BURST_MODE 0x3
|
|
u32 video_transfer_mode:2;
|
|
|
|
u32 cabc_supported:1;
|
|
u32 pwm_blc:1;
|
|
|
|
/* Bit 13:10 */
|
|
#define PIXEL_FORMAT_RGB565 0x1
|
|
#define PIXEL_FORMAT_RGB666 0x2
|
|
#define PIXEL_FORMAT_RGB666_LOOSELY_PACKED 0x3
|
|
#define PIXEL_FORMAT_RGB888 0x4
|
|
u32 videomode_color_format:4;
|
|
|
|
/* Bit 15:14 */
|
|
#define ENABLE_ROTATION_0 0x0
|
|
#define ENABLE_ROTATION_90 0x1
|
|
#define ENABLE_ROTATION_180 0x2
|
|
#define ENABLE_ROTATION_270 0x3
|
|
u32 rotation:2;
|
|
u32 bta_enabled:1;
|
|
u32 rsvd2:15;
|
|
|
|
/* 2 byte Port Description */
|
|
#define DUAL_LINK_NOT_SUPPORTED 0
|
|
#define DUAL_LINK_FRONT_BACK 1
|
|
#define DUAL_LINK_PIXEL_ALT 2
|
|
u16 dual_link:2;
|
|
u16 lane_cnt:2;
|
|
u16 pixel_overlap:3;
|
|
u16 rsvd3:9;
|
|
|
|
u16 rsvd4;
|
|
|
|
u8 rsvd5;
|
|
u32 target_burst_mode_freq;
|
|
u32 dsi_ddr_clk;
|
|
u32 bridge_ref_clk;
|
|
|
|
#define BYTE_CLK_SEL_20MHZ 0
|
|
#define BYTE_CLK_SEL_10MHZ 1
|
|
#define BYTE_CLK_SEL_5MHZ 2
|
|
u8 byte_clk_sel:2;
|
|
|
|
u8 rsvd6:6;
|
|
|
|
/* DPHY Flags */
|
|
u16 dphy_param_valid:1;
|
|
u16 eot_pkt_disabled:1;
|
|
u16 enable_clk_stop:1;
|
|
u16 rsvd7:13;
|
|
|
|
u32 hs_tx_timeout;
|
|
u32 lp_rx_timeout;
|
|
u32 turn_around_timeout;
|
|
u32 device_reset_timer;
|
|
u32 master_init_timer;
|
|
u32 dbi_bw_timer;
|
|
u32 lp_byte_clk_val;
|
|
|
|
/* 4 byte Dphy Params */
|
|
u32 prepare_cnt:6;
|
|
u32 rsvd8:2;
|
|
u32 clk_zero_cnt:8;
|
|
u32 trail_cnt:5;
|
|
u32 rsvd9:3;
|
|
u32 exit_zero_cnt:6;
|
|
u32 rsvd10:2;
|
|
|
|
u32 clk_lane_switch_cnt;
|
|
u32 hl_switch_cnt;
|
|
|
|
u32 rsvd11[6];
|
|
|
|
/* timings based on dphy spec */
|
|
u8 tclk_miss;
|
|
u8 tclk_post;
|
|
u8 rsvd12;
|
|
u8 tclk_pre;
|
|
u8 tclk_prepare;
|
|
u8 tclk_settle;
|
|
u8 tclk_term_enable;
|
|
u8 tclk_trail;
|
|
u16 tclk_prepare_clkzero;
|
|
u8 rsvd13;
|
|
u8 td_term_enable;
|
|
u8 teot;
|
|
u8 ths_exit;
|
|
u8 ths_prepare;
|
|
u16 ths_prepare_hszero;
|
|
u8 rsvd14;
|
|
u8 ths_settle;
|
|
u8 ths_skip;
|
|
u8 ths_trail;
|
|
u8 tinit;
|
|
u8 tlpx;
|
|
u8 rsvd15[3];
|
|
|
|
/* GPIOs */
|
|
u8 panel_enable;
|
|
u8 bl_enable;
|
|
u8 pwm_enable;
|
|
u8 reset_r_n;
|
|
u8 pwr_down_r;
|
|
u8 stdby_r_n;
|
|
|
|
} __packed;
|
|
|
|
/* Block 52 contains MIPI configuration block
|
|
* 6 * bdb_mipi_config, followed by 6 pps data
|
|
* block below
|
|
*
|
|
* all delays has a unit of 100us
|
|
*/
|
|
struct mipi_pps_data {
|
|
u16 panel_on_delay;
|
|
u16 bl_enable_delay;
|
|
u16 bl_disable_delay;
|
|
u16 panel_off_delay;
|
|
u16 panel_power_cycle_delay;
|
|
} __packed;
|
|
|
|
struct bdb_mipi_config {
|
|
struct mipi_config config[MAX_MIPI_CONFIGURATIONS];
|
|
struct mipi_pps_data pps[MAX_MIPI_CONFIGURATIONS];
|
|
} __packed;
|
|
|
|
/* Block 53 contains MIPI sequences as needed by the panel
|
|
* for enabling it. This block can be variable in size and
|
|
* can be maximum of 6 blocks
|
|
*/
|
|
struct bdb_mipi_sequence {
|
|
u8 version;
|
|
u8 data[0];
|
|
} __packed;
|
|
|
|
/* MIPI Sequnece Block definitions */
|
|
enum mipi_seq {
|
|
MIPI_SEQ_END = 0,
|
|
MIPI_SEQ_ASSERT_RESET,
|
|
MIPI_SEQ_INIT_OTP,
|
|
MIPI_SEQ_DISPLAY_ON,
|
|
MIPI_SEQ_DISPLAY_OFF,
|
|
MIPI_SEQ_DEASSERT_RESET,
|
|
MIPI_SEQ_BACKLIGHT_ON, /* sequence block v2+ */
|
|
MIPI_SEQ_BACKLIGHT_OFF, /* sequence block v2+ */
|
|
MIPI_SEQ_TEAR_ON, /* sequence block v2+ */
|
|
MIPI_SEQ_TEAR_OFF, /* sequence block v3+ */
|
|
MIPI_SEQ_POWER_ON, /* sequence block v3+ */
|
|
MIPI_SEQ_POWER_OFF, /* sequence block v3+ */
|
|
MIPI_SEQ_MAX
|
|
};
|
|
|
|
enum mipi_seq_element {
|
|
MIPI_SEQ_ELEM_END = 0,
|
|
MIPI_SEQ_ELEM_SEND_PKT,
|
|
MIPI_SEQ_ELEM_DELAY,
|
|
MIPI_SEQ_ELEM_GPIO,
|
|
MIPI_SEQ_ELEM_I2C, /* sequence block v2+ */
|
|
MIPI_SEQ_ELEM_SPI, /* sequence block v3+ */
|
|
MIPI_SEQ_ELEM_PMIC, /* sequence block v3+ */
|
|
MIPI_SEQ_ELEM_MAX
|
|
};
|
|
|
|
enum mipi_gpio_pin_index {
|
|
MIPI_GPIO_UNDEFINED = 0,
|
|
MIPI_GPIO_PANEL_ENABLE,
|
|
MIPI_GPIO_BL_ENABLE,
|
|
MIPI_GPIO_PWM_ENABLE,
|
|
MIPI_GPIO_RESET_N,
|
|
MIPI_GPIO_PWR_DOWN_R,
|
|
MIPI_GPIO_STDBY_RST_N,
|
|
MIPI_GPIO_MAX
|
|
};
|
|
|
|
#endif /* _INTEL_BIOS_H_ */
|