168 lines
5.7 KiB
NASM
168 lines
5.7 KiB
NASM
;*****************************************************************************
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;*
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;* Open Watcom Project
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;*
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;* Portions Copyright (c) 1983-2002 Sybase, Inc. All Rights Reserved.
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;*
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;* ========================================================================
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;*
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;* This file contains Original Code and/or Modifications of Original
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;* Code as defined in and that are subject to the Sybase Open Watcom
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;* Public License version 1.0 (the 'License'). You may not use this file
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;* except in compliance with the License. BY USING THIS FILE YOU AGREE TO
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;* ALL TERMS AND CONDITIONS OF THE LICENSE. A copy of the License is
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;* provided with the Original Code and Modifications, and is also
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;* available at www.sybase.com/developer/opensource.
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;*
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;* The Original Code and all software distributed under the License are
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;* distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
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;* EXPRESS OR IMPLIED, AND SYBASE AND ALL CONTRIBUTORS HEREBY DISCLAIM
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;* ALL SUCH WARRANTIES, INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF
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;* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR
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;* NON-INFRINGEMENT. Please see the License for the specific language
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;* governing rights and limitations under the License.
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;*
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;* ========================================================================
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;*
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;* Description: WHEN YOU FIGURE OUT WHAT THIS FILE DOES, PLEASE
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;* DESCRIBE IT HERE!
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;*
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;*****************************************************************************
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; static char sccs_id[] = "@(#)fptan32.asm 1.4 12/20/94 16:51:51";
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;
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; This code is being published by Intel to users of the Pentium(tm)
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; processor. Recipients are authorized to copy, modify, compile, use and
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; distribute the code.
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;
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; Intel makes no warranty of any kind with regard to this code, including
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; but not limited to, implied warranties or merchantability and fitness for
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; a particular purpose. Intel assumes no responsibility for any errors that
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; may appear in this code.
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;
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; No patent licenses are granted, express or implied.
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;
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;
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; The following code is a PRELIMINARY IMPLEMENTATION of a
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; software patch for the floating point divide instructions.
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;
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;
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include mdef.inc
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.386
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.387
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PATCH_CW EQU 00ch
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PREV_CW EQU 010h
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COSINE EQU 0 ; These two are overlaid because they
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ANGLE EQU 0 ; are not live at the same time.
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STACK_SIZE EQU 014h
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ONESMASK EQU 0e000000h
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DATA32 SEGMENT DWORD USE32 PUBLIC 'DATA'
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fdiv_risk_table DB 0, 1, 0, 0, 4, 0, 0, 7, 0, 0, 10, 0, 0, 13, 0, 0
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fdiv_scale DD 03f700000h ; 0.9375
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one_shl_63 DD 05f000000h
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DATA32 ENDS
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DGROUP GROUP DATA32
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_TEXT SEGMENT DWORD USE32 PUBLIC 'CODE'
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assume cs:_TEXT, ds:DGROUP, es:DGROUP, ss:nothing
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public __fptan_chk
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;
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; PRELIMINARY VERSION for register-register divides.
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;
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defpe __fptan_chk
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push eax
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sub esp, STACK_SIZE
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fstp tbyte ptr [esp+ANGLE]
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mov eax, [esp+ANGLE+8]
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and eax, 07fffh
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jz use_hardware ; denormals, ...
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cmp eax, 07fffh
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je use_hardware ; NaNs, infinities, ...
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mov eax, [esp+ANGLE+4]
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add eax, eax
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jnc use_hardware ; unnormals (explicit 1 missing)
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fld tbyte ptr [esp+ANGLE]
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;
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; Check for proper parameter range ( |<angle>| < 2^63)
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;
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fabs
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fcomp one_shl_63
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fstsw ax
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sahf
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jae use_hardware
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fld tbyte ptr [esp+ANGLE]
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fsincos
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fstp tbyte ptr [esp+COSINE]
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fld tbyte ptr [esp+COSINE] ; load the denominator (cos(x))
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mov eax, [esp+COSINE+4] ; get mantissa bits 32-64
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add eax,eax ; shift the one's bit onto carry
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xor eax, ONESMASK ; invert the bits that must be ones
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test eax, ONESMASK ; and make sure they are all ones
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jz scale_if_needed ; if all are one scale numbers
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fdivp st(1), st ; use of hardware is OK.
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fld1 ; push 1.0 onto FPU stack
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add esp, STACK_SIZE
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pop eax
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ret
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scale_if_needed:
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shr eax, 28 ; keep first 4 bits after point
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cmp fdiv_risk_table[eax], ah ; check for (1,4,7,a,d)
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jnz divide_scaled ; are in potential problem area
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fdivp st(1), st ; use of hardware is OK.
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fld1 ; push 1.0 onto FPU stack
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add esp, STACK_SIZE
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pop eax
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ret
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divide_scaled:
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fwait ; catch preceding exceptions
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fstcw [esp+PREV_CW] ; save caller's control word
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mov eax, [esp+PREV_CW]
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or eax, 033fh ; mask exceptions, pc=80
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mov [esp+PATCH_CW], eax
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fldcw [esp+PATCH_CW] ; mask exceptions & pc=80
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fmul fdiv_scale ; scale denominator by 15/16
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fxch
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fmul fdiv_scale ; scale numerator by 15/16
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fxch
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; This assures correctly rounded result if pc=64 as well
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fldcw [esp+PREV_CW] ; restore caller's control word
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fdivp st(1), st ; use of hardware is OK.
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fld1 ; push 1.0 onto FPU stack
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add esp, STACK_SIZE
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pop eax
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ret
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use_hardware:
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fld tbyte ptr [esp+ANGLE]
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fptan
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add esp, STACK_SIZE
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pop eax
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ret
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__fptan_chk ENDP
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_TEXT ENDS
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end
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