115 lines
3.8 KiB
C
115 lines
3.8 KiB
C
/*
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* Copyright © 2010 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Zhou Chang <chang.zhou@intel.com>
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*
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*/
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#ifndef _GEN6_MFC_H_
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#define _GEN6_MFC_H_
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#include <xf86drm.h>
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#include <drm.h>
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#include <i915_drm.h>
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#include <intel_bufmgr.h>
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struct encode_state;
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#define MAX_MFC_REFERENCE_SURFACES 16
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#define NUM_MFC_DMV_BUFFERS 34
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struct gen6_mfc_context
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{
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struct {
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unsigned int width;
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unsigned int height;
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unsigned int w_pitch;
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unsigned int h_pitch;
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} surface_state;
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//MFX_PIPE_BUF_ADDR_STATE
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struct {
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dri_bo *bo;
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} post_deblocking_output; //OUTPUT: reconstructed picture
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struct {
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dri_bo *bo;
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} pre_deblocking_output; //OUTPUT: reconstructed picture with deblocked
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struct {
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dri_bo *bo;
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} uncompressed_picture_source; //INPUT: original compressed image
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struct {
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dri_bo *bo;
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} intra_row_store_scratch_buffer; //INTERNAL:
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struct {
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dri_bo *bo;
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} deblocking_filter_row_store_scratch_buffer; //INTERNAL:
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struct {
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dri_bo *bo;
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} reference_surfaces[MAX_MFC_REFERENCE_SURFACES]; //INTERNAL: refrence surfaces
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//MFX_IND_OBJ_BASE_ADDR_STATE
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struct{
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dri_bo *bo;
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} mfc_indirect_mv_object; //INPUT: the blocks' mv info
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struct {
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dri_bo *bo;
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int offset;
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} mfc_indirect_pak_bse_object; //OUTPUT: the compressed bitstream
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//MFX_BSP_BUF_BASE_ADDR_STATE
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struct {
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dri_bo *bo;
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}bsd_mpc_row_store_scratch_buffer; //INTERNAL:
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//MFX_AVC_DIRECTMODE_STATE
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struct {
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dri_bo *bo;
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}direct_mv_buffers[NUM_MFC_DMV_BUFFERS]; //INTERNAL: 0-31 as input,32 and 33 as output
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};
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VAStatus
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gen6_mfc_pipeline(VADriverContextP ctx,
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VAProfile profile,
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struct encode_state *encode_state,
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struct gen6_encoder_context *gen6_encoder_context);
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Bool gen6_mfc_context_init(VADriverContextP ctx, struct gen6_mfc_context *mfc_context);
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Bool gen6_mfc_context_destroy(struct gen6_mfc_context *mfc_context);
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VAStatus
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gen75_mfc_pipeline(VADriverContextP ctx,
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VAProfile profile,
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struct encode_state *encode_state,
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struct gen6_encoder_context *gen6_encoder_context);
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Bool gen75_mfc_context_init(VADriverContextP ctx, struct gen6_mfc_context *mfc_context);
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Bool gen75_mfc_context_destroy(struct gen6_mfc_context *mfc_context);
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#endif /* _GEN6_MFC_BCS_H_ */
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