623 lines
20 KiB
C
623 lines
20 KiB
C
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static Bool rhdMapMMIO(RHDPtr rhdPtr)
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{
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rhdPtr->MMIOMapSize = 1 << rhdPtr->memsize[RHD_MMIO_BAR];
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rhdPtr->MMIOBase = MapIoMem((void*)rhdPtr->memBase[RHD_MMIO_BAR],
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rhdPtr->MMIOMapSize,PG_SW+PG_NOCACHE);
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if( rhdPtr->MMIOBase==0)
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return 0;
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DBG(dbgprintf("Mapped IO at %x (size %x)\n", rhdPtr->MMIOBase, rhdPtr->MMIOMapSize));
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return 1;
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}
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/* Read MC register */
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unsigned INMC(RHDPtr info, int addr)
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{
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u32_t data;
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if ((info->ChipFamily == CHIP_FAMILY_RS690) ||
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(info->ChipFamily == CHIP_FAMILY_RS740)) {
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OUTREG(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
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data = INREG(RS690_MC_DATA);
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} else if (info->ChipFamily == CHIP_FAMILY_RS600) {
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OUTREG(RS600_MC_INDEX, (addr & RS600_MC_INDEX_MASK));
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data = INREG(RS600_MC_DATA);
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} else if (IS_AVIVO_VARIANT) {
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OUTREG(AVIVO_MC_INDEX, (addr & 0xff) | 0x7f0000);
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(void)INREG(AVIVO_MC_INDEX);
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data = INREG(AVIVO_MC_DATA);
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OUTREG(AVIVO_MC_INDEX, 0);
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(void)INREG(AVIVO_MC_INDEX);
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} else {
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OUTREG(R300_MC_IND_INDEX, addr & 0x3f);
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(void)INREG(R300_MC_IND_INDEX);
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data = INREG(R300_MC_IND_DATA);
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OUTREG(R300_MC_IND_INDEX, 0);
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(void)INREG(R300_MC_IND_INDEX);
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}
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return data;
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}
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#define LOC_FB 0x1
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#define LOC_AGP 0x2
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static void radeon_read_mc_fb_agp_location(RHDPtr info, int mask,
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u32_t *fb_loc, u32_t *agp_loc, u32_t *agp_loc_hi)
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{
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if (info->ChipFamily >= CHIP_FAMILY_RV770) {
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if (mask & LOC_FB)
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*fb_loc = INREG(R700_MC_VM_FB_LOCATION);
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if (mask & LOC_AGP) {
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*agp_loc = INREG(R600_MC_VM_AGP_BOT);
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*agp_loc_hi = INREG(R600_MC_VM_AGP_TOP);
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}
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} else if (info->ChipFamily >= CHIP_FAMILY_R600) {
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if (mask & LOC_FB)
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*fb_loc = INREG(R600_MC_VM_FB_LOCATION);
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if (mask & LOC_AGP) {
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*agp_loc = INREG(R600_MC_VM_AGP_BOT);
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*agp_loc_hi = INREG(R600_MC_VM_AGP_TOP);
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}
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} else if (info->ChipFamily == CHIP_FAMILY_RV515) {
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if (mask & LOC_FB)
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*fb_loc = INMC(info, RV515_MC_FB_LOCATION);
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if (mask & LOC_AGP) {
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*agp_loc = INMC(info, RV515_MC_AGP_LOCATION);
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*agp_loc_hi = 0;
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}
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} else if (info->ChipFamily == CHIP_FAMILY_RS600) {
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if (mask & LOC_FB)
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*fb_loc = INMC(info, RS600_MC_FB_LOCATION);
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if (mask & LOC_AGP) {
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*agp_loc = 0;//INMC(pScrn, RS600_MC_AGP_LOCATION);
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*agp_loc_hi = 0;
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}
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} else if ((info->ChipFamily == CHIP_FAMILY_RS690) ||
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(info->ChipFamily == CHIP_FAMILY_RS740)) {
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if (mask & LOC_FB)
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*fb_loc = INMC(info, RS690_MC_FB_LOCATION);
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if (mask & LOC_AGP) {
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*agp_loc = INMC(info, RS690_MC_AGP_LOCATION);
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*agp_loc_hi = 0;
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}
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} else if (info->ChipFamily >= CHIP_FAMILY_R520) {
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if (mask & LOC_FB)
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*fb_loc = INMC(info, R520_MC_FB_LOCATION);
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if (mask & LOC_AGP) {
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*agp_loc = INMC(info, R520_MC_AGP_LOCATION);
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*agp_loc_hi = 0;
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}
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} else {
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if (mask & LOC_FB)
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*fb_loc = INREG(RADEON_MC_FB_LOCATION);
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if (mask & LOC_AGP)
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*agp_loc = INREG(RADEON_MC_AGP_LOCATION);
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}
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}
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static void RADEONInitMemoryMap(RHDPtr info)
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{
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u32_t mem_size;
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u32_t aper_size;
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radeon_read_mc_fb_agp_location(info, LOC_FB | LOC_AGP, &info->mc_fb_location,
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&info->mc_agp_location, &info->mc_agp_location_hi);
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/* We shouldn't use info->videoRam here which might have been clipped
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* but the real video RAM instead
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*/
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if (info->ChipFamily >= CHIP_FAMILY_R600){
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mem_size = INREG(R600_CONFIG_MEMSIZE);
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aper_size = INREG(R600_CONFIG_APER_SIZE);
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}
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else {
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mem_size = INREG(RADEON_CONFIG_MEMSIZE);
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aper_size = INREG(RADEON_CONFIG_APER_SIZE);
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}
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if (mem_size == 0)
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mem_size = 0x800000;
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/* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
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Novell bug 204882 + along with lots of ubuntu ones */
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if (aper_size > mem_size)
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mem_size = aper_size;
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if ( (info->ChipFamily != CHIP_FAMILY_RS600) &&
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(info->ChipFamily != CHIP_FAMILY_RS690) &&
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(info->ChipFamily != CHIP_FAMILY_RS740)) {
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if (info->IsIGP)
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info->mc_fb_location = INREG(RADEON_NB_TOM);
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else
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{
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u32_t aper0_base;
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if (info->ChipFamily >= CHIP_FAMILY_R600) {
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aper0_base = INREG(R600_CONFIG_F0_BASE);
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}
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else {
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aper0_base = INREG(RADEON_CONFIG_APER_0_BASE);
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}
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/* Recent chips have an "issue" with the memory controller, the
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* location must be aligned to the size. We just align it down,
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* too bad if we walk over the top of system memory, we don't
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* use DMA without a remapped anyway.
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* Affected chips are rv280, all r3xx, and all r4xx, but not IGP
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*/
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if ( info->ChipFamily == CHIP_FAMILY_RV280 ||
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info->ChipFamily == CHIP_FAMILY_R300 ||
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info->ChipFamily == CHIP_FAMILY_R350 ||
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info->ChipFamily == CHIP_FAMILY_RV350 ||
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info->ChipFamily == CHIP_FAMILY_RV380 ||
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info->ChipFamily == CHIP_FAMILY_R420 ||
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info->ChipFamily == CHIP_FAMILY_RV410)
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aper0_base &= ~(mem_size - 1);
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if ( info->ChipFamily >= CHIP_FAMILY_R600) {
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info->mc_fb_location = (aper0_base >> 24) |
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(((aper0_base + mem_size - 1) & 0xff000000U) >> 8);
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dbgprintf("mc fb loc is %08x\n", (unsigned int)info->mc_fb_location);
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}
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else {
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info->mc_fb_location = (aper0_base >> 16) |
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((aper0_base + mem_size - 1) & 0xffff0000U);
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}
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}
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}
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if (info->ChipFamily >= CHIP_FAMILY_R600) {
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info->fbLocation = (info->mc_fb_location & 0xffff) << 24;
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}
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else {
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info->fbLocation = (info->mc_fb_location & 0xffff) << 16;
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}
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/* Just disable the damn AGP apertures for now, it may be
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* re-enabled later by the DRM
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*/
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if (IS_AVIVO_VARIANT) {
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if (info->ChipFamily >= CHIP_FAMILY_R600) {
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OUTREG(R600_HDP_NONSURFACE_BASE, (info->mc_fb_location << 16) & 0xff0000);
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}
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else {
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OUTREG(AVIVO_HDP_FB_LOCATION, info->mc_fb_location);
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}
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info->mc_agp_location = 0x003f0000;
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}
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else
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info->mc_agp_location = 0xffffffc0;
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dbgprintf("RADEONInitMemoryMap() : \n");
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dbgprintf(" mem_size : 0x%08x\n", (unsigned)mem_size);
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dbgprintf(" MC_FB_LOCATION : 0x%08x\n", (unsigned)info->mc_fb_location);
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dbgprintf(" MC_AGP_LOCATION : 0x%08x\n", (unsigned)info->mc_agp_location);
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}
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static void RADEONGetVRamType(RHDPtr info)
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{
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u32_t tmp;
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if (info->IsIGP || (info->ChipFamily >= CHIP_FAMILY_R300))
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info->IsDDR = TRUE;
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else if (INREG(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
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info->IsDDR = TRUE;
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else
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info->IsDDR = FALSE;
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if ( (info->ChipFamily >= CHIP_FAMILY_R600) &&
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(info->ChipFamily <= CHIP_FAMILY_RV635))
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{
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int chansize;
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/* r6xx */
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tmp = INREG(R600_RAMCFG);
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if (tmp & R600_CHANSIZE_OVERRIDE)
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chansize = 16;
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else if (tmp & R600_CHANSIZE)
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chansize = 64;
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else
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chansize = 32;
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if (info->ChipFamily == CHIP_FAMILY_R600)
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info->RamWidth = 8 * chansize;
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else if (info->ChipFamily == CHIP_FAMILY_RV670)
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info->RamWidth = 4 * chansize;
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else if ((info->ChipFamily == CHIP_FAMILY_RV610) ||
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(info->ChipFamily == CHIP_FAMILY_RV620))
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info->RamWidth = chansize;
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else if ((info->ChipFamily == CHIP_FAMILY_RV630) ||
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(info->ChipFamily == CHIP_FAMILY_RV635))
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info->RamWidth = 2 * chansize;
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}
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else if (info->ChipFamily == CHIP_FAMILY_RV515) {
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/* rv515/rv550 */
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tmp = INMC(info, RV515_MC_CNTL);
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tmp &= RV515_MEM_NUM_CHANNELS_MASK;
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switch (tmp) {
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case 0: info->RamWidth = 64; break;
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case 1: info->RamWidth = 128; break;
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default: info->RamWidth = 128; break;
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}
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}
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else if ((info->ChipFamily >= CHIP_FAMILY_R520) &&
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(info->ChipFamily <= CHIP_FAMILY_RV570)){
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/* r520/rv530/rv560/rv570/r580 */
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tmp = INMC(info, R520_MC_CNTL0);
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switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) {
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case 0: info->RamWidth = 32; break;
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case 1: info->RamWidth = 64; break;
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case 2: info->RamWidth = 128; break;
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case 3: info->RamWidth = 256; break;
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default: info->RamWidth = 64; break;
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}
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if (tmp & R520_MC_CHANNEL_SIZE) {
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info->RamWidth *= 2;
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}
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}
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else if ((info->ChipFamily >= CHIP_FAMILY_R300) &&
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(info->ChipFamily <= CHIP_FAMILY_RV410)) {
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/* r3xx, r4xx */
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tmp = INREG(RADEON_MEM_CNTL);
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tmp &= R300_MEM_NUM_CHANNELS_MASK;
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switch (tmp) {
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case 0: info->RamWidth = 64; break;
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case 1: info->RamWidth = 128; break;
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case 2: info->RamWidth = 256; break;
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default: info->RamWidth = 128; break;
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}
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}
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else if ((info->ChipFamily == CHIP_FAMILY_RV100) ||
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(info->ChipFamily == CHIP_FAMILY_RS100) ||
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(info->ChipFamily == CHIP_FAMILY_RS200)){
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tmp = INREG(RADEON_MEM_CNTL);
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if (tmp & RV100_HALF_MODE)
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info->RamWidth = 32;
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else
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info->RamWidth = 64;
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/// if (!info->HasCRTC2) {
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/// info->RamWidth /= 4;
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/// info->IsDDR = TRUE;
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/// }
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}
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else if (info->ChipFamily <= CHIP_FAMILY_RV280) {
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tmp = INREG(RADEON_MEM_CNTL);
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if (tmp & RADEON_MEM_NUM_CHANNELS_MASK)
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info->RamWidth = 128;
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else
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info->RamWidth = 64;
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} else {
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/* newer IGPs */
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info->RamWidth = 128;
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}
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/* This may not be correct, as some cards can have half of channel disabled
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* ToDo: identify these cases
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*/
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}
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/*
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* Depending on card genertation, chipset bugs, etc... the amount of vram
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* accessible to the CPU can vary. This function is our best shot at figuring
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* it out. Returns a value in KB.
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*/
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static u32_t RADEONGetAccessibleVRAM(RHDPtr info)
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{
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u32_t aper_size;
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unsigned char byte;
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if (info->ChipFamily >= CHIP_FAMILY_R600)
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aper_size = INREG(R600_CONFIG_APER_SIZE) / 1024;
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else
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aper_size = INREG(RADEON_CONFIG_APER_SIZE) / 1024;
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/* Set HDP_APER_CNTL only on cards that are known not to be broken,
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* that is has the 2nd generation multifunction PCI interface
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*/
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if (info->ChipFamily == CHIP_FAMILY_RV280 ||
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info->ChipFamily == CHIP_FAMILY_RV350 ||
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info->ChipFamily == CHIP_FAMILY_RV380 ||
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info->ChipFamily == CHIP_FAMILY_R420 ||
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info->ChipFamily == CHIP_FAMILY_RV410 ||
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IS_AVIVO_VARIANT) {
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MASKREG (RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
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~RADEON_HDP_APER_CNTL);
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dbgprintf("Generation 2 PCI interface, using max accessible memory\n");
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return aper_size * 2;
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}
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/* Older cards have all sorts of funny issues to deal with. First
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* check if it's a multifunction card by reading the PCI config
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* header type... Limit those to one aperture size
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*/
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// PCI_READ_BYTE(info->PciInfo, &byte, 0xe);
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// if (byte & 0x80) {
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// xf86DrvMsg(pScrn->scrnIndex, X_INFO,
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// "Generation 1 PCI interface in multifunction mode"
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// ", accessible memory limited to one aperture\n");
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// return aper_size;
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// }
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/* Single function older card. We read HDP_APER_CNTL to see how the BIOS
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* have set it up. We don't write this as it's broken on some ASICs but
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* we expect the BIOS to have done the right thing (might be too optimistic...)
|
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*/
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// if (INREG(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
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// return aper_size * 2;
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return aper_size;
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}
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static Bool RADEONPreInitVRAM(RHDPtr info)
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{
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u32_t accessible, bar_size;
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|
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if ((!IS_AVIVO_VARIANT) && info->IsIGP)
|
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{
|
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u32_t tom = INREG(RADEON_NB_TOM);
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|
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info->videoRam = (((tom >> 16) -
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(tom & 0xffff) + 1) << 6);
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|
|
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OUTREG(RADEON_CONFIG_MEMSIZE, info->videoRam * 1024);
|
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}
|
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else
|
|
{
|
|
if (info->ChipFamily >= CHIP_FAMILY_R600)
|
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info->videoRam = INREG(R600_CONFIG_MEMSIZE) / 1024;
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else
|
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{
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/* Read VRAM size from card */
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info->videoRam = INREG(RADEON_CONFIG_MEMSIZE) / 1024;
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|
|
/* Some production boards of m6 will return 0 if it's 8 MB */
|
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if (info->videoRam == 0)
|
|
{
|
|
info->videoRam = 8192;
|
|
OUTREG(RADEON_CONFIG_MEMSIZE, 0x800000);
|
|
}
|
|
}
|
|
}
|
|
|
|
RADEONGetVRamType(info);
|
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|
|
/* Get accessible memory */
|
|
accessible = RADEONGetAccessibleVRAM(info);
|
|
|
|
/* Crop it to the size of the PCI BAR */
|
|
// bar_size = PCI_REGION_SIZE(info->PciInfo, 0) / 1024;
|
|
|
|
bar_size = 1 << (info->memsize[RHD_FB_BAR] - 10);
|
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|
|
if (bar_size == 0)
|
|
bar_size = 0x20000;
|
|
if (accessible > bar_size)
|
|
accessible = bar_size;
|
|
|
|
dbgprintf("Detected total video RAM=%dK width=%dbit,"
|
|
"accessible=%uK (PCI BAR=%uK)\n",
|
|
info->videoRam, info->RamWidth,
|
|
(unsigned)accessible, (unsigned)bar_size);
|
|
|
|
if (info->videoRam > accessible)
|
|
info->videoRam = accessible;
|
|
|
|
if (!IS_AVIVO_VARIANT)
|
|
info->MemCntl = INREG(RADEON_SDRAM_MODE_REG);
|
|
info->BusCntl = INREG(RADEON_BUS_CNTL);
|
|
|
|
info->videoRam &= ~1023;
|
|
info->FbMapSize = info->videoRam * 1024;
|
|
|
|
/* if the card is PCI Express reserve the last 32k for the gart table */
|
|
|
|
// if (info->cardType == CARD_PCIE )
|
|
/* work out the size of pcie aperture */
|
|
// info->FbSecureSize = RADEONDRIGetPciAperTableSize(info);
|
|
// else
|
|
// info->FbSecureSize = 0;
|
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|
|
return TRUE;
|
|
}
|
|
|
|
/*
|
|
|
|
#define RADEON_NB_TOM 0x15c
|
|
|
|
static size_t rhdGetVideoRamSize(RHDPtr rhdPtr)
|
|
{
|
|
size_t RamSize, BARSize;
|
|
|
|
if (rhdPtr->ChipFamily == CHIP_FAMILY_RS690)
|
|
RamSize = (_RHDRegRead(rhdPtr, R5XX_CONFIG_MEMSIZE))>>10;
|
|
else
|
|
if (rhdPtr->IsIGP)
|
|
{
|
|
u32_t tom = _RHDRegRead(rhdPtr, RADEON_NB_TOM);
|
|
RamSize = (((tom >> 16) - (tom & 0xffff) + 1) << 6);
|
|
_RHDRegWrite(rhdPtr,R5XX_CONFIG_MEMSIZE, RamSize<<10);
|
|
}
|
|
else
|
|
{
|
|
if (rhdPtr->ChipFamily < CHIP_FAMILY_R600)
|
|
{
|
|
RamSize = (_RHDRegRead(rhdPtr, R5XX_CONFIG_MEMSIZE)) >> 10;
|
|
if(RamSize==0) RamSize=8192;
|
|
}
|
|
else
|
|
RamSize = (_RHDRegRead(rhdPtr, R6XX_CONFIG_MEMSIZE)) >> 10;
|
|
};
|
|
|
|
BARSize = 1 << (rhdPtr->memsize[RHD_FB_BAR] - 10);
|
|
if(BARSize==0)
|
|
BARSize = 0x20000;
|
|
|
|
if (RamSize > BARSize) {
|
|
DBG(dbgprintf("The detected amount of videoram"
|
|
" exceeds the PCI BAR aperture.\n"));
|
|
DBG(dbgprintf("Using only %dkB of the total "
|
|
"%dkB.\n", (int) BARSize, (int) RamSize));
|
|
return BARSize;
|
|
}
|
|
else return RamSize;
|
|
}
|
|
*/
|
|
|
|
#if 0
|
|
static Bool
|
|
rhdMapFB(RHDPtr rhdPtr)
|
|
{
|
|
rhdPtr->FbMapSize = 1 << rhdPtr->memsize[RHD_FB_BAR];
|
|
rhdPtr->PhisBase = rhdPtr->memBase[RHD_FB_BAR];
|
|
|
|
// rhdPtr->FbBase = MapIoMem(rhdPtr->PhisBase, rhdPtr->FbMapSize,PG_SW+PG_NOCACHE);
|
|
|
|
// if (!rhdPtr->FbBase)
|
|
// return FALSE;
|
|
|
|
/* These devices have an internal address reference, which some other
|
|
* address registers in there also use. This can be different from the
|
|
* address in the BAR */
|
|
if (rhdPtr->ChipFamily < CHIP_FAMILY_R600)
|
|
rhdPtr->FbIntAddress = _RHDRegRead(rhdPtr, HDP_FB_LOCATION)<< 16;
|
|
else
|
|
rhdPtr->FbIntAddress = _RHDRegRead(rhdPtr, R6XX_CONFIG_FB_BASE);
|
|
|
|
// rhdPtr->FbIntAddress = _RHDRegRead(rhdPtr, 0x6110);
|
|
// dbgprintf("rhdPtr->FbIntAddress %x\n",rhdPtr->FbIntAddress);
|
|
|
|
if (rhdPtr->FbIntAddress != rhdPtr->PhisBase)
|
|
dbgprintf("PCI FB Address (BAR) is at "
|
|
"0x%08X while card Internal Address is 0x%08X\n",
|
|
(unsigned int) rhdPtr->PhisBase,rhdPtr->FbIntAddress);
|
|
// dbgprintf("Mapped FB at %p (size 0x%08X)\n",rhdPtr->FbBase, rhdPtr->FbMapSize);
|
|
return TRUE;
|
|
}
|
|
#endif
|
|
|
|
static Bool RADEONPreInitChipType(RHDPtr rhdPtr)
|
|
{
|
|
u32_t cmd_stat;
|
|
|
|
rhdPtr->ChipErrata = 0;
|
|
|
|
if ( (rhdPtr->ChipFamily == CHIP_FAMILY_R300) &&
|
|
((_RHDRegRead(rhdPtr,RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK)
|
|
== RADEON_CFG_ATI_REV_A11))
|
|
rhdPtr->ChipErrata |= CHIP_ERRATA_R300_CG;
|
|
|
|
if ( (rhdPtr->ChipFamily == CHIP_FAMILY_RV200) ||
|
|
(rhdPtr->ChipFamily == CHIP_FAMILY_RS200) )
|
|
rhdPtr->ChipErrata |= CHIP_ERRATA_PLL_DUMMYREADS;
|
|
|
|
if ( (rhdPtr->ChipFamily == CHIP_FAMILY_RV100) ||
|
|
(rhdPtr->ChipFamily == CHIP_FAMILY_RS100) ||
|
|
(rhdPtr->ChipFamily == CHIP_FAMILY_RS200) )
|
|
rhdPtr->ChipErrata |= CHIP_ERRATA_PLL_DELAY;
|
|
|
|
rhdPtr->cardType = CARD_PCI;
|
|
|
|
|
|
cmd_stat = pciReadLong(rhdPtr->PciTag, PCI_CMD_STAT_REG);
|
|
|
|
if (cmd_stat & RADEON_CAP_LIST)
|
|
{
|
|
u32_t cap_ptr, cap_id;
|
|
|
|
cap_ptr = pciReadLong(rhdPtr->PciTag, RADEON_CAPABILITIES_PTR_PCI_CONFIG);
|
|
cap_ptr &= RADEON_CAP_PTR_MASK;
|
|
|
|
while(cap_ptr != RADEON_CAP_ID_NULL)
|
|
{
|
|
cap_id = pciReadLong(rhdPtr->PciTag, cap_ptr);
|
|
if ((cap_id & 0xff)== RADEON_CAP_ID_AGP) {
|
|
rhdPtr->cardType = CARD_AGP;
|
|
break;
|
|
}
|
|
if ((cap_id & 0xff)== RADEON_CAP_ID_EXP) {
|
|
rhdPtr->cardType = CARD_PCIE;
|
|
break;
|
|
}
|
|
cap_ptr = (cap_id >> 8) & RADEON_CAP_PTR_MASK;
|
|
}
|
|
}
|
|
|
|
dbgprintf("%s card detected\n",(rhdPtr->cardType==CARD_PCI) ? "PCI" :
|
|
(rhdPtr->cardType==CARD_PCIE) ? "PCIE" : "AGP");
|
|
|
|
/* treat PCIE IGP cards as PCI */
|
|
if (rhdPtr->cardType == CARD_PCIE && rhdPtr->IsIGP)
|
|
rhdPtr->cardType = CARD_PCI;
|
|
|
|
if ( (rhdPtr->ChipFamily == CHIP_FAMILY_RS100) ||
|
|
(rhdPtr->ChipFamily == CHIP_FAMILY_RS200) ||
|
|
(rhdPtr->ChipFamily == CHIP_FAMILY_RS300) ||
|
|
(rhdPtr->ChipFamily == CHIP_FAMILY_RS400) ||
|
|
(rhdPtr->ChipFamily == CHIP_FAMILY_RS480) ||
|
|
(rhdPtr->ChipFamily == CHIP_FAMILY_RS600) ||
|
|
(rhdPtr->ChipFamily == CHIP_FAMILY_RS690) ||
|
|
(rhdPtr->ChipFamily == CHIP_FAMILY_RS740))
|
|
rhdPtr->has_tcl = FALSE;
|
|
else {
|
|
rhdPtr->has_tcl = TRUE;
|
|
}
|
|
|
|
rhdPtr->LinearAddr = rhdPtr->memBase[RHD_FB_BAR];
|
|
|
|
return TRUE;
|
|
}
|
|
|
|
Bool RHDPreInit()
|
|
{
|
|
/* We need access to IO space already */
|
|
if ( !rhdMapMMIO(&rhd) ) {
|
|
dbgprintf("Failed to map MMIO.\n");
|
|
return FALSE;
|
|
};
|
|
|
|
|
|
if( !RADEONPreInitChipType(&rhd))
|
|
return FALSE;
|
|
|
|
if (!RADEONPreInitVRAM(&rhd))
|
|
return FALSE;
|
|
|
|
RADEONInitMemoryMap(&rhd);
|
|
|
|
if (!rhd.videoRam)
|
|
{
|
|
dbgprintf("No Video RAM detected.\n");
|
|
goto error1;
|
|
}
|
|
dbgprintf("VideoRAM: %d kByte\n",rhd.videoRam);
|
|
|
|
rhd.FbFreeStart = 0;
|
|
rhd.FbFreeSize = rhd.videoRam << 10;
|
|
|
|
// if( !rhdMapFB(&rhd))
|
|
// return FALSE;
|
|
|
|
// rhd.FbScanoutStart = 0;
|
|
// rhd.FbScanoutSize = 8*1024*1024;
|
|
|
|
rhd.FbFreeStart = 10*1024*1024;
|
|
rhd.FbFreeSize = rhd.FbMapSize - rhd.FbFreeStart;
|
|
|
|
rhdInitHeap(&rhd);
|
|
return TRUE;
|
|
|
|
error1:
|
|
return FALSE;
|
|
};
|
|
|
|
|
|
|