761 lines
25 KiB
C
761 lines
25 KiB
C
/*
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* pci.h
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*
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* PCI defines and function prototypes
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* Copyright 1994, Drew Eckhardt
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* Copyright 1997--1999 Martin Mares <mj@ucw.cz>
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*
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* For more information, please consult the following manuals (look at
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* http://www.pcisig.com/ for how to get them):
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*
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* PCI BIOS Specification
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* PCI Local Bus Specification
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* PCI to PCI Bridge Specification
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* PCI System Design Guide
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*/
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#ifndef LINUX_PCI_H
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#define LINUX_PCI_H
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#include <linux/types.h>
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#include <linux/list.h>
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#include <linux/compiler.h>
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#include <linux/errno.h>
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#include <linux/atomic.h>
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#include <linux/pci_regs.h> /* The pci register defines */
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#include <linux/ioport.h>
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#define PCI_CFG_SPACE_SIZE 256
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#define PCI_CFG_SPACE_EXP_SIZE 4096
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#define PCI_ANY_ID (~0)
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#define PCI_CLASS_NOT_DEFINED 0x0000
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#define PCI_CLASS_NOT_DEFINED_VGA 0x0001
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#define PCI_BASE_CLASS_STORAGE 0x01
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#define PCI_CLASS_STORAGE_SCSI 0x0100
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#define PCI_CLASS_STORAGE_IDE 0x0101
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#define PCI_CLASS_STORAGE_FLOPPY 0x0102
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#define PCI_CLASS_STORAGE_IPI 0x0103
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#define PCI_CLASS_STORAGE_RAID 0x0104
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#define PCI_CLASS_STORAGE_SATA 0x0106
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#define PCI_CLASS_STORAGE_SATA_AHCI 0x010601
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#define PCI_CLASS_STORAGE_SAS 0x0107
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#define PCI_CLASS_STORAGE_OTHER 0x0180
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#define PCI_BASE_CLASS_NETWORK 0x02
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#define PCI_CLASS_NETWORK_ETHERNET 0x0200
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#define PCI_CLASS_NETWORK_TOKEN_RING 0x0201
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#define PCI_CLASS_NETWORK_FDDI 0x0202
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#define PCI_CLASS_NETWORK_ATM 0x0203
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#define PCI_CLASS_NETWORK_OTHER 0x0280
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#define PCI_BASE_CLASS_DISPLAY 0x03
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#define PCI_CLASS_DISPLAY_VGA 0x0300
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#define PCI_CLASS_DISPLAY_XGA 0x0301
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#define PCI_CLASS_DISPLAY_3D 0x0302
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#define PCI_CLASS_DISPLAY_OTHER 0x0380
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#define PCI_BASE_CLASS_MULTIMEDIA 0x04
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#define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400
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#define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401
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#define PCI_CLASS_MULTIMEDIA_PHONE 0x0402
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#define PCI_CLASS_MULTIMEDIA_OTHER 0x0480
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#define PCI_BASE_CLASS_MEMORY 0x05
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#define PCI_CLASS_MEMORY_RAM 0x0500
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#define PCI_CLASS_MEMORY_FLASH 0x0501
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#define PCI_CLASS_MEMORY_OTHER 0x0580
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#define PCI_BASE_CLASS_BRIDGE 0x06
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#define PCI_CLASS_BRIDGE_HOST 0x0600
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#define PCI_CLASS_BRIDGE_ISA 0x0601
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#define PCI_CLASS_BRIDGE_EISA 0x0602
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#define PCI_CLASS_BRIDGE_MC 0x0603
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#define PCI_CLASS_BRIDGE_PCI 0x0604
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#define PCI_CLASS_BRIDGE_PCMCIA 0x0605
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#define PCI_CLASS_BRIDGE_NUBUS 0x0606
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#define PCI_CLASS_BRIDGE_CARDBUS 0x0607
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#define PCI_CLASS_BRIDGE_RACEWAY 0x0608
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#define PCI_CLASS_BRIDGE_OTHER 0x0680
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#define PCI_BASE_CLASS_COMMUNICATION 0x07
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#define PCI_CLASS_COMMUNICATION_SERIAL 0x0700
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#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701
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#define PCI_CLASS_COMMUNICATION_MULTISERIAL 0x0702
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#define PCI_CLASS_COMMUNICATION_MODEM 0x0703
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#define PCI_CLASS_COMMUNICATION_OTHER 0x0780
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#define PCI_BASE_CLASS_SYSTEM 0x08
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#define PCI_CLASS_SYSTEM_PIC 0x0800
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#define PCI_CLASS_SYSTEM_PIC_IOAPIC 0x080010
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#define PCI_CLASS_SYSTEM_PIC_IOXAPIC 0x080020
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#define PCI_CLASS_SYSTEM_DMA 0x0801
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#define PCI_CLASS_SYSTEM_TIMER 0x0802
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#define PCI_CLASS_SYSTEM_RTC 0x0803
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#define PCI_CLASS_SYSTEM_PCI_HOTPLUG 0x0804
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#define PCI_CLASS_SYSTEM_SDHCI 0x0805
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#define PCI_CLASS_SYSTEM_OTHER 0x0880
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#define PCI_BASE_CLASS_INPUT 0x09
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#define PCI_CLASS_INPUT_KEYBOARD 0x0900
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#define PCI_CLASS_INPUT_PEN 0x0901
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#define PCI_CLASS_INPUT_MOUSE 0x0902
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#define PCI_CLASS_INPUT_SCANNER 0x0903
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#define PCI_CLASS_INPUT_GAMEPORT 0x0904
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#define PCI_CLASS_INPUT_OTHER 0x0980
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#define PCI_BASE_CLASS_DOCKING 0x0a
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#define PCI_CLASS_DOCKING_GENERIC 0x0a00
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#define PCI_CLASS_DOCKING_OTHER 0x0a80
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#define PCI_BASE_CLASS_PROCESSOR 0x0b
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#define PCI_CLASS_PROCESSOR_386 0x0b00
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#define PCI_CLASS_PROCESSOR_486 0x0b01
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#define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02
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#define PCI_CLASS_PROCESSOR_ALPHA 0x0b10
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#define PCI_CLASS_PROCESSOR_POWERPC 0x0b20
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#define PCI_CLASS_PROCESSOR_MIPS 0x0b30
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#define PCI_CLASS_PROCESSOR_CO 0x0b40
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#define PCI_BASE_CLASS_SERIAL 0x0c
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#define PCI_CLASS_SERIAL_FIREWIRE 0x0c00
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#define PCI_CLASS_SERIAL_FIREWIRE_OHCI 0x0c0010
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#define PCI_CLASS_SERIAL_ACCESS 0x0c01
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#define PCI_CLASS_SERIAL_SSA 0x0c02
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#define PCI_CLASS_SERIAL_USB 0x0c03
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#define PCI_CLASS_SERIAL_USB_UHCI 0x0c0300
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#define PCI_CLASS_SERIAL_USB_OHCI 0x0c0310
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#define PCI_CLASS_SERIAL_USB_EHCI 0x0c0320
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#define PCI_CLASS_SERIAL_FIBER 0x0c04
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#define PCI_CLASS_SERIAL_SMBUS 0x0c05
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#define PCI_BASE_CLASS_WIRELESS 0x0d
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#define PCI_CLASS_WIRELESS_RF_CONTROLLER 0x0d10
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#define PCI_CLASS_WIRELESS_WHCI 0x0d1010
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#define PCI_BASE_CLASS_INTELLIGENT 0x0e
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#define PCI_CLASS_INTELLIGENT_I2O 0x0e00
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#define PCI_BASE_CLASS_SATELLITE 0x0f
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#define PCI_CLASS_SATELLITE_TV 0x0f00
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#define PCI_CLASS_SATELLITE_AUDIO 0x0f01
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#define PCI_CLASS_SATELLITE_VOICE 0x0f03
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#define PCI_CLASS_SATELLITE_DATA 0x0f04
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#define PCI_BASE_CLASS_CRYPT 0x10
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#define PCI_CLASS_CRYPT_NETWORK 0x1000
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#define PCI_CLASS_CRYPT_ENTERTAINMENT 0x1001
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#define PCI_CLASS_CRYPT_OTHER 0x1080
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#define PCI_BASE_CLASS_SIGNAL_PROCESSING 0x11
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#define PCI_CLASS_SP_DPIO 0x1100
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#define PCI_CLASS_SP_OTHER 0x1180
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#define PCI_CLASS_OTHERS 0xff
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#define PCI_MAP_IS_IO(b) ((b) & PCI_MAP_IO)
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#define PCI_MAP_IS_MEM(b) (!PCI_MAP_IS_IO(b))
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#define PCI_MAP_IS64BITMEM(b) \
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(((b) & PCI_MAP_MEMORY_TYPE_MASK) == PCI_MAP_MEMORY_TYPE_64BIT)
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#define PCIGETMEMORY(b) ((b) & PCI_MAP_MEMORY_ADDRESS_MASK)
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#define PCIGETMEMORY64HIGH(b) (*((CARD32*)&b + 1))
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#define PCIGETMEMORY64(b) \
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(PCIGETMEMORY(b) | ((CARD64)PCIGETMEMORY64HIGH(b) << 32))
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#define PCI_MAP_IO_ADDRESS_MASK 0xfffffffc
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#define PCIGETIO(b) ((b) & PCI_MAP_IO_ADDRESS_MASK)
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#define PCI_MAP_ROM_DECODE_ENABLE 0x00000001
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#define PCI_MAP_ROM_ADDRESS_MASK 0xfffff800
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#define PCIGETROM(b) ((b) & PCI_MAP_ROM_ADDRESS_MASK)
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#ifndef PCI_DOM_MASK
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# define PCI_DOM_MASK 0x0ffu
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#endif
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#define PCI_DOMBUS_MASK (((PCI_DOM_MASK) << 8) | 0x0ffu)
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#define PCI_MAKE_TAG(b,d,f) ((((b) & (PCI_DOMBUS_MASK)) << 16) | \
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(((d) & 0x00001fu) << 11) | \
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(((f) & 0x000007u) << 8))
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#define PCI_BUS_FROM_TAG(tag) (((tag) >> 16) & (PCI_DOMBUS_MASK))
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#define PCI_DEV_FROM_TAG(tag) (((tag) & 0x0000f800u) >> 11)
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#define PCI_FUNC_FROM_TAG(tag) (((tag) & 0x00000700u) >> 8)
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#define PCI_DFN_FROM_TAG(tag) (((tag) & 0x0000ff00u) >> 8)
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/*
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* The PCI interface treats multi-function devices as independent
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* devices. The slot/function address of each device is encoded
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* in a single byte as follows:
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*
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* 7:3 = slot
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* 2:0 = function
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*/
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#define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
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#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
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#define PCI_FUNC(devfn) ((devfn) & 0x07)
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typedef unsigned int PCITAG;
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extern inline PCITAG
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pciTag(int busnum, int devnum, int funcnum)
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{
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return(PCI_MAKE_TAG(busnum,devnum,funcnum));
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}
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/* pci_slot represents a physical slot */
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struct pci_slot {
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struct pci_bus *bus; /* The bus this slot is on */
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struct list_head list; /* node in list of slots on this bus */
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struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
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unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
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};
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/* File state for mmap()s on /proc/bus/pci/X/Y */
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enum pci_mmap_state {
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pci_mmap_io,
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pci_mmap_mem
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};
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/* This defines the direction arg to the DMA mapping routines. */
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#define PCI_DMA_BIDIRECTIONAL 0
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#define PCI_DMA_TODEVICE 1
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#define PCI_DMA_FROMDEVICE 2
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#define PCI_DMA_NONE 3
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/*
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* For PCI devices, the region numbers are assigned this way:
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*/
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enum {
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/* #0-5: standard PCI resources */
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PCI_STD_RESOURCES,
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PCI_STD_RESOURCE_END = 5,
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/* #6: expansion ROM resource */
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PCI_ROM_RESOURCE,
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/* device specific resources */
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#ifdef CONFIG_PCI_IOV
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PCI_IOV_RESOURCES,
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PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
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#endif
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/* resources assigned to buses behind the bridge */
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#define PCI_BRIDGE_RESOURCE_NUM 4
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PCI_BRIDGE_RESOURCES,
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PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
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PCI_BRIDGE_RESOURCE_NUM - 1,
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/* total resources associated with a PCI device */
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PCI_NUM_RESOURCES,
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/* preserve this for compatibility */
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DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
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};
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typedef int __bitwise pci_power_t;
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#define PCI_D0 ((pci_power_t __force) 0)
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#define PCI_D1 ((pci_power_t __force) 1)
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#define PCI_D2 ((pci_power_t __force) 2)
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#define PCI_D3hot ((pci_power_t __force) 3)
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#define PCI_D3cold ((pci_power_t __force) 4)
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#define PCI_UNKNOWN ((pci_power_t __force) 5)
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#define PCI_POWER_ERROR ((pci_power_t __force) -1)
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/* Remember to update this when the list above changes! */
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extern const char *pci_power_names[];
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static inline const char *pci_power_name(pci_power_t state)
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{
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return pci_power_names[1 + (int) state];
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}
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#define PCI_PM_D2_DELAY 200
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#define PCI_PM_D3_WAIT 10
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#define PCI_PM_D3COLD_WAIT 100
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#define PCI_PM_BUS_WAIT 50
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/** The pci_channel state describes connectivity between the CPU and
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* the pci device. If some PCI bus between here and the pci device
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* has crashed or locked up, this info is reflected here.
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*/
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typedef unsigned int __bitwise pci_channel_state_t;
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enum pci_channel_state {
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/* I/O channel is in normal state */
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pci_channel_io_normal = (__force pci_channel_state_t) 1,
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/* I/O to channel is blocked */
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pci_channel_io_frozen = (__force pci_channel_state_t) 2,
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/* PCI card is dead */
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pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
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};
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typedef unsigned short __bitwise pci_bus_flags_t;
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enum pci_bus_flags {
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PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
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PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
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};
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/* These values come from the PCI Express Spec */
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enum pcie_link_width {
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PCIE_LNK_WIDTH_RESRV = 0x00,
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PCIE_LNK_X1 = 0x01,
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PCIE_LNK_X2 = 0x02,
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PCIE_LNK_X4 = 0x04,
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PCIE_LNK_X8 = 0x08,
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PCIE_LNK_X12 = 0x0C,
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PCIE_LNK_X16 = 0x10,
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PCIE_LNK_X32 = 0x20,
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PCIE_LNK_WIDTH_UNKNOWN = 0xFF,
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};
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/* Based on the PCI Hotplug Spec, but some values are made up by us */
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enum pci_bus_speed {
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PCI_SPEED_33MHz = 0x00,
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PCI_SPEED_66MHz = 0x01,
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PCI_SPEED_66MHz_PCIX = 0x02,
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PCI_SPEED_100MHz_PCIX = 0x03,
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PCI_SPEED_133MHz_PCIX = 0x04,
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PCI_SPEED_66MHz_PCIX_ECC = 0x05,
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PCI_SPEED_100MHz_PCIX_ECC = 0x06,
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PCI_SPEED_133MHz_PCIX_ECC = 0x07,
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PCI_SPEED_66MHz_PCIX_266 = 0x09,
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PCI_SPEED_100MHz_PCIX_266 = 0x0a,
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PCI_SPEED_133MHz_PCIX_266 = 0x0b,
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AGP_UNKNOWN = 0x0c,
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AGP_1X = 0x0d,
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AGP_2X = 0x0e,
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AGP_4X = 0x0f,
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AGP_8X = 0x10,
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PCI_SPEED_66MHz_PCIX_533 = 0x11,
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PCI_SPEED_100MHz_PCIX_533 = 0x12,
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PCI_SPEED_133MHz_PCIX_533 = 0x13,
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PCIE_SPEED_2_5GT = 0x14,
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PCIE_SPEED_5_0GT = 0x15,
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PCIE_SPEED_8_0GT = 0x16,
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PCI_SPEED_UNKNOWN = 0xff,
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};
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struct pci_cap_saved_data {
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u16 cap_nr;
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bool cap_extended;
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unsigned int size;
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u32 data[0];
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};
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struct pci_cap_saved_state {
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struct hlist_node next;
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struct pci_cap_saved_data cap;
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};
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struct pcie_link_state;
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struct pci_vpd;
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struct pci_sriov;
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struct pci_ats;
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/*
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* The pci_dev structure is used to describe PCI devices.
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*/
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struct pci_dev {
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struct list_head bus_list; /* node in per-bus list */
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struct pci_bus *bus; /* bus this device is on */
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struct pci_bus *subordinate; /* bus this device bridges to */
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void *sysdata; /* hook for sys-specific extension */
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// struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
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struct pci_slot *slot; /* Physical slot this device is in */
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u32 busnr;
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unsigned int devfn; /* encoded device & function index */
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unsigned short vendor;
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unsigned short device;
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unsigned short subsystem_vendor;
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unsigned short subsystem_device;
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unsigned int class; /* 3 bytes: (base,sub,prog-if) */
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u8 revision; /* PCI revision, low byte of class word */
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u8 hdr_type; /* PCI header type (`multi' flag masked out) */
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u8 pcie_cap; /* PCI-E capability offset */
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u8 pcie_mpss:3; /* PCI-E Max Payload Size Supported */
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u8 rom_base_reg; /* which config register controls the ROM */
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u8 pin; /* which interrupt pin this device uses */
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u16 pcie_flags_reg; /* cached PCI-E Capabilities Register */
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// struct pci_driver *driver; /* which driver has allocated this device */
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u64 dma_mask; /* Mask of the bits of bus address this
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device implements. Normally this is
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0xffffffff. You only need to change
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this if your device has broken DMA
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or supports 64-bit transfers. */
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// struct device_dma_parameters dma_parms;
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pci_power_t current_state; /* Current operating state. In ACPI-speak,
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this is D0-D3, D0 being fully functional,
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and D3 being off. */
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u8 pm_cap; /* PM capability offset */
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unsigned int pme_support:5; /* Bitmask of states from which PME#
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can be generated */
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unsigned int pme_interrupt:1;
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unsigned int pme_poll:1; /* Poll device's PME status bit */
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unsigned int d1_support:1; /* Low power state D1 is supported */
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unsigned int d2_support:1; /* Low power state D2 is supported */
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unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
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unsigned int no_d3cold:1; /* D3cold is forbidden */
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unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
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unsigned int mmio_always_on:1; /* disallow turning off io/mem
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decoding during bar sizing */
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unsigned int wakeup_prepared:1;
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unsigned int runtime_d3cold:1; /* whether go through runtime
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D3cold, not set for devices
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powered on/off by the
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corresponding bridge */
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unsigned int d3_delay; /* D3->D0 transition time in ms */
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unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
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#ifdef CONFIG_PCIEASPM
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struct pcie_link_state *link_state; /* ASPM link state. */
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#endif
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pci_channel_state_t error_state; /* current connectivity state */
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struct device dev; /* Generic device interface */
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int cfg_size; /* Size of configuration space */
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/*
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* Instead of touching interrupt line and base address registers
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* directly, use the values stored here. They might be different!
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*/
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unsigned int irq;
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struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
|
|
|
|
/* These fields are used by common fixups */
|
|
unsigned int transparent:1; /* Transparent PCI bridge */
|
|
unsigned int multifunction:1;/* Part of multi-function device */
|
|
/* keep track of device state */
|
|
unsigned int is_added:1;
|
|
unsigned int is_busmaster:1; /* device is busmaster */
|
|
unsigned int no_msi:1; /* device may not use msi */
|
|
unsigned int block_cfg_access:1; /* config space access is blocked */
|
|
unsigned int broken_parity_status:1; /* Device generates false positive parity */
|
|
unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
|
|
unsigned int msi_enabled:1;
|
|
unsigned int msix_enabled:1;
|
|
unsigned int ari_enabled:1; /* ARI forwarding */
|
|
unsigned int is_managed:1;
|
|
unsigned int is_pcie:1; /* Obsolete. Will be removed.
|
|
Use pci_is_pcie() instead */
|
|
unsigned int needs_freset:1; /* Dev requires fundamental reset */
|
|
unsigned int state_saved:1;
|
|
unsigned int is_physfn:1;
|
|
unsigned int is_virtfn:1;
|
|
unsigned int reset_fn:1;
|
|
unsigned int is_hotplug_bridge:1;
|
|
unsigned int __aer_firmware_first_valid:1;
|
|
unsigned int __aer_firmware_first:1;
|
|
unsigned int broken_intx_masking:1;
|
|
unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */
|
|
// pci_dev_flags_t dev_flags;
|
|
atomic_t enable_cnt; /* pci_enable_device has been called */
|
|
|
|
|
|
|
|
};
|
|
|
|
#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
|
|
#define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
|
|
#define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
|
|
#define pci_resource_len(dev,bar) \
|
|
((pci_resource_start((dev), (bar)) == 0 && \
|
|
pci_resource_end((dev), (bar)) == \
|
|
pci_resource_start((dev), (bar))) ? 0 : \
|
|
\
|
|
(pci_resource_end((dev), (bar)) - \
|
|
pci_resource_start((dev), (bar)) + 1))
|
|
|
|
#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
|
|
|
|
struct pci_bus {
|
|
struct list_head node; /* node in list of buses */
|
|
struct pci_bus *parent; /* parent bus this bridge is on */
|
|
struct list_head children; /* list of child buses */
|
|
struct list_head devices; /* list of devices on this bus */
|
|
struct pci_dev *self; /* bridge device as seen by parent */
|
|
struct list_head slots; /* list of slots on this bus */
|
|
struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
|
|
struct list_head resources; /* address space routed to this bus */
|
|
struct resource busn_res; /* bus numbers routed to this bus */
|
|
|
|
struct pci_ops *ops; /* configuration access functions */
|
|
void *sysdata; /* hook for sys-specific extension */
|
|
struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
|
|
|
|
unsigned char number; /* bus number */
|
|
unsigned char primary; /* number of primary bridge */
|
|
unsigned char max_bus_speed; /* enum pci_bus_speed */
|
|
unsigned char cur_bus_speed; /* enum pci_bus_speed */
|
|
|
|
char name[48];
|
|
|
|
unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
|
|
pci_bus_flags_t bus_flags; /* inherited by child buses */
|
|
struct device *bridge;
|
|
struct device dev;
|
|
struct bin_attribute *legacy_io; /* legacy I/O for this bus */
|
|
struct bin_attribute *legacy_mem; /* legacy mem */
|
|
unsigned int is_added:1;
|
|
};
|
|
|
|
|
|
#define pci_bus_b(n) list_entry(n, struct pci_bus, node)
|
|
#define to_pci_bus(n) container_of(n, struct pci_bus, dev)
|
|
#define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
|
|
#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
|
|
#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
|
|
|
|
|
|
/* Low-level architecture-dependent routines */
|
|
|
|
struct pci_sysdata {
|
|
int domain; /* PCI domain */
|
|
int node; /* NUMA node */
|
|
};
|
|
|
|
|
|
#define pci_bus_b(n) list_entry(n, struct pci_bus, node)
|
|
#define to_pci_bus(n) container_of(n, struct pci_bus, dev)
|
|
|
|
/*
|
|
* Returns true if the PCI bus is root (behind host-PCI bridge),
|
|
* false otherwise
|
|
*
|
|
* Some code assumes that "bus->self == NULL" means that bus is a root bus.
|
|
* This is incorrect because "virtual" buses added for SR-IOV (via
|
|
* virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
|
|
*/
|
|
static inline bool pci_is_root_bus(struct pci_bus *pbus)
|
|
{
|
|
return !(pbus->parent);
|
|
}
|
|
|
|
struct pci_bus *
|
|
pci_find_next_bus(const struct pci_bus *from);
|
|
|
|
|
|
/*
|
|
* Error values that may be returned by PCI functions.
|
|
*/
|
|
#define PCIBIOS_SUCCESSFUL 0x00
|
|
#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
|
|
#define PCIBIOS_BAD_VENDOR_ID 0x83
|
|
#define PCIBIOS_DEVICE_NOT_FOUND 0x86
|
|
#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
|
|
#define PCIBIOS_SET_FAILED 0x88
|
|
#define PCIBIOS_BUFFER_TOO_SMALL 0x89
|
|
|
|
/*
|
|
* Translate above to generic errno for passing back through non-PCI code.
|
|
*/
|
|
static inline int pcibios_err_to_errno(int err)
|
|
{
|
|
if (err <= PCIBIOS_SUCCESSFUL)
|
|
return err; /* Assume already errno */
|
|
|
|
switch (err) {
|
|
case PCIBIOS_FUNC_NOT_SUPPORTED:
|
|
return -ENOENT;
|
|
case PCIBIOS_BAD_VENDOR_ID:
|
|
return -ENOTTY;
|
|
case PCIBIOS_DEVICE_NOT_FOUND:
|
|
return -ENODEV;
|
|
case PCIBIOS_BAD_REGISTER_NUMBER:
|
|
return -EFAULT;
|
|
case PCIBIOS_SET_FAILED:
|
|
return -EIO;
|
|
case PCIBIOS_BUFFER_TOO_SMALL:
|
|
return -ENOSPC;
|
|
}
|
|
|
|
return -ERANGE;
|
|
}
|
|
|
|
/* Low-level architecture-dependent routines */
|
|
|
|
struct pci_ops {
|
|
int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
|
|
int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
|
|
};
|
|
|
|
/*
|
|
* ACPI needs to be able to access PCI config space before we've done a
|
|
* PCI bus scan and created pci_bus structures.
|
|
*/
|
|
int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
|
|
int reg, int len, u32 *val);
|
|
int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
|
|
int reg, int len, u32 val);
|
|
|
|
struct pci_bus_region {
|
|
dma_addr_t start;
|
|
dma_addr_t end;
|
|
};
|
|
|
|
enum pci_bar_type {
|
|
pci_bar_unknown, /* Standard PCI BAR probe */
|
|
pci_bar_io, /* An io port BAR */
|
|
pci_bar_mem32, /* A 32-bit memory BAR */
|
|
pci_bar_mem64, /* A 64-bit memory BAR */
|
|
};
|
|
|
|
/*
|
|
* PCI domain support. Sometimes called PCI segment (eg by ACPI),
|
|
* a PCI domain is defined to be a set of PCI busses which share
|
|
* configuration space.
|
|
*/
|
|
#ifdef CONFIG_PCI_DOMAINS
|
|
extern int pci_domains_supported;
|
|
#else
|
|
enum { pci_domains_supported = 0 };
|
|
static inline int pci_domain_nr(struct pci_bus *bus)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int pci_proc_domain(struct pci_bus *bus)
|
|
{
|
|
return 0;
|
|
}
|
|
#endif /* CONFIG_PCI_DOMAINS */
|
|
|
|
/**
|
|
* pci_pcie_cap - get the saved PCIe capability offset
|
|
* @dev: PCI device
|
|
*
|
|
* PCIe capability offset is calculated at PCI device initialization
|
|
* time and saved in the data structure. This function returns saved
|
|
* PCIe capability offset. Using this instead of pci_find_capability()
|
|
* reduces unnecessary search in the PCI configuration space. If you
|
|
* need to calculate PCIe capability offset from raw device for some
|
|
* reasons, please use pci_find_capability() instead.
|
|
*/
|
|
static inline int pci_pcie_cap(struct pci_dev *dev)
|
|
{
|
|
return dev->pcie_cap;
|
|
}
|
|
|
|
/**
|
|
* pci_is_pcie - check if the PCI device is PCI Express capable
|
|
* @dev: PCI device
|
|
*
|
|
* Returns: true if the PCI device is PCI Express capable, false otherwise.
|
|
*/
|
|
static inline bool pci_is_pcie(struct pci_dev *dev)
|
|
{
|
|
return !!pci_pcie_cap(dev);
|
|
}
|
|
|
|
/**
|
|
* pci_pcie_type - get the PCIe device/port type
|
|
* @dev: PCI device
|
|
*/
|
|
static inline int pci_pcie_type(const struct pci_dev *dev)
|
|
{
|
|
return (dev->pcie_flags_reg & PCI_EXP_FLAGS_TYPE) >> 4;
|
|
}
|
|
|
|
|
|
static inline int pci_iov_init(struct pci_dev *dev)
|
|
{
|
|
return -ENODEV;
|
|
}
|
|
static inline void pci_iov_release(struct pci_dev *dev)
|
|
|
|
{}
|
|
|
|
static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno,
|
|
enum pci_bar_type *type)
|
|
{
|
|
return 0;
|
|
}
|
|
static inline void pci_restore_iov_state(struct pci_dev *dev)
|
|
{
|
|
}
|
|
static inline int pci_iov_bus_range(struct pci_bus *bus)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int pci_enable_ats(struct pci_dev *dev, int ps)
|
|
{
|
|
return -ENODEV;
|
|
}
|
|
static inline void pci_disable_ats(struct pci_dev *dev)
|
|
{
|
|
}
|
|
static inline int pci_ats_queue_depth(struct pci_dev *dev)
|
|
{
|
|
return -ENODEV;
|
|
}
|
|
static inline int pci_ats_enabled(struct pci_dev *dev)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
int pci_setup_device(struct pci_dev *dev);
|
|
int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
|
|
struct resource *res, unsigned int reg);
|
|
int pci_resource_bar(struct pci_dev *dev, int resno,
|
|
enum pci_bar_type *type);
|
|
int pci_bus_add_child(struct pci_bus *bus);
|
|
unsigned int pci_scan_child_bus(struct pci_bus *bus);
|
|
|
|
|
|
typedef struct
|
|
{
|
|
struct list_head link;
|
|
struct pci_dev pci_dev;
|
|
}pci_dev_t;
|
|
|
|
int enum_pci_devices(void);
|
|
|
|
const struct pci_device_id*
|
|
find_pci_device(pci_dev_t* pdev, const struct pci_device_id *idlist);
|
|
|
|
#define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1))
|
|
|
|
#define pci_set_dma_mask(a, b) 0
|
|
#define pci_set_consistent_dma_mask(a, b)
|
|
|
|
struct pci_dev *pci_get_bus_and_slot(unsigned int bus, unsigned int devfn);
|
|
struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
|
|
|
|
void __iomem *pci_map_rom(struct pci_dev *pdev, size_t *size);
|
|
|
|
#define pci_name(x) "radeon"
|
|
|
|
static inline dma_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
|
|
{
|
|
return pdev->resource[bar].start;
|
|
}
|
|
|
|
#endif //__PCI__H__
|
|
|
|
|