814 lines
19 KiB
PHP
814 lines
19 KiB
PHP
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; ;;
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;; Copyright (C) KolibriOS team 2004-2011. All rights reserved. ;;
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;; Distributed under terms of the GNU General Public License ;;
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;; ;;
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;; R6040 driver for KolibriOS ;;
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;; ;;
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;; based on R6040.c from linux ;;
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;; ;;
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;; Written by Asper (asper.85@mail.ru) ;;
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;; and hidnplayr (hidnplayr@gmail.com) ;;
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;; ;;
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;; GNU GENERAL PUBLIC LICENSE ;;
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;; Version 2, June 1991 ;;
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;; ;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;********************************************************************
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; Interface
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; r6040_reset
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; r6040_probe
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; r6040_poll
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; r6040_transmit
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;
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; These functions are referenced in ethernet.inc
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;
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;********************************************************************
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;; A few user-configurable values.
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TX_RING_SIZE equ 4
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RX_RING_SIZE equ 4
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; ethernet address length
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ETH_ALEN equ 6
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ETH_HLEN equ (2 * ETH_ALEN + 2)
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ETH_ZLEN equ 60 ; 60 + 4bytes auto payload for
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; mininmum 64bytes frame length
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; system timer frequency
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HZ equ 1000
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; max time out delay time
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W_MAX_TIMEOUT equ 0x0FFF
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;; Size of the in-memory receive ring.
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RX_BUF_LEN_IDX equ 3 ;; 0==8K, 1==16K, 2==32K, 3==64K
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RX_BUF_LEN equ (8192 << RX_BUF_LEN_IDX)
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;-; Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4).
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;-TX_BUF_SIZE equ 1536
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;-RX_BUF_SIZE equ 1536
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;; PCI Tuning Parameters
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; Threshold is bytes transferred to chip before transmission starts.
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TX_FIFO_THRESH equ 256 ;; In bytes, rounded down to 32 byte units.
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;; The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024.
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RX_FIFO_THRESH equ 4 ;; Rx buffer level before first PCI xfer.
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RX_DMA_BURST equ 4 ;; Maximum PCI burst, '4' is 256 bytes
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TX_DMA_BURST equ 4
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;; Operational parameters that usually are not changed.
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PHY1_ADDR equ 1 ;For MAC1
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PHY2_ADDR equ 3 ;For MAC2
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PHY_MODE equ 0x3100 ;PHY CHIP Register 0
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PHY_CAP equ 0x01E1 ;PHY CHIP Register 4
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;; Time in jiffies before concluding the transmitter is hung.
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TX_TIMEOUT equ ((6000*HZ)/1000)
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R6040_IO_SIZE equ 256 ; RDC MAC I/O Size
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MAX_MAC equ 2 ; MAX RDC MAC
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;**************************************************************************
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; RDC R6040 Register Definitions
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;**************************************************************************
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MCR0 equ 0x00 ;Control register 0
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MCR1 equ 0x01 ;Control register 1
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MAC_RST equ 0x0001 ;Reset the MAC
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MBCR equ 0x08 ;Bus control
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MT_ICR equ 0x0C ;TX interrupt control
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MR_ICR equ 0x10 ;RX interrupt control
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MTPR equ 0x14 ;TX poll command register
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MR_BSR equ 0x18 ;RX buffer size
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MR_DCR equ 0x1A ;RX descriptor control
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MLSR equ 0x1C ;Last status
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MMDIO equ 0x20 ;MDIO control register
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MDIO_WRITE equ 0x4000 ;MDIO write
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MDIO_READ equ 0x2000 ;MDIO read
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MMRD equ 0x24 ;MDIO read data register
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MMWD equ 0x28 ;MDIO write data register
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MTD_SA0 equ 0x2C ;TX descriptor start address 0
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MTD_SA1 equ 0x30 ;TX descriptor start address 1
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MRD_SA0 equ 0x34 ;RX descriptor start address 0
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MRD_SA1 equ 0x38 ;RX descriptor start address 1
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MISR equ 0x3C ;Status register
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MIER equ 0x40 ;INT enable register
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MSK_INT equ 0x0000 ;Mask off interrupts
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RX_FINISH equ 0x0001 ;RX finished
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RX_NO_DESC equ 0x0002 ;No RX descriptor available
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RX_FIFO_FULL equ 0x0004 ;RX FIFO full
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RX_EARLY equ 0x0008 ;RX early
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TX_FINISH equ 0x0010 ;TX finished
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TX_EARLY equ 0x0080 ;TX early
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EVENT_OVRFL equ 0x0100 ;Event counter overflow
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LINK_CHANGED equ 0x0200 ;PHY link changed
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ME_CISR equ 0x44 ;Event counter INT status
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ME_CIER equ 0x48 ;Event counter INT enable
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MR_CNT equ 0x50 ;Successfully received packet counter
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ME_CNT0 equ 0x52 ;Event counter 0
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ME_CNT1 equ 0x54 ;Event counter 1
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ME_CNT2 equ 0x56 ;Event counter 2
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ME_CNT3 equ 0x58 ;Event counter 3
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MT_CNT equ 0x5A ;Successfully transmit packet counter
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ME_CNT4 equ 0x5C ;Event counter 4
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MP_CNT equ 0x5E ;Pause frame counter register
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MAR0 equ 0x60 ;Hash table 0
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MAR1 equ 0x62 ;Hash table 1
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MAR2 equ 0x64 ;Hash table 2
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MAR3 equ 0x66 ;Hash table 3
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MID_0L equ 0x68 ;Multicast address MID0 Low
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MID_0M equ 0x6A ;Multicast address MID0 Medium
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MID_0H equ 0x6C ;Multicast address MID0 High
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MID_1L equ 0x70 ;MID1 Low
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MID_1M equ 0x72 ;MID1 Medium
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MID_1H equ 0x74 ;MID1 High
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MID_2L equ 0x78 ;MID2 Low
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MID_2M equ 0x7A ;MID2 Medium
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MID_2H equ 0x7C ;MID2 High
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MID_3L equ 0x80 ;MID3 Low
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MID_3M equ 0x82 ;MID3 Medium
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MID_3H equ 0x84 ;MID3 High
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PHY_CC equ 0x88 ;PHY status change configuration register
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PHY_ST equ 0x8A ;PHY status register
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MAC_SM equ 0xAC ;MAC status machine
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MAC_ID equ 0xBE ;Identifier register
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MAX_BUF_SIZE equ 0x600 ;1536
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MBCR_DEFAULT equ 0x012A ;MAC Bus Control Register
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MCAST_MAX equ 3 ;Max number multicast addresses to filter
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;Descriptor status
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DSC_OWNER_MAC equ 0x8000 ;MAC is the owner of this descriptor
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DSC_RX_OK equ 0x4000 ;RX was successfull
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DSC_RX_ERR equ 0x0800 ;RX PHY error
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DSC_RX_ERR_DRI equ 0x0400 ;RX dribble packet
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DSC_RX_ERR_BUF equ 0x0200 ;RX length exceeds buffer size
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DSC_RX_ERR_LONG equ 0x0100 ;RX length > maximum packet length
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DSC_RX_ERR_RUNT equ 0x0080 ;RX packet length < 64 byte
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DSC_RX_ERR_CRC equ 0x0040 ;RX CRC error
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DSC_RX_BCAST equ 0x0020 ;RX broadcast (no error)
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DSC_RX_MCAST equ 0x0010 ;RX multicast (no error)
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DSC_RX_MCH_HIT equ 0x0008 ;RX multicast hit in hash table (no error)
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DSC_RX_MIDH_HIT equ 0x0004 ;RX MID table hit (no error)
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DSC_RX_IDX_MID_MASK equ 3 ;RX mask for the index of matched MIDx
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;PHY settings
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ICPLUS_PHY_ID equ 0x0243
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RX_INTS equ RX_FIFO_FULL or RX_NO_DESC or RX_FINISH
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TX_INTS equ TX_FINISH
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INT_MASK equ RX_INTS or TX_INTS
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r6040_txb equ (eth_data_start)
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r6040_rxb equ ((r6040_txb+(MAX_BUF_SIZE*TX_RING_SIZE)+32) and 0xfffffff0)
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r6040_tx_ring equ ((r6040_rxb+(MAX_BUF_SIZE*RX_RING_SIZE)+32) and 0xfffffff0)
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r6040_rx_ring equ ((r6040_tx_ring+(r6040_x_head.sizeof*TX_RING_SIZE)+32) and 0xfffffff0)
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virtual at ((r6040_rx_ring+(r6040_x_head.sizeof*RX_RING_SIZE)+32) and 0xfffffff0)
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r6040_private:
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.rx_ring dd ?
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.tx_ring dd ?
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.cur_rx dw ?
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.cur_tx dw ?
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.phy_addr dw ?
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.phy_mode dw ?
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.mcr0 dw ?
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.mcr1 dw ?
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.switch_sig dw ?
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end virtual
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virtual at 0
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r6040_x_head:
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.status dw ? ;0-1
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.len dw ? ;2-3
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.buf dd ? ;4-7
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.ndesc dd ? ;8-B
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.rev1 dd ? ;C-F
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.vbufp dd ? ;10-13
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.vndescp dd ? ;14-17
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.skb_ptr dd ? ;18-1B
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.rev2 dd ? ;1C-1F
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.sizeof:
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end virtual
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; Read a word data from PHY Chip
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proc r6040_phy_read stdcall, phy_addr:dword, reg:dword
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push ecx edx
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mov eax, [phy_addr]
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shl eax, 8
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add eax, [reg]
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add eax, MDIO_READ
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mov edx, [io_addr]
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add edx, MMDIO
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out dx, ax
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;Wait for the read bit to be cleared.
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mov ecx, 2048 ;limit
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xor eax, eax
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.read:
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in ax, dx
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test ax, MDIO_READ
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jz @f
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dec ecx
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test ecx, ecx
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jnz .read
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@@:
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mov edx, [io_addr]
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add edx, MMRD
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in ax, dx
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and eax, 0xFFFF
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pop edx ecx
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ret
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endp
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; Write a word data to PHY Chip
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proc r6040_phy_write stdcall, phy_addr:dword, reg:dword, val:dword
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push eax ecx edx
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mov eax, [val]
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mov edx, [io_addr]
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add edx, MMWD
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out dx, ax
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;Write the command to the MDIO bus
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mov eax, [phy_addr]
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shl eax, 8
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add eax, [reg]
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add eax, MDIO_WRITE
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mov edx, [io_addr]
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add edx, MMDIO
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out dx, ax
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;Wait for the write bit to be cleared.
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mov ecx, 2048 ;limit
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xor eax, eax
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.write:
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in ax, dx
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test ax, MDIO_WRITE
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jz @f
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dec ecx
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test ecx, ecx
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jnz .write
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@@:
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pop edx ecx eax
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ret
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endp
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macro r6040_mdio_write reg, val {
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stdcall r6040_phy_read, [io_addr], [r6040_private.phy_addr], reg
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}
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macro r6040_mdio_write reg, val {
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stdcall r6040_phy_write, [io_addr], [r6040_private.phy_addr], reg, val
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}
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proc r6040_init_ring_desc stdcall, desc_ring:dword, size:dword
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push eax ecx esi
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mov ecx, [size]
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test ecx, ecx
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jz .out
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mov esi, [desc_ring]
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mov eax, esi
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.next_desc:
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add eax, r6040_x_head.sizeof - OS_BASE
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mov [esi+r6040_x_head.ndesc], eax
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add eax, OS_BASE
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mov [esi+r6040_x_head.vndescp], eax
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mov esi, eax
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dec ecx
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jnz .next_desc
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sub esi, r6040_x_head.sizeof
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mov eax, [desc_ring]
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mov [esi+r6040_x_head.vndescp], eax
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sub eax, OS_BASE
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mov [esi+r6040_x_head.ndesc], eax
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.out:
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pop esi ecx eax
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ret
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endp
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r6040_init_rxbufs:
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stdcall r6040_init_ring_desc, r6040_rx_ring, RX_RING_SIZE
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; Allocate skbs for the rx descriptors
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mov esi, r6040_rx_ring
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mov ebx, r6040_rxb
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mov ecx, RX_RING_SIZE
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mov eax, r6040_rx_ring
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.next_desc:
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mov [esi+r6040_x_head.skb_ptr], ebx
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mov [esi+r6040_x_head.buf], ebx
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sub [esi+r6040_x_head.buf], OS_BASE
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mov [esi+r6040_x_head.status], DSC_OWNER_MAC
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mov eax, [esi+r6040_x_head.vndescp]
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mov esi, eax
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add ebx, MAX_BUF_SIZE
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dec ecx
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jnz .next_desc
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xor eax, eax
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.out:
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ret
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r6040_probe:
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DEBUGF 1, "Probing r6040\n"
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call adjust_pci_device
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; If PHY status change register is still set to zero
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; it means the bootloader didn't initialize it
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mov edx, [io_addr]
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add edx, PHY_CC
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in ax, dx
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test ax, ax
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jnz @f
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mov eax, 0x9F07
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out dx, ax
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@@:
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; Set MAC address
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mov ecx, 3
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mov edi, node_addr
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mov edx, [io_addr]
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add edx, MID_0L
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.mac:
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in ax, dx
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stosw
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add edx, 2
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dec ecx
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jnz .mac
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; Some bootloaders/BIOSes do not initialize
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; MAC address, warn about that
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and eax, 0xFF
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or eax, [node_addr]
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test eax, eax
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jnz @f
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DEBUGF 1, "K : MAC address not initialized\n" ;, generating random"
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;Asper: Add here generate function call!
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; Temporary workaround: init by constant adress
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mov dword [node_addr], 0x00006000
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mov word [node_addr+4], 0x0001
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@@:
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; Init RDC private data
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mov [r6040_private.mcr0], 0x1002
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;mov [r6040_private.phy_addr], 1 ; Asper: Only one network card is supported now.
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mov [r6040_private.switch_sig], 0
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; Check the vendor ID on the PHY, if 0xFFFF assume none attached
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stdcall r6040_phy_read, 1, 2
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cmp ax, 0xFFFF
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jne @f
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DEBUGF 1, "K : Failed to detect an attached PHY\n" ;, generating random"
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mov eax, -1
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ret
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@@:
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; Set MAC address
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call r6040_mac_address
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; Initialize and alloc RX/TX buffers
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stdcall r6040_init_ring_desc, r6040_tx_ring, TX_RING_SIZE
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call r6040_init_rxbufs ;r6040_alloc_rxbufs
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test eax, eax
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jnz .out
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; Read the PHY ID
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mov [r6040_private.phy_mode], 0x8000
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stdcall r6040_phy_read, 0, 2
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mov [r6040_private.switch_sig], ax
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cmp ax, ICPLUS_PHY_ID
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jne @f
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stdcall r6040_phy_write, 29, 31, 0x175C ; Enable registers
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jmp .phy_readen
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@@:
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; PHY Mode Check
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movzx eax, [r6040_private.phy_addr]
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stdcall r6040_phy_write, eax, 4, PHY_CAP
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stdcall r6040_phy_write, eax, 0, PHY_MODE
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; if PHY_MODE = 0x3100
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call r6040_phy_mode_chk
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mov [r6040_private.phy_mode], ax
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jmp .phy_readen
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; end if
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; if not (PHY_MODE and 0x0100)
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mov [r6040_private.phy_mode], 0
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; end if
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.phy_readen:
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; Set duplex mode
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mov ax, [r6040_private.phy_mode]
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or [r6040_private.mcr0], ax
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; improve performance (by RDC guys)
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stdcall r6040_phy_read, 30, 17
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or ax, 0x4000
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stdcall r6040_phy_write, 30, 17, eax
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stdcall r6040_phy_read, 30, 17
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xor ax, -1
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or ax, 0x2000
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xor ax, -1
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stdcall r6040_phy_write, 30, 17, eax
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stdcall r6040_phy_write, 0, 19, 0x0000
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stdcall r6040_phy_write, 0, 30, 0x01F0
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; Initialize all Mac registers
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call r6040_reset
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xor eax, eax
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.out:
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ret
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align 4
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r6040_reset:
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DEBUGF 1, "Resetting r6040\n"
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push eax ecx edx
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; Mask off Interrupt
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mov eax, MSK_INT
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mov edx, [io_addr]
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add edx, MIER
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out dx, ax
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;Reset RDC MAC
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mov eax, MAC_RST
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mov edx, [io_addr]
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add edx, MCR1
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out dx, ax
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mov ecx, 2048 ;limit
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.read:
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in ax, dx
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test ax, 0x1
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jnz @f
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dec ecx
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test ecx, ecx
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jnz .read
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@@:
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;Reset internal state machine
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mov ax, 2
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mov edx, [io_addr]
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add edx, MAC_SM
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out dx, ax
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xor ax, ax
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out dx, ax
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mov esi, 5
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call delay_ms
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;MAC Bus Control Register
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mov ax, MBCR_DEFAULT
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mov edx, [io_addr]
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add edx, MBCR
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out dx, ax
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;Buffer Size Register
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mov ax, MAX_BUF_SIZE
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mov edx, [io_addr]
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add edx, MR_BSR
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out dx, ax
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;Write TX ring start address
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mov eax, r6040_tx_ring - OS_BASE ;Asper: Maybe we can just write dword? Hidnplayr: better use word, as described in datasheet.
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mov edx, [io_addr]
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add edx, MTD_SA0
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out dx, ax
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shr eax, 16
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add edx, MTD_SA1 - MTD_SA0
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out dx, ax
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;Write RX ring start address
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mov eax, r6040_rx_ring - OS_BASE ;Asper: Maybe we can just write dword?
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mov edx, [io_addr]
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add edx, MRD_SA0
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out dx, ax
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shr eax, 16
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add edx, MRD_SA1 - MRD_SA0
|
|
out dx, ax
|
|
|
|
;Set interrupt waiting time and packet numbers
|
|
xor ax, ax
|
|
mov edx, [io_addr]
|
|
add edx, MT_ICR
|
|
out dx, ax
|
|
|
|
;Asper: ~ Disable ints ;Enable interrupts
|
|
;mov ax, MSK_INT ;INT_MASK ;Asper ~
|
|
;mov edx, [io_addr]
|
|
;add edx, MIER
|
|
;out dx, ax
|
|
|
|
;Enable TX and RX
|
|
mov ax, [r6040_private.mcr0]
|
|
or ax, 0x0002
|
|
mov edx, [io_addr]
|
|
out dx, ax
|
|
|
|
;Let TX poll the descriptors
|
|
;we may got called by r6040_tx_timeout which has left
|
|
;some unset tx buffers
|
|
xor ax, ax
|
|
inc ax
|
|
mov edx, [io_addr]
|
|
add edx, MTPR
|
|
out dx, ax
|
|
|
|
pop edx ecx eax
|
|
|
|
DEBUGF 1, "reset ok!\n"
|
|
|
|
; Indicate that we have successfully reset the card
|
|
mov eax, [pci_data]
|
|
mov [eth_status], eax
|
|
ret
|
|
|
|
|
|
|
|
proc r6040_tx_timeout
|
|
push eax edx
|
|
;...
|
|
inc [stats.tx_errors]
|
|
;Reset MAC and re-init all registers
|
|
call r6040_init_mac_regs
|
|
pop edx eax
|
|
ret
|
|
endp
|
|
|
|
proc r6040_get_stats
|
|
push eax edx
|
|
mov edx, [io_addr]
|
|
add edx, ME_CNT1
|
|
in al, dx
|
|
add [stats.rx_crc_errors], al
|
|
mov edx, [io_addr]
|
|
add edx, ME_CNT0
|
|
in al, dx
|
|
add [stats.multicast], al
|
|
pop edx eax
|
|
ret
|
|
endp
|
|
|
|
;...
|
|
|
|
proc r6040_phy_mode_chk
|
|
push ebx
|
|
;PHY Link Status Check
|
|
movzx eax, [r6040_private.phy_addr]
|
|
stdcall r6040_phy_read, eax, 1
|
|
test eax, 0x4
|
|
jnz @f
|
|
mov eax, 0x8000 ;Link Failed, full duplex
|
|
@@:
|
|
;PHY Chip Auto-Negotiation Status
|
|
movzx eax, [r6040_private.phy_addr]
|
|
stdcall r6040_phy_read, eax, 1
|
|
test eax, 0x0020
|
|
jz .force_mode
|
|
;Auto Negotuiation Mode
|
|
movzx eax, [r6040_private.phy_addr]
|
|
stdcall r6040_phy_read, eax, 5
|
|
mov ebx, eax
|
|
movzx eax, [r6040_private.phy_addr]
|
|
stdcall r6040_phy_read, eax, 4
|
|
and eax, ebx
|
|
test eax, 0x140
|
|
jz .ret_0
|
|
jmp .ret_0x8000
|
|
.force_mode:
|
|
;Force Mode
|
|
movzx eax, [r6040_private.phy_addr]
|
|
stdcall r6040_phy_read, eax, 0
|
|
test eax, 0x100
|
|
jz .ret_0
|
|
.ret_0x8000:
|
|
mov eax, 0x8000
|
|
pop ebx
|
|
ret
|
|
.ret_0:
|
|
xor eax, eax
|
|
pop ebx
|
|
ret
|
|
endp
|
|
|
|
|
|
|
|
;***************************************************************************
|
|
; Function
|
|
; r6040_rx
|
|
; Description
|
|
; polls card to see if there is a packet waiting
|
|
;
|
|
; Currently only supports one descriptor per packet, if packet is fragmented
|
|
; between multiple descriptors you will lose part of the packet
|
|
;***************************************************************************
|
|
r6040_poll:
|
|
push ebx ecx esi edi
|
|
|
|
xor eax, eax
|
|
mov [eth_rx_data_len], ax
|
|
|
|
movzx eax, [r6040_private.cur_rx]
|
|
mov ebx, eax
|
|
shl ebx, 5
|
|
|
|
mov cx, [ebx+r6040_rx_ring+r6040_x_head.status] ; Read the descriptor status
|
|
test cx, DSC_OWNER_MAC
|
|
jnz .out
|
|
|
|
test cx, DSC_RX_ERR ; Global error status set
|
|
jz .no_dsc_rx_err
|
|
;...
|
|
jmp .out
|
|
|
|
.no_dsc_rx_err:
|
|
; Packet successfully received
|
|
movzx ecx, [ebx+r6040_rx_ring+r6040_x_head.len]
|
|
and ecx, 0xFFF
|
|
sub ecx, 4 ; Do not count the CRC
|
|
mov [eth_rx_data_len], cx
|
|
mov esi, [ebx+r6040_rx_ring+r6040_x_head.skb_ptr]
|
|
|
|
push ecx
|
|
shr ecx, 2
|
|
mov edi, Ether_buffer
|
|
cld
|
|
rep movsd
|
|
pop ecx
|
|
and ecx, 3
|
|
rep movsb
|
|
|
|
or [ebx+r6040_rx_ring+r6040_x_head.status], DSC_OWNER_MAC
|
|
|
|
inc [r6040_private.cur_rx]
|
|
and [r6040_private.cur_rx], RX_RING_SIZE-1
|
|
|
|
xor eax, eax
|
|
.out:
|
|
pop edi esi ecx ebx
|
|
ret
|
|
|
|
|
|
|
|
;***************************************************************************
|
|
; Function
|
|
; r6040_transmit
|
|
; Description
|
|
; Transmits a packet of data via the ethernet card
|
|
; Pointer to 48 bit destination address in edi
|
|
; Type of packet in bx
|
|
; size of packet in ecx
|
|
; pointer to packet data in esi
|
|
;
|
|
;***************************************************************************
|
|
r6040_transmit:
|
|
cmp ecx, MAX_BUF_SIZE
|
|
jg .out ; packet is too long
|
|
|
|
push edi esi ebx ecx
|
|
|
|
movzx eax, [r6040_private.cur_tx]
|
|
shl eax, 5
|
|
|
|
; DEBUGF 1,"R6040: TX buffer status: 0x%x, eax=%u\n", [eax + r6040_tx_ring + r6040_x_head.status]:4, eax
|
|
|
|
test [r6040_tx_ring + eax + r6040_x_head.status], 0x8000 ; check if buffer is available
|
|
jz .l3
|
|
|
|
push ecx esi
|
|
mov ecx, [timer_ticks]
|
|
add ecx, 100
|
|
.l2:
|
|
test [r6040_tx_ring + eax + r6040_x_head.status], 0x8000
|
|
jz .l5
|
|
cmp ecx, [timer_ticks]
|
|
jb .l4
|
|
mov esi, 10
|
|
call delay_ms
|
|
jmp .l2
|
|
|
|
.l4:
|
|
pop esi ecx
|
|
DEBUGF 1,"R6040: Send timeout\n"
|
|
jmp .out
|
|
|
|
.l5:
|
|
pop esi ecx
|
|
.l3:
|
|
push eax
|
|
|
|
mov esi, edi
|
|
|
|
; point to the current tx buffer
|
|
movzx edi, [r6040_private.cur_tx]
|
|
imul edi, MAX_BUF_SIZE
|
|
add edi, r6040_txb
|
|
lea eax, [edi - OS_BASE] ; real buffer address in eax
|
|
|
|
; copy destination address
|
|
movsd
|
|
movsw
|
|
; copy source address
|
|
mov esi, node_addr
|
|
movsd
|
|
movsw
|
|
; copy packet type
|
|
mov [edi], bx
|
|
add edi, 2
|
|
|
|
mov esi, [esp+8+4]
|
|
mov ecx, [esp+4]
|
|
; copy the packet data
|
|
push ecx
|
|
shr ecx,2
|
|
rep movsd
|
|
pop ecx
|
|
and ecx,3
|
|
rep movsb
|
|
|
|
pop edi
|
|
|
|
mov ecx, [esp]
|
|
add ecx, ETH_HLEN
|
|
cmp cx, ETH_ZLEN
|
|
jae @f
|
|
mov cx, ETH_ZLEN
|
|
@@:
|
|
|
|
mov [r6040_tx_ring + edi + r6040_x_head.len], cx
|
|
mov [r6040_tx_ring + edi + r6040_x_head.buf], eax
|
|
mov [r6040_tx_ring + edi + r6040_x_head.status], 0x8000
|
|
|
|
; Trigger the MAC to check the TX descriptor
|
|
mov ax, 0x01
|
|
mov edx, [io_addr]
|
|
add edx, MTPR
|
|
out dx, ax
|
|
|
|
inc [r6040_private.cur_tx]
|
|
and [r6040_private.cur_tx], TX_RING_SIZE-1
|
|
xor eax, eax
|
|
|
|
pop ecx ebx esi edi
|
|
.out:
|
|
ret
|
|
|
|
|
|
|
|
r6040_mac_address:
|
|
push eax ecx edx esi edi
|
|
; MAC operation register
|
|
mov ax, 1
|
|
mov edx, [io_addr]
|
|
add edx, MCR1
|
|
out dx, ax
|
|
; Reset MAC
|
|
mov ax, 2
|
|
mov edx, [io_addr]
|
|
add edx, MAC_SM
|
|
out dx, ax
|
|
; Reset internal state machine
|
|
xor ax, ax
|
|
out dx, ax
|
|
mov esi, 5
|
|
call delay_ms
|
|
|
|
; Restore MAC Address
|
|
mov ecx, 3
|
|
mov edi, node_addr
|
|
mov edx, [io_addr]
|
|
add edx, MID_0L
|
|
.mac:
|
|
in ax, dx
|
|
stosw
|
|
add edx, 2
|
|
dec ecx
|
|
jnz .mac
|
|
|
|
pop edi esi edx ecx eax
|
|
ret
|
|
|