539 lines
17 KiB
C
539 lines
17 KiB
C
/*
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* Copyright © 2008 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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*
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*/
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#include <linux/string.h>
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#include <linux/bitops.h>
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#include <drm/drmP.h>
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#include <drm/i915_drm.h>
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#include "i915_drv.h"
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/** @file i915_gem_tiling.c
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*
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* Support for managing tiling state of buffer objects.
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*
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* The idea behind tiling is to increase cache hit rates by rearranging
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* pixel data so that a group of pixel accesses are in the same cacheline.
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* Performance improvement from doing this on the back/depth buffer are on
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* the order of 30%.
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*
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* Intel architectures make this somewhat more complicated, though, by
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* adjustments made to addressing of data when the memory is in interleaved
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* mode (matched pairs of DIMMS) to improve memory bandwidth.
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* For interleaved memory, the CPU sends every sequential 64 bytes
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* to an alternate memory channel so it can get the bandwidth from both.
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*
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* The GPU also rearranges its accesses for increased bandwidth to interleaved
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* memory, and it matches what the CPU does for non-tiled. However, when tiled
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* it does it a little differently, since one walks addresses not just in the
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* X direction but also Y. So, along with alternating channels when bit
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* 6 of the address flips, it also alternates when other bits flip -- Bits 9
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* (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines)
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* are common to both the 915 and 965-class hardware.
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*
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* The CPU also sometimes XORs in higher bits as well, to improve
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* bandwidth doing strided access like we do so frequently in graphics. This
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* is called "Channel XOR Randomization" in the MCH documentation. The result
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* is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address
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* decode.
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*
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* All of this bit 6 XORing has an effect on our memory management,
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* as we need to make sure that the 3d driver can correctly address object
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* contents.
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*
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* If we don't have interleaved memory, all tiling is safe and no swizzling is
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* required.
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*
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* When bit 17 is XORed in, we simply refuse to tile at all. Bit
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* 17 is not just a page offset, so as we page an objet out and back in,
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* individual pages in it will have different bit 17 addresses, resulting in
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* each 64 bytes being swapped with its neighbor!
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*
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* Otherwise, if interleaved, we have to tell the 3d driver what the address
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* swizzling it needs to do is, since it's writing with the CPU to the pages
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* (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the
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* pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling
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* required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order
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* to match what the GPU expects.
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*/
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#define I915_TILING_NONE 0
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#define I915_TILING_X 1
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#define I915_TILING_Y 2
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#define I915_BIT_6_SWIZZLE_NONE 0
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#define I915_BIT_6_SWIZZLE_9 1
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#define I915_BIT_6_SWIZZLE_9_10 2
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#define I915_BIT_6_SWIZZLE_9_11 3
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#define I915_BIT_6_SWIZZLE_9_10_11 4
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/* Not seen by userland */
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#define I915_BIT_6_SWIZZLE_UNKNOWN 5
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/* Seen by userland. */
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#define I915_BIT_6_SWIZZLE_9_17 6
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#define I915_BIT_6_SWIZZLE_9_10_17 7
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/**
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* Detects bit 6 swizzling of address lookup between IGD access and CPU
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* access through main memory.
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*/
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void
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i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
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uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
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if (IS_VALLEYVIEW(dev)) {
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swizzle_x = I915_BIT_6_SWIZZLE_NONE;
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swizzle_y = I915_BIT_6_SWIZZLE_NONE;
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} else if (INTEL_INFO(dev)->gen >= 6) {
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uint32_t dimm_c0, dimm_c1;
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dimm_c0 = I915_READ(MAD_DIMM_C0);
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dimm_c1 = I915_READ(MAD_DIMM_C1);
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dimm_c0 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK;
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dimm_c1 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK;
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/* Enable swizzling when the channels are populated with
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* identically sized dimms. We don't need to check the 3rd
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* channel because no cpu with gpu attached ships in that
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* configuration. Also, swizzling only makes sense for 2
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* channels anyway. */
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if (dimm_c0 == dimm_c1) {
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swizzle_x = I915_BIT_6_SWIZZLE_9_10;
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swizzle_y = I915_BIT_6_SWIZZLE_9;
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} else {
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swizzle_x = I915_BIT_6_SWIZZLE_NONE;
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swizzle_y = I915_BIT_6_SWIZZLE_NONE;
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}
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} else if (IS_GEN5(dev)) {
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/* On Ironlake whatever DRAM config, GPU always do
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* same swizzling setup.
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*/
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swizzle_x = I915_BIT_6_SWIZZLE_9_10;
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swizzle_y = I915_BIT_6_SWIZZLE_9;
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} else if (IS_GEN2(dev)) {
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/* As far as we know, the 865 doesn't have these bit 6
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* swizzling issues.
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*/
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swizzle_x = I915_BIT_6_SWIZZLE_NONE;
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swizzle_y = I915_BIT_6_SWIZZLE_NONE;
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} else if (IS_MOBILE(dev) || (IS_GEN3(dev) && !IS_G33(dev))) {
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uint32_t dcc;
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/* On 9xx chipsets, channel interleave by the CPU is
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* determined by DCC. For single-channel, neither the CPU
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* nor the GPU do swizzling. For dual channel interleaved,
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* the GPU's interleave is bit 9 and 10 for X tiled, and bit
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* 9 for Y tiled. The CPU's interleave is independent, and
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* can be based on either bit 11 (haven't seen this yet) or
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* bit 17 (common).
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*/
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dcc = I915_READ(DCC);
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switch (dcc & DCC_ADDRESSING_MODE_MASK) {
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case DCC_ADDRESSING_MODE_SINGLE_CHANNEL:
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case DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC:
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swizzle_x = I915_BIT_6_SWIZZLE_NONE;
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swizzle_y = I915_BIT_6_SWIZZLE_NONE;
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break;
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case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED:
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if (dcc & DCC_CHANNEL_XOR_DISABLE) {
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/* This is the base swizzling by the GPU for
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* tiled buffers.
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*/
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swizzle_x = I915_BIT_6_SWIZZLE_9_10;
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swizzle_y = I915_BIT_6_SWIZZLE_9;
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} else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) {
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/* Bit 11 swizzling by the CPU in addition. */
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swizzle_x = I915_BIT_6_SWIZZLE_9_10_11;
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swizzle_y = I915_BIT_6_SWIZZLE_9_11;
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} else {
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/* Bit 17 swizzling by the CPU in addition. */
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swizzle_x = I915_BIT_6_SWIZZLE_9_10_17;
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swizzle_y = I915_BIT_6_SWIZZLE_9_17;
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}
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break;
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}
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if (dcc == 0xffffffff) {
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DRM_ERROR("Couldn't read from MCHBAR. "
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"Disabling tiling.\n");
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swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
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swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
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}
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} else {
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/* The 965, G33, and newer, have a very flexible memory
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* configuration. It will enable dual-channel mode
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* (interleaving) on as much memory as it can, and the GPU
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* will additionally sometimes enable different bit 6
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* swizzling for tiled objects from the CPU.
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*
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* Here's what I found on the G965:
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* slot fill memory size swizzling
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* 0A 0B 1A 1B 1-ch 2-ch
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* 512 0 0 0 512 0 O
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* 512 0 512 0 16 1008 X
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* 512 0 0 512 16 1008 X
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* 0 512 0 512 16 1008 X
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* 1024 1024 1024 0 2048 1024 O
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*
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* We could probably detect this based on either the DRB
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* matching, which was the case for the swizzling required in
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* the table above, or from the 1-ch value being less than
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* the minimum size of a rank.
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*/
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if (I915_READ16(C0DRB3) != I915_READ16(C1DRB3)) {
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swizzle_x = I915_BIT_6_SWIZZLE_NONE;
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swizzle_y = I915_BIT_6_SWIZZLE_NONE;
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} else {
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swizzle_x = I915_BIT_6_SWIZZLE_9_10;
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swizzle_y = I915_BIT_6_SWIZZLE_9;
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}
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}
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dev_priv->mm.bit_6_swizzle_x = swizzle_x;
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dev_priv->mm.bit_6_swizzle_y = swizzle_y;
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}
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#if 0
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/* Check pitch constriants for all chips & tiling formats */
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static bool
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i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
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{
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int tile_width;
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/* Linear is always fine */
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if (tiling_mode == I915_TILING_NONE)
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return true;
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if (IS_GEN2(dev) ||
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(tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
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tile_width = 128;
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else
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tile_width = 512;
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/* check maximum stride & object size */
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if (INTEL_INFO(dev)->gen >= 4) {
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/* i965 stores the end address of the gtt mapping in the fence
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* reg, so dont bother to check the size */
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if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
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return false;
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} else {
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if (stride > 8192)
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return false;
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if (IS_GEN3(dev)) {
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if (size > I830_FENCE_MAX_SIZE_VAL << 20)
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return false;
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} else {
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if (size > I830_FENCE_MAX_SIZE_VAL << 19)
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return false;
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}
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}
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/* 965+ just needs multiples of tile width */
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if (INTEL_INFO(dev)->gen >= 4) {
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if (stride & (tile_width - 1))
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return false;
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return true;
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}
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/* Pre-965 needs power of two tile widths */
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if (stride < tile_width)
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return false;
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if (stride & (stride - 1))
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return false;
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return true;
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}
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/* Is the current GTT allocation valid for the change in tiling? */
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static bool
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i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode)
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{
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u32 size;
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if (tiling_mode == I915_TILING_NONE)
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return true;
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if (INTEL_INFO(obj->base.dev)->gen >= 4)
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return true;
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if (INTEL_INFO(obj->base.dev)->gen == 3) {
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if (obj->gtt_offset & ~I915_FENCE_START_MASK)
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return false;
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} else {
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if (obj->gtt_offset & ~I830_FENCE_START_MASK)
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return false;
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}
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/*
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* Previous chips need to be aligned to the size of the smallest
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* fence register that can contain the object.
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*/
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if (INTEL_INFO(obj->base.dev)->gen == 3)
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size = 1024*1024;
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else
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size = 512*1024;
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while (size < obj->base.size)
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size <<= 1;
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if (obj->gtt_space->size != size)
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return false;
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if (obj->gtt_offset & (size - 1))
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return false;
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return true;
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}
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/**
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* Sets the tiling mode of an object, returning the required swizzling of
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* bit 6 of addresses in the object.
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*/
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int
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i915_gem_set_tiling(struct drm_device *dev, void *data,
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struct drm_file *file)
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{
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struct drm_i915_gem_set_tiling *args = data;
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drm_i915_private_t *dev_priv = dev->dev_private;
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struct drm_i915_gem_object *obj;
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int ret = 0;
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obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
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if (&obj->base == NULL)
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return -ENOENT;
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if (!i915_tiling_ok(dev,
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args->stride, obj->base.size, args->tiling_mode)) {
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drm_gem_object_unreference_unlocked(&obj->base);
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return -EINVAL;
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}
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if (obj->pin_count) {
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drm_gem_object_unreference_unlocked(&obj->base);
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return -EBUSY;
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}
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if (args->tiling_mode == I915_TILING_NONE) {
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args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
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args->stride = 0;
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} else {
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if (args->tiling_mode == I915_TILING_X)
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args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
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else
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args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
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/* Hide bit 17 swizzling from the user. This prevents old Mesa
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* from aborting the application on sw fallbacks to bit 17,
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* and we use the pread/pwrite bit17 paths to swizzle for it.
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* If there was a user that was relying on the swizzle
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* information for drm_intel_bo_map()ed reads/writes this would
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* break it, but we don't have any of those.
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*/
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if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
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args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
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if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
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args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
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/* If we can't handle the swizzling, make it untiled. */
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if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) {
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args->tiling_mode = I915_TILING_NONE;
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args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
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args->stride = 0;
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}
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}
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mutex_lock(&dev->struct_mutex);
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if (args->tiling_mode != obj->tiling_mode ||
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args->stride != obj->stride) {
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/* We need to rebind the object if its current allocation
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* no longer meets the alignment restrictions for its new
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* tiling mode. Otherwise we can just leave it alone, but
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* need to ensure that any fence register is updated before
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* the next fenced (either through the GTT or by the BLT unit
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* on older GPUs) access.
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*
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* After updating the tiling parameters, we then flag whether
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* we need to update an associated fence register. Note this
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* has to also include the unfenced register the GPU uses
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* whilst executing a fenced command for an untiled object.
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*/
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obj->map_and_fenceable =
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obj->gtt_space == NULL ||
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(obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end &&
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i915_gem_object_fence_ok(obj, args->tiling_mode));
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/* Rebind if we need a change of alignment */
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if (!obj->map_and_fenceable) {
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u32 unfenced_alignment =
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i915_gem_get_unfenced_gtt_alignment(dev,
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obj->base.size,
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args->tiling_mode);
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if (obj->gtt_offset & (unfenced_alignment - 1))
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ret = i915_gem_object_unbind(obj);
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}
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if (ret == 0) {
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obj->fence_dirty =
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obj->fenced_gpu_access ||
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obj->fence_reg != I915_FENCE_REG_NONE;
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obj->tiling_mode = args->tiling_mode;
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obj->stride = args->stride;
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/* Force the fence to be reacquired for GTT access */
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i915_gem_release_mmap(obj);
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}
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}
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/* we have to maintain this existing ABI... */
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args->stride = obj->stride;
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args->tiling_mode = obj->tiling_mode;
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drm_gem_object_unreference(&obj->base);
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mutex_unlock(&dev->struct_mutex);
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return ret;
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}
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/**
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* Returns the current tiling mode and required bit 6 swizzling for the object.
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*/
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int
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i915_gem_get_tiling(struct drm_device *dev, void *data,
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struct drm_file *file)
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{
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struct drm_i915_gem_get_tiling *args = data;
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drm_i915_private_t *dev_priv = dev->dev_private;
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struct drm_i915_gem_object *obj;
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obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
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if (&obj->base == NULL)
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return -ENOENT;
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mutex_lock(&dev->struct_mutex);
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args->tiling_mode = obj->tiling_mode;
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switch (obj->tiling_mode) {
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case I915_TILING_X:
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args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
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break;
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case I915_TILING_Y:
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args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
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break;
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case I915_TILING_NONE:
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args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
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break;
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default:
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DRM_ERROR("unknown tiling mode\n");
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}
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|
|
/* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */
|
|
if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
|
|
args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
|
|
if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
|
|
args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
|
|
|
|
drm_gem_object_unreference(&obj->base);
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* Swap every 64 bytes of this page around, to account for it having a new
|
|
* bit 17 of its physical address and therefore being interpreted differently
|
|
* by the GPU.
|
|
*/
|
|
static void
|
|
i915_gem_swizzle_page(struct page *page)
|
|
{
|
|
char temp[64];
|
|
char *vaddr;
|
|
int i;
|
|
|
|
vaddr = kmap(page);
|
|
|
|
for (i = 0; i < PAGE_SIZE; i += 128) {
|
|
memcpy(temp, &vaddr[i], 64);
|
|
memcpy(&vaddr[i], &vaddr[i + 64], 64);
|
|
memcpy(&vaddr[i + 64], temp, 64);
|
|
}
|
|
|
|
kunmap(page);
|
|
}
|
|
|
|
void
|
|
i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj)
|
|
{
|
|
struct scatterlist *sg;
|
|
int page_count = obj->base.size >> PAGE_SHIFT;
|
|
int i;
|
|
|
|
if (obj->bit_17 == NULL)
|
|
return;
|
|
|
|
for_each_sg(obj->pages->sgl, sg, page_count, i) {
|
|
struct page *page = sg_page(sg);
|
|
char new_bit_17 = page_to_phys(page) >> 17;
|
|
if ((new_bit_17 & 0x1) !=
|
|
(test_bit(i, obj->bit_17) != 0)) {
|
|
i915_gem_swizzle_page(page);
|
|
set_page_dirty(page);
|
|
}
|
|
}
|
|
}
|
|
|
|
void
|
|
i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj)
|
|
{
|
|
struct scatterlist *sg;
|
|
int page_count = obj->base.size >> PAGE_SHIFT;
|
|
int i;
|
|
|
|
if (obj->bit_17 == NULL) {
|
|
obj->bit_17 = kmalloc(BITS_TO_LONGS(page_count) *
|
|
sizeof(long), GFP_KERNEL);
|
|
if (obj->bit_17 == NULL) {
|
|
DRM_ERROR("Failed to allocate memory for bit 17 "
|
|
"record\n");
|
|
return;
|
|
}
|
|
}
|
|
|
|
for_each_sg(obj->pages->sgl, sg, page_count, i) {
|
|
struct page *page = sg_page(sg);
|
|
if (page_to_phys(page) & (1 << 17))
|
|
__set_bit(i, obj->bit_17);
|
|
else
|
|
__clear_bit(i, obj->bit_17);
|
|
}
|
|
}
|
|
|
|
#endif
|