1127 lines
29 KiB
C
1127 lines
29 KiB
C
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#define iowrite32(v, addr) writel((v), (addr))
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#include "drmP.h"
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#include "drm.h"
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#include "i915_drm.h"
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#include "i915_drv.h"
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#include "intel_drv.h"
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mod_devicetable.h>
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#include <errno-base.h>
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#include <linux/pci.h>
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#include <syscall.h>
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#include "bitmap.h"
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extern struct drm_device *main_device;
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typedef struct
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{
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kobj_t header;
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uint32_t *data;
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uint32_t hot_x;
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uint32_t hot_y;
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struct list_head list;
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struct drm_i915_gem_object *cobj;
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}cursor_t;
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#define CURSOR_WIDTH 64
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#define CURSOR_HEIGHT 64
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struct tag_display
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{
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int x;
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int y;
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int width;
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int height;
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int bpp;
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int vrefresh;
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int pitch;
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int lfb;
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int supported_modes;
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struct drm_device *ddev;
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struct drm_connector *connector;
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struct drm_crtc *crtc;
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struct list_head cursors;
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cursor_t *cursor;
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int (*init_cursor)(cursor_t*);
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cursor_t* (__stdcall *select_cursor)(cursor_t*);
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void (*show_cursor)(int show);
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void (__stdcall *move_cursor)(cursor_t *cursor, int x, int y);
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void (__stdcall *restore_cursor)(int x, int y);
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void (*disable_mouse)(void);
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};
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static display_t *os_display;
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u32_t cmd_buffer;
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u32_t cmd_offset;
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void init_render();
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int sna_init();
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int init_cursor(cursor_t *cursor);
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static cursor_t* __stdcall select_cursor_kms(cursor_t *cursor);
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static void __stdcall move_cursor_kms(cursor_t *cursor, int x, int y);
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void __stdcall restore_cursor(int x, int y)
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{};
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void disable_mouse(void)
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{};
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static int count_connector_modes(struct drm_connector* connector)
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{
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struct drm_display_mode *mode;
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int count = 0;
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list_for_each_entry(mode, &connector->modes, head)
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{
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count++;
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};
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return count;
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};
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int init_display_kms(struct drm_device *dev)
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{
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struct drm_connector *connector;
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struct drm_connector_helper_funcs *connector_funcs;
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struct drm_encoder *encoder;
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struct drm_crtc *crtc = NULL;
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struct drm_framebuffer *fb;
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cursor_t *cursor;
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u32_t ifl;
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ENTER();
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list_for_each_entry(connector, &dev->mode_config.connector_list, head)
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{
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if( connector->status != connector_status_connected)
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continue;
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connector_funcs = connector->helper_private;
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encoder = connector_funcs->best_encoder(connector);
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if( encoder == NULL)
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{
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dbgprintf("CONNECTOR %x ID: %d no active encoders\n",
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connector, connector->base.id);
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continue;
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}
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connector->encoder = encoder;
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dbgprintf("CONNECTOR %x ID: %d status %d encoder %x\n crtc %x\n",
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connector, connector->base.id,
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connector->status, connector->encoder,
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encoder->crtc);
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crtc = encoder->crtc;
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break;
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};
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if(connector == NULL)
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{
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dbgprintf("No active connectors!\n");
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return -1;
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};
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if(crtc == NULL)
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{
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struct drm_crtc *tmp_crtc;
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int crtc_mask = 1;
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list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head)
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{
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if (encoder->possible_crtcs & crtc_mask)
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{
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crtc = tmp_crtc;
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encoder->crtc = crtc;
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break;
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};
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crtc_mask <<= 1;
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};
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};
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if(crtc == NULL)
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{
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dbgprintf("No CRTC for encoder %d\n", encoder->base.id);
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return -1;
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};
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DRM_DEBUG_KMS("[Select CRTC:%d]\n", crtc->base.id);
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os_display = GetDisplay();
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os_display->ddev = dev;
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os_display->connector = connector;
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os_display->crtc = crtc;
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os_display->supported_modes = count_connector_modes(connector);
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ifl = safe_cli();
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{
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struct intel_crtc *intel_crtc = to_intel_crtc(os_display->crtc);
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list_for_each_entry(cursor, &os_display->cursors, list)
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{
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init_cursor(cursor);
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};
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os_display->restore_cursor(0,0);
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os_display->init_cursor = init_cursor;
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os_display->select_cursor = select_cursor_kms;
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os_display->show_cursor = NULL;
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os_display->move_cursor = move_cursor_kms;
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os_display->restore_cursor = restore_cursor;
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os_display->disable_mouse = disable_mouse;
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intel_crtc->cursor_x = os_display->width/2;
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intel_crtc->cursor_y = os_display->height/2;
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select_cursor_kms(os_display->cursor);
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};
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safe_sti(ifl);
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#define XY_COLOR_BLT ((2<<29)|(0x50<<22)|(0x4))
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#define BLT_WRITE_ALPHA (1<<21)
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#define BLT_WRITE_RGB (1<<20)
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#if 1
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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struct drm_i915_gem_object *obj;
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struct intel_ring_buffer *ring;
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obj = i915_gem_alloc_object(dev, 4096);
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i915_gem_object_pin(obj, 4096, true);
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cmd_buffer = MapIoMem((addr_t)obj->pages[0], 4096, PG_SW|PG_NOCACHE);
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cmd_offset = obj->gtt_offset;
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};
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#endif
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main_device = dev;
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int err;
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err = init_bitmaps();
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if( !err )
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{
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printf("Initialize bitmap manager\n");
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};
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sna_init();
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LEAVE();
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return 0;
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};
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bool set_mode(struct drm_device *dev, struct drm_connector *connector,
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videomode_t *reqmode, bool strict)
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{
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struct drm_display_mode *mode = NULL, *tmpmode;
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drm_i915_private_t *dev_priv = dev->dev_private;
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struct drm_fb_helper *fb_helper = &dev_priv->fbdev->helper;
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bool ret = false;
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ENTER();
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dbgprintf("width %d height %d vrefresh %d\n",
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reqmode->width, reqmode->height, reqmode->freq);
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list_for_each_entry(tmpmode, &connector->modes, head)
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{
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if( (drm_mode_width(tmpmode) == reqmode->width) &&
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(drm_mode_height(tmpmode) == reqmode->height) &&
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(drm_mode_vrefresh(tmpmode) == reqmode->freq) )
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{
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mode = tmpmode;
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goto do_set;
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}
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};
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if( (mode == NULL) && (strict == false) )
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{
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list_for_each_entry(tmpmode, &connector->modes, head)
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{
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if( (drm_mode_width(tmpmode) == reqmode->width) &&
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(drm_mode_height(tmpmode) == reqmode->height) )
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{
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mode = tmpmode;
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goto do_set;
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}
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};
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};
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do_set:
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if( mode != NULL )
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{
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struct drm_framebuffer *fb;
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struct drm_encoder *encoder;
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struct drm_crtc *crtc;
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char *con_name;
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char *enc_name;
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encoder = connector->encoder;
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crtc = encoder->crtc;
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con_name = drm_get_connector_name(connector);
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enc_name = drm_get_encoder_name(encoder);
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dbgprintf("set mode %d %d connector %s encoder %s\n",
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reqmode->width, reqmode->height, con_name, enc_name);
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fb = fb_helper->fb;
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fb->width = reqmode->width;
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fb->height = reqmode->height;
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fb->pitches[0] = ALIGN(reqmode->width * 4, 64);
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fb->pitches[1] = ALIGN(reqmode->width * 4, 64);
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fb->pitches[2] = ALIGN(reqmode->width * 4, 64);
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fb->pitches[3] = ALIGN(reqmode->width * 4, 64);
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fb->bits_per_pixel = 32;
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fb->depth == 24;
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crtc->fb = fb;
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crtc->enabled = true;
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os_display->crtc = crtc;
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ret = drm_crtc_helper_set_mode(crtc, mode, 0, 0, fb);
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// select_cursor_kms(rdisplay->cursor);
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// radeon_show_cursor_kms(crtc);
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if (ret == true)
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{
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os_display->width = fb->width;
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os_display->height = fb->height;
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os_display->pitch = fb->pitches[0];
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os_display->vrefresh = drm_mode_vrefresh(mode);
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sysSetScreen(fb->width, fb->height, fb->pitches[0]);
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dbgprintf("new mode %d x %d pitch %d\n",
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fb->width, fb->height, fb->pitches[0]);
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}
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else
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DRM_ERROR("failed to set mode %d_%d on crtc %p\n",
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fb->width, fb->height, crtc);
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}
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LEAVE();
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return ret;
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};
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int get_videomodes(videomode_t *mode, int *count)
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{
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int err = -1;
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ENTER();
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dbgprintf("mode %x count %d\n", mode, *count);
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if( *count == 0 )
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{
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*count = os_display->supported_modes;
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err = 0;
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}
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else if( mode != NULL )
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{
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struct drm_display_mode *drmmode;
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int i = 0;
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if( *count > os_display->supported_modes)
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*count = os_display->supported_modes;
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list_for_each_entry(drmmode, &os_display->connector->modes, head)
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{
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if( i < *count)
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{
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mode->width = drm_mode_width(drmmode);
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mode->height = drm_mode_height(drmmode);
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mode->bpp = 32;
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mode->freq = drm_mode_vrefresh(drmmode);
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i++;
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mode++;
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}
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else break;
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};
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*count = i;
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err = 0;
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};
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LEAVE();
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return err;
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};
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int set_user_mode(videomode_t *mode)
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{
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int err = -1;
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ENTER();
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dbgprintf("width %d height %d vrefresh %d\n",
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mode->width, mode->height, mode->freq);
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if( (mode->width != 0) &&
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(mode->height != 0) &&
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(mode->freq != 0 ) &&
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( (mode->width != os_display->width) ||
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(mode->height != os_display->height) ||
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(mode->freq != os_display->vrefresh) ) )
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{
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if( set_mode(os_display->ddev, os_display->connector, mode, true) )
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err = 0;
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};
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LEAVE();
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return err;
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};
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void __attribute__((regparm(1))) destroy_cursor(cursor_t *cursor)
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{
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/* FIXME synchronization */
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list_del(&cursor->list);
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// radeon_bo_unpin(cursor->robj);
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// KernelFree(cursor->data);
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__DestroyObject(cursor);
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};
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int init_cursor(cursor_t *cursor)
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{
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struct drm_i915_private *dev_priv = os_display->ddev->dev_private;
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struct drm_i915_gem_object *obj;
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uint32_t *bits;
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uint32_t *src;
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int i,j;
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int ret;
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ENTER();
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if (dev_priv->info->cursor_needs_physical)
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{
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bits = (uint32_t*)KernelAlloc(CURSOR_WIDTH*CURSOR_HEIGHT*4);
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if (unlikely(bits == NULL))
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return ENOMEM;
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cursor->cobj = (struct drm_i915_gem_object *)GetPgAddr(bits);
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}
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else
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{
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obj = i915_gem_alloc_object(os_display->ddev, CURSOR_WIDTH*CURSOR_HEIGHT*4);
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if (unlikely(obj == NULL))
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return -ENOMEM;
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ret = i915_gem_object_pin(obj, CURSOR_WIDTH*CURSOR_HEIGHT*4, true);
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if (ret) {
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drm_gem_object_unreference(&obj->base);
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return ret;
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}
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/* You don't need to worry about fragmentation issues.
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* GTT space is continuous. I guarantee it. */
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bits = (u32*)MapIoMem(get_bus_addr() + obj->gtt_offset,
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CURSOR_WIDTH*CURSOR_HEIGHT*4, PG_SW);
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if (unlikely(bits == NULL))
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{
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i915_gem_object_unpin(obj);
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drm_gem_object_unreference(&obj->base);
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return -ENOMEM;
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};
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cursor->cobj = obj;
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};
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src = cursor->data;
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for(i = 0; i < 32; i++)
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{
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for(j = 0; j < 32; j++)
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*bits++ = *src++;
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for(j = 32; j < CURSOR_WIDTH; j++)
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*bits++ = 0;
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}
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for(i = 0; i < CURSOR_WIDTH*(CURSOR_HEIGHT-32); i++)
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*bits++ = 0;
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// release old cursor
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KernelFree(cursor->data);
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cursor->data = bits;
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cursor->header.destroy = destroy_cursor;
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LEAVE();
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return 0;
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}
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static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int pipe = intel_crtc->pipe;
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bool visible = base != 0;
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if (intel_crtc->cursor_visible != visible) {
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uint32_t cntl = I915_READ(CURCNTR(pipe));
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if (base) {
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cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
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cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
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cntl |= pipe << 28; /* Connect to correct pipe */
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} else {
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cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
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cntl |= CURSOR_MODE_DISABLE;
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}
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I915_WRITE(CURCNTR(pipe), cntl);
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intel_crtc->cursor_visible = visible;
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}
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/* and commit changes on next vblank */
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I915_WRITE(CURBASE(pipe), base);
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}
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void __stdcall move_cursor_kms(cursor_t *cursor, int x, int y)
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{
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struct drm_i915_private *dev_priv = os_display->ddev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(os_display->crtc);
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u32 base, pos;
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bool visible;
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int pipe = intel_crtc->pipe;
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intel_crtc->cursor_x = x;
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intel_crtc->cursor_y = y;
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x = x - cursor->hot_x;
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y = y - cursor->hot_y;
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pos = 0;
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base = intel_crtc->cursor_addr;
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if (x >= os_display->width)
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base = 0;
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if (y >= os_display->height)
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base = 0;
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if (x < 0)
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{
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if (x + intel_crtc->cursor_width < 0)
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base = 0;
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pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
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x = -x;
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}
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pos |= x << CURSOR_X_SHIFT;
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if (y < 0)
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{
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if (y + intel_crtc->cursor_height < 0)
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base = 0;
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pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
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y = -y;
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}
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pos |= y << CURSOR_Y_SHIFT;
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visible = base != 0;
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if (!visible && !intel_crtc->cursor_visible)
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return;
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|
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I915_WRITE(CURPOS(pipe), pos);
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// if (IS_845G(dev) || IS_I865G(dev))
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// i845_update_cursor(crtc, base);
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// else
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i9xx_update_cursor(os_display->crtc, base);
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|
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};
|
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|
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|
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cursor_t* __stdcall select_cursor_kms(cursor_t *cursor)
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{
|
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struct drm_i915_private *dev_priv = os_display->ddev->dev_private;
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(os_display->crtc);
|
|
cursor_t *old;
|
|
|
|
old = os_display->cursor;
|
|
os_display->cursor = cursor;
|
|
|
|
if (!dev_priv->info->cursor_needs_physical)
|
|
intel_crtc->cursor_addr = cursor->cobj->gtt_offset;
|
|
else
|
|
intel_crtc->cursor_addr = (addr_t)cursor->cobj;
|
|
|
|
intel_crtc->cursor_width = 32;
|
|
intel_crtc->cursor_height = 32;
|
|
|
|
move_cursor_kms(cursor, intel_crtc->cursor_x, intel_crtc->cursor_y);
|
|
return old;
|
|
};
|
|
|
|
|
|
#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
|
|
|
|
|
|
typedef struct
|
|
{
|
|
int left;
|
|
int top;
|
|
int right;
|
|
int bottom;
|
|
}rect_t;
|
|
|
|
|
|
#include "clip.inc"
|
|
|
|
void FASTCALL GetWindowRect(rect_t *rc)__asm__("GetWindowRect");
|
|
|
|
#define CURRENT_TASK (0x80003000)
|
|
|
|
static u32_t get_display_map()
|
|
{
|
|
u32_t addr;
|
|
|
|
addr = (u32_t)os_display;
|
|
addr+= sizeof(display_t); /* shoot me */
|
|
return *(u32_t*)addr;
|
|
}
|
|
|
|
#define XY_SRC_COPY_CHROMA_CMD ((2<<29)|(0x73<<22)|8)
|
|
#define ROP_COPY_SRC 0xCC
|
|
#define FORMAT8888 3
|
|
|
|
typedef int v4si __attribute__ ((vector_size (16)));
|
|
|
|
|
|
int blit_video(u32 hbitmap, int dst_x, int dst_y,
|
|
int src_x, int src_y, u32 w, u32 h)
|
|
{
|
|
drm_i915_private_t *dev_priv = main_device->dev_private;
|
|
struct intel_ring_buffer *ring;
|
|
|
|
bitmap_t *bitmap;
|
|
rect_t winrc;
|
|
clip_t dst_clip;
|
|
clip_t src_clip;
|
|
u32_t width;
|
|
u32_t height;
|
|
|
|
u32_t br13, cmd, slot_mask, *b;
|
|
u32_t offset;
|
|
u8 slot;
|
|
int n=0;
|
|
|
|
if(unlikely(hbitmap==0))
|
|
return -1;
|
|
|
|
bitmap = (bitmap_t*)hman_get_data(&bm_man, hbitmap);
|
|
|
|
if(unlikely(bitmap==NULL))
|
|
return -1;
|
|
|
|
|
|
GetWindowRect(&winrc);
|
|
|
|
dst_clip.xmin = 0;
|
|
dst_clip.ymin = 0;
|
|
dst_clip.xmax = winrc.right-winrc.left-1;
|
|
dst_clip.ymax = winrc.bottom -winrc.top -1;
|
|
|
|
src_clip.xmin = 0;
|
|
src_clip.ymin = 0;
|
|
src_clip.xmax = bitmap->width - 1;
|
|
src_clip.ymax = bitmap->height - 1;
|
|
|
|
width = w;
|
|
height = h;
|
|
|
|
if( blit_clip(&dst_clip, &dst_x, &dst_y,
|
|
&src_clip, &src_x, &src_y,
|
|
&width, &height) )
|
|
return 0;
|
|
|
|
dst_x+= winrc.left;
|
|
dst_y+= winrc.top;
|
|
|
|
slot = *((u8*)CURRENT_TASK);
|
|
|
|
slot_mask = (u32_t)slot<<24;
|
|
|
|
{
|
|
#if 0
|
|
static v4si write_mask = {0xFF000000, 0xFF000000,
|
|
0xFF000000, 0xFF000000};
|
|
|
|
u8* src_offset;
|
|
u8* dst_offset;
|
|
|
|
src_offset = (u8*)(src_y*bitmap->pitch + src_x*4);
|
|
src_offset += (u32)bitmap->uaddr;
|
|
|
|
dst_offset = (u8*)(dst_y*os_display->width + dst_x);
|
|
dst_offset+= get_display_map();
|
|
|
|
u32_t tmp_h = height;
|
|
|
|
__asm__ __volatile__ (
|
|
"movdqa %[write_mask], %%xmm7 \n"
|
|
"movd %[slot_mask], %%xmm6 \n"
|
|
"punpckldq %%xmm6, %%xmm6 \n"
|
|
"punpcklqdq %%xmm6, %%xmm6 \n"
|
|
:: [write_mask] "m" (write_mask),
|
|
[slot_mask] "g" (slot_mask)
|
|
:"xmm7", "xmm6");
|
|
|
|
while( tmp_h--)
|
|
{
|
|
u32_t tmp_w = width;
|
|
|
|
u8* tmp_src = src_offset;
|
|
u8* tmp_dst = dst_offset;
|
|
|
|
src_offset+= bitmap->pitch;
|
|
dst_offset+= os_display->width;
|
|
|
|
while( tmp_w >= 8 )
|
|
{
|
|
__asm__ __volatile__ (
|
|
"movq (%0), %%xmm0 \n"
|
|
"punpcklbw %%xmm0, %%xmm0 \n"
|
|
"movdqa %%xmm0, %%xmm1 \n"
|
|
"punpcklwd %%xmm0, %%xmm0 \n"
|
|
"punpckhwd %%xmm1, %%xmm1 \n"
|
|
"pcmpeqb %%xmm6, %%xmm0 \n"
|
|
"pcmpeqb %%xmm6, %%xmm1 \n"
|
|
"maskmovdqu %%xmm7, %%xmm0 \n"
|
|
"addl $16, %%edi \n"
|
|
"maskmovdqu %%xmm7, %%xmm1 \n"
|
|
:: "r" (tmp_dst), "D" (tmp_src)
|
|
:"xmm0", "xmm1");
|
|
__asm__ __volatile__ ("":::"edi");
|
|
tmp_w -= 8;
|
|
tmp_src += 32;
|
|
tmp_dst += 8;
|
|
};
|
|
|
|
if( tmp_w >= 4 )
|
|
{
|
|
__asm__ __volatile__ (
|
|
"movd (%0), %%xmm0 \n"
|
|
"punpcklbw %%xmm0, %%xmm0 \n"
|
|
"punpcklwd %%xmm0, %%xmm0 \n"
|
|
"pcmpeqb %%xmm6, %%xmm0 \n"
|
|
"maskmovdqu %%xmm7, %%xmm0 \n"
|
|
:: "r" (tmp_dst), "D" (tmp_src)
|
|
:"xmm0");
|
|
tmp_w -= 4;
|
|
tmp_src += 16;
|
|
tmp_dst += 4;
|
|
};
|
|
|
|
while( tmp_w--)
|
|
{
|
|
*(tmp_src+3) = (*tmp_dst==slot)?0xFF:0x00;
|
|
tmp_src+=4;
|
|
tmp_dst++;
|
|
};
|
|
};
|
|
#else
|
|
u8* src_offset;
|
|
u8* dst_offset;
|
|
u32 ifl;
|
|
|
|
src_offset = (u8*)(src_y*bitmap->pitch + src_x*4);
|
|
src_offset += (u32)bitmap->uaddr;
|
|
|
|
dst_offset = (u8*)(dst_y*os_display->width + dst_x);
|
|
dst_offset+= get_display_map();
|
|
|
|
u32_t tmp_h = height;
|
|
|
|
ifl = safe_cli();
|
|
while( tmp_h--)
|
|
{
|
|
u32_t tmp_w = width;
|
|
|
|
u8* tmp_src = src_offset;
|
|
u8* tmp_dst = dst_offset;
|
|
|
|
src_offset+= bitmap->pitch;
|
|
dst_offset+= os_display->width;
|
|
|
|
while( tmp_w--)
|
|
{
|
|
*(tmp_src+3) = (*tmp_dst==slot)?0xFF:0x00;
|
|
tmp_src+=4;
|
|
tmp_dst++;
|
|
};
|
|
};
|
|
safe_sti(ifl);
|
|
}
|
|
#endif
|
|
|
|
if((cmd_buffer & 0xFC0)==0xFC0)
|
|
cmd_buffer&= 0xFFFFF000;
|
|
|
|
b = (u32_t*)ALIGN(cmd_buffer,16);
|
|
|
|
offset = cmd_offset + ((u32_t)b & 0xFFF);
|
|
|
|
cmd = XY_SRC_COPY_CHROMA_CMD | BLT_WRITE_RGB | BLT_WRITE_ALPHA;
|
|
cmd |= 3 << 17;
|
|
|
|
br13 = os_display->pitch;
|
|
br13|= ROP_COPY_SRC << 16;
|
|
br13|= FORMAT8888 << 24;
|
|
|
|
b[n++] = cmd;
|
|
b[n++] = br13;
|
|
b[n++] = (dst_y << 16) | dst_x; // left, top
|
|
b[n++] = ((dst_y+height-1)<< 16)|(dst_x+width-1); // bottom, right
|
|
b[n++] = 0; // destination
|
|
b[n++] = (src_y << 16) | src_x; // source left & top
|
|
b[n++] = bitmap->pitch; // source pitch
|
|
b[n++] = bitmap->gaddr; // source
|
|
|
|
b[n++] = 0; // Transparency Color Low
|
|
b[n++] = 0x00FFFFFF; // Transparency Color High
|
|
|
|
b[n++] = MI_BATCH_BUFFER_END;
|
|
if( n & 1)
|
|
b[n++] = MI_NOOP;
|
|
|
|
i915_gem_object_set_to_gtt_domain(bitmap->obj, false);
|
|
|
|
if (HAS_BLT(main_device))
|
|
{
|
|
int ret;
|
|
|
|
ring = &dev_priv->ring[BCS];
|
|
ring->dispatch_execbuffer(ring, cmd_offset, n*4);
|
|
|
|
ret = intel_ring_begin(ring, 4);
|
|
if (ret)
|
|
return ret;
|
|
|
|
intel_ring_emit(ring, MI_FLUSH_DW);
|
|
intel_ring_emit(ring, 0);
|
|
intel_ring_emit(ring, 0);
|
|
intel_ring_emit(ring, MI_NOOP);
|
|
intel_ring_advance(ring);
|
|
}
|
|
else
|
|
{
|
|
ring = &dev_priv->ring[RCS];
|
|
ring->dispatch_execbuffer(ring, cmd_offset, n*4);
|
|
ring->flush(ring, 0, I915_GEM_DOMAIN_RENDER);
|
|
};
|
|
|
|
bitmap->obj->base.read_domains = I915_GEM_DOMAIN_CPU;
|
|
bitmap->obj->base.write_domain = I915_GEM_DOMAIN_CPU;
|
|
|
|
return 0;
|
|
fail:
|
|
return -1;
|
|
};
|
|
|
|
|
|
/* For display hotplug interrupt */
|
|
static void
|
|
ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
|
|
{
|
|
if ((dev_priv->irq_mask & mask) != 0) {
|
|
dev_priv->irq_mask &= ~mask;
|
|
I915_WRITE(DEIMR, dev_priv->irq_mask);
|
|
POSTING_READ(DEIMR);
|
|
}
|
|
}
|
|
|
|
static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
|
|
{
|
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
|
unsigned long irqflags;
|
|
|
|
// if (!i915_pipe_enabled(dev, pipe))
|
|
// return -EINVAL;
|
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
|
|
ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
|
|
DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
|
|
static int i915_interrupt_info(struct drm_device *dev)
|
|
{
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
int ret, i, pipe;
|
|
|
|
if (!HAS_PCH_SPLIT(dev)) {
|
|
dbgprintf("Interrupt enable: %08x\n",
|
|
I915_READ(IER));
|
|
dbgprintf("Interrupt identity: %08x\n",
|
|
I915_READ(IIR));
|
|
dbgprintf("Interrupt mask: %08x\n",
|
|
I915_READ(IMR));
|
|
for_each_pipe(pipe)
|
|
dbgprintf("Pipe %c stat: %08x\n",
|
|
pipe_name(pipe),
|
|
I915_READ(PIPESTAT(pipe)));
|
|
} else {
|
|
dbgprintf("North Display Interrupt enable: %08x\n",
|
|
I915_READ(DEIER));
|
|
dbgprintf("North Display Interrupt identity: %08x\n",
|
|
I915_READ(DEIIR));
|
|
dbgprintf("North Display Interrupt mask: %08x\n",
|
|
I915_READ(DEIMR));
|
|
dbgprintf("South Display Interrupt enable: %08x\n",
|
|
I915_READ(SDEIER));
|
|
dbgprintf("South Display Interrupt identity: %08x\n",
|
|
I915_READ(SDEIIR));
|
|
dbgprintf("South Display Interrupt mask: %08x\n",
|
|
I915_READ(SDEIMR));
|
|
dbgprintf("Graphics Interrupt enable: %08x\n",
|
|
I915_READ(GTIER));
|
|
dbgprintf("Graphics Interrupt identity: %08x\n",
|
|
I915_READ(GTIIR));
|
|
dbgprintf("Graphics Interrupt mask: %08x\n",
|
|
I915_READ(GTIMR));
|
|
}
|
|
dbgprintf("Interrupts received: %d\n",
|
|
atomic_read(&dev_priv->irq_received));
|
|
for (i = 0; i < I915_NUM_RINGS; i++) {
|
|
if (IS_GEN6(dev) || IS_GEN7(dev)) {
|
|
printf("Graphics Interrupt mask (%s): %08x\n",
|
|
dev_priv->ring[i].name,
|
|
I915_READ_IMR(&dev_priv->ring[i]));
|
|
}
|
|
// i915_ring_seqno_info(m, &dev_priv->ring[i]);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
void execute_buffer (struct drm_i915_gem_object *buffer, uint32_t offset,
|
|
int size)
|
|
{
|
|
struct intel_ring_buffer *ring;
|
|
drm_i915_private_t *dev_priv = main_device->dev_private;
|
|
u32 invalidate;
|
|
u32 seqno = 2;
|
|
|
|
offset += buffer->gtt_offset;
|
|
// dbgprintf("execute %x size %d\n", offset, size);
|
|
|
|
// asm volatile(
|
|
// "mfence \n"
|
|
// "wbinvd \n"
|
|
// "mfence \n"
|
|
// :::"memory");
|
|
|
|
ring = &dev_priv->ring[RCS];
|
|
ring->dispatch_execbuffer(ring, offset, size);
|
|
|
|
invalidate = I915_GEM_DOMAIN_COMMAND;
|
|
if (INTEL_INFO(main_device)->gen >= 4)
|
|
invalidate |= I915_GEM_DOMAIN_SAMPLER;
|
|
if (ring->flush(ring, invalidate, 0))
|
|
i915_gem_next_request_seqno(ring);
|
|
|
|
ring->irq_get(ring);
|
|
|
|
ring->add_request(ring, &seqno);
|
|
|
|
// i915_interrupt_info(main_device);
|
|
|
|
// ironlake_enable_vblank(main_device, 0);
|
|
};
|
|
|
|
|
|
int blit_textured(u32 hbitmap, int dst_x, int dst_y,
|
|
int src_x, int src_y, u32 w, u32 h)
|
|
{
|
|
drm_i915_private_t *dev_priv = main_device->dev_private;
|
|
|
|
bitmap_t *src_bitmap, *dst_bitmap;
|
|
bitmap_t screen;
|
|
|
|
rect_t winrc;
|
|
|
|
// dbgprintf(" handle: %d dx %d dy %d sx %d sy %d w %d h %d\n",
|
|
// hbitmap, dst_x, dst_y, src_x, src_y, w, h);
|
|
|
|
if(unlikely(hbitmap==0))
|
|
return -1;
|
|
|
|
src_bitmap = (bitmap_t*)hman_get_data(&bm_man, hbitmap);
|
|
// dbgprintf("bitmap %x\n", src_bitmap);
|
|
|
|
if(unlikely(src_bitmap==NULL))
|
|
return -1;
|
|
|
|
GetWindowRect(&winrc);
|
|
|
|
screen.pitch = os_display->pitch;
|
|
screen.gaddr = 0;
|
|
screen.width = os_display->width;
|
|
screen.height = os_display->height;
|
|
screen.obj = (void*)-1;
|
|
|
|
dst_bitmap = &screen;
|
|
|
|
dst_x+= winrc.left;
|
|
dst_y+= winrc.top;
|
|
|
|
sna_blit_copy(dst_bitmap, dst_x, dst_y, w, h, src_bitmap, src_x, src_y);
|
|
|
|
};
|
|
|
|
|
|
void __stdcall run_workqueue(struct workqueue_struct *cwq)
|
|
{
|
|
unsigned long irqflags;
|
|
|
|
// dbgprintf("wq: %x head %x, next %x\n",
|
|
// cwq, &cwq->worklist, cwq->worklist.next);
|
|
|
|
spin_lock_irqsave(&cwq->lock, irqflags);
|
|
|
|
while (!list_empty(&cwq->worklist))
|
|
{
|
|
struct work_struct *work = list_entry(cwq->worklist.next,
|
|
struct work_struct, entry);
|
|
work_func_t f = work->func;
|
|
list_del_init(cwq->worklist.next);
|
|
// dbgprintf("head %x, next %x\n",
|
|
// &cwq->worklist, cwq->worklist.next);
|
|
|
|
spin_unlock_irqrestore(&cwq->lock, irqflags);
|
|
f(work);
|
|
spin_lock_irqsave(&cwq->lock, irqflags);
|
|
}
|
|
|
|
spin_unlock_irqrestore(&cwq->lock, irqflags);
|
|
}
|
|
|
|
|
|
static inline
|
|
int __queue_work(struct workqueue_struct *wq,
|
|
struct work_struct *work)
|
|
{
|
|
unsigned long flags;
|
|
// ENTER();
|
|
|
|
// dbgprintf("wq: %x, work: %x\n",
|
|
// wq, work );
|
|
|
|
if(!list_empty(&work->entry))
|
|
return 0;
|
|
|
|
spin_lock_irqsave(&wq->lock, flags);
|
|
|
|
if(list_empty(&wq->worklist))
|
|
TimerHs(0,0, run_workqueue, wq);
|
|
|
|
list_add_tail(&work->entry, &wq->worklist);
|
|
|
|
spin_unlock_irqrestore(&wq->lock, flags);
|
|
// dbgprintf("wq: %x head %x, next %x\n",
|
|
// wq, &wq->worklist, wq->worklist.next);
|
|
|
|
// LEAVE();
|
|
return 1;
|
|
};
|
|
|
|
void __stdcall delayed_work_timer_fn(unsigned long __data)
|
|
{
|
|
// ENTER();
|
|
struct delayed_work *dwork = (struct delayed_work *)__data;
|
|
struct workqueue_struct *wq = dwork->work.data;
|
|
|
|
// dbgprintf("wq: %x, work: %x\n",
|
|
// wq, &dwork->work );
|
|
|
|
__queue_work(wq, &dwork->work);
|
|
// LEAVE();
|
|
}
|
|
|
|
|
|
int queue_delayed_work_on(struct workqueue_struct *wq,
|
|
struct delayed_work *dwork, unsigned long delay)
|
|
{
|
|
struct work_struct *work = &dwork->work;
|
|
|
|
work->data = wq;
|
|
TimerHs(0,0, delayed_work_timer_fn, dwork);
|
|
return 1;
|
|
}
|
|
|
|
int queue_delayed_work(struct workqueue_struct *wq,
|
|
struct delayed_work *dwork, unsigned long delay)
|
|
{
|
|
u32 flags;
|
|
// ENTER();
|
|
|
|
// dbgprintf("wq: %x, work: %x\n",
|
|
// wq, &dwork->work );
|
|
|
|
if (delay == 0)
|
|
return __queue_work(wq, &dwork->work);
|
|
|
|
return queue_delayed_work_on(wq, dwork, delay);
|
|
}
|
|
|
|
|
|
struct workqueue_struct *alloc_workqueue(const char *fmt,
|
|
unsigned int flags,
|
|
int max_active)
|
|
{
|
|
struct workqueue_struct *wq;
|
|
|
|
wq = kzalloc(sizeof(*wq),0);
|
|
if (!wq)
|
|
goto err;
|
|
|
|
INIT_LIST_HEAD(&wq->worklist);
|
|
|
|
return wq;
|
|
err:
|
|
return NULL;
|
|
}
|
|
|
|
|
|
|
|
|
|
|