261 lines
7.7 KiB
C
261 lines
7.7 KiB
C
/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#ifndef _INTEL_GUC_FWIF_H
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#define _INTEL_GUC_FWIF_H
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/*
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* This file is partially autogenerated, although currently with some manual
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* fixups afterwards. In future, it should be entirely autogenerated, in order
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* to ensure that the definitions herein remain in sync with those used by the
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* GuC's own firmware.
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*
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* EDITING THIS FILE IS THEREFORE NOT RECOMMENDED - YOUR CHANGES MAY BE LOST.
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*/
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#define GFXCORE_FAMILY_GEN9 12
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#define GFXCORE_FAMILY_UNKNOWN 0x7fffffff
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#define GUC_CTX_PRIORITY_KMD_HIGH 0
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#define GUC_CTX_PRIORITY_HIGH 1
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#define GUC_CTX_PRIORITY_KMD_NORMAL 2
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#define GUC_CTX_PRIORITY_NORMAL 3
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#define GUC_MAX_GPU_CONTEXTS 1024
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#define GUC_INVALID_CTX_ID GUC_MAX_GPU_CONTEXTS
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/* Work queue item header definitions */
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#define WQ_STATUS_ACTIVE 1
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#define WQ_STATUS_SUSPENDED 2
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#define WQ_STATUS_CMD_ERROR 3
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#define WQ_STATUS_ENGINE_ID_NOT_USED 4
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#define WQ_STATUS_SUSPENDED_FROM_RESET 5
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#define WQ_TYPE_SHIFT 0
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#define WQ_TYPE_BATCH_BUF (0x1 << WQ_TYPE_SHIFT)
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#define WQ_TYPE_PSEUDO (0x2 << WQ_TYPE_SHIFT)
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#define WQ_TYPE_INORDER (0x3 << WQ_TYPE_SHIFT)
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#define WQ_TARGET_SHIFT 10
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#define WQ_LEN_SHIFT 16
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#define WQ_NO_WCFLUSH_WAIT (1 << 27)
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#define WQ_PRESENT_WORKLOAD (1 << 28)
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#define WQ_WORKLOAD_SHIFT 29
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#define WQ_WORKLOAD_GENERAL (0 << WQ_WORKLOAD_SHIFT)
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#define WQ_WORKLOAD_GPGPU (1 << WQ_WORKLOAD_SHIFT)
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#define WQ_WORKLOAD_TOUCH (2 << WQ_WORKLOAD_SHIFT)
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#define WQ_RING_TAIL_SHIFT 20
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#define WQ_RING_TAIL_MASK (0x7FF << WQ_RING_TAIL_SHIFT)
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#define GUC_DOORBELL_ENABLED 1
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#define GUC_DOORBELL_DISABLED 0
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#define GUC_CTX_DESC_ATTR_ACTIVE (1 << 0)
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#define GUC_CTX_DESC_ATTR_PENDING_DB (1 << 1)
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#define GUC_CTX_DESC_ATTR_KERNEL (1 << 2)
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#define GUC_CTX_DESC_ATTR_PREEMPT (1 << 3)
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#define GUC_CTX_DESC_ATTR_RESET (1 << 4)
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#define GUC_CTX_DESC_ATTR_WQLOCKED (1 << 5)
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#define GUC_CTX_DESC_ATTR_PCH (1 << 6)
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#define GUC_CTX_DESC_ATTR_TERMINATED (1 << 7)
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/* The guc control data is 10 DWORDs */
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#define GUC_CTL_CTXINFO 0
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#define GUC_CTL_CTXNUM_IN16_SHIFT 0
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#define GUC_CTL_BASE_ADDR_SHIFT 12
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#define GUC_CTL_ARAT_HIGH 1
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#define GUC_CTL_ARAT_LOW 2
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#define GUC_CTL_DEVICE_INFO 3
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#define GUC_CTL_GTTYPE_SHIFT 0
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#define GUC_CTL_COREFAMILY_SHIFT 7
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#define GUC_CTL_LOG_PARAMS 4
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#define GUC_LOG_VALID (1 << 0)
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#define GUC_LOG_NOTIFY_ON_HALF_FULL (1 << 1)
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#define GUC_LOG_ALLOC_IN_MEGABYTE (1 << 3)
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#define GUC_LOG_CRASH_PAGES 1
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#define GUC_LOG_CRASH_SHIFT 4
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#define GUC_LOG_DPC_PAGES 3
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#define GUC_LOG_DPC_SHIFT 6
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#define GUC_LOG_ISR_PAGES 3
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#define GUC_LOG_ISR_SHIFT 9
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#define GUC_LOG_BUF_ADDR_SHIFT 12
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#define GUC_CTL_PAGE_FAULT_CONTROL 5
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#define GUC_CTL_WA 6
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#define GUC_CTL_WA_UK_BY_DRIVER (1 << 3)
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#define GUC_CTL_FEATURE 7
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#define GUC_CTL_VCS2_ENABLED (1 << 0)
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#define GUC_CTL_KERNEL_SUBMISSIONS (1 << 1)
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#define GUC_CTL_FEATURE2 (1 << 2)
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#define GUC_CTL_POWER_GATING (1 << 3)
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#define GUC_CTL_DISABLE_SCHEDULER (1 << 4)
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#define GUC_CTL_PREEMPTION_LOG (1 << 5)
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#define GUC_CTL_ENABLE_SLPC (1 << 7)
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#define GUC_CTL_RESET_ON_PREMPT_FAILURE (1 << 8)
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#define GUC_CTL_DEBUG 8
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#define GUC_LOG_VERBOSITY_SHIFT 0
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#define GUC_LOG_VERBOSITY_LOW (0 << GUC_LOG_VERBOSITY_SHIFT)
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#define GUC_LOG_VERBOSITY_MED (1 << GUC_LOG_VERBOSITY_SHIFT)
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#define GUC_LOG_VERBOSITY_HIGH (2 << GUC_LOG_VERBOSITY_SHIFT)
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#define GUC_LOG_VERBOSITY_ULTRA (3 << GUC_LOG_VERBOSITY_SHIFT)
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/* Verbosity range-check limits, without the shift */
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#define GUC_LOG_VERBOSITY_MIN 0
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#define GUC_LOG_VERBOSITY_MAX 3
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#define GUC_CTL_RSRVD 9
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#define GUC_CTL_MAX_DWORDS (GUC_CTL_RSRVD + 1)
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struct guc_doorbell_info {
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u32 db_status;
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u32 cookie;
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u32 reserved[14];
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} __packed;
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union guc_doorbell_qw {
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struct {
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u32 db_status;
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u32 cookie;
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};
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u64 value_qw;
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} __packed;
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#define GUC_MAX_DOORBELLS 256
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#define GUC_INVALID_DOORBELL_ID (GUC_MAX_DOORBELLS)
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#define GUC_DB_SIZE (PAGE_SIZE)
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#define GUC_WQ_SIZE (PAGE_SIZE * 2)
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/* Work item for submitting workloads into work queue of GuC. */
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struct guc_wq_item {
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u32 header;
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u32 context_desc;
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u32 ring_tail;
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u32 fence_id;
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} __packed;
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struct guc_process_desc {
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u32 context_id;
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u64 db_base_addr;
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u32 head;
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u32 tail;
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u32 error_offset;
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u64 wq_base_addr;
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u32 wq_size_bytes;
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u32 wq_status;
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u32 engine_presence;
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u32 priority;
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u32 reserved[30];
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} __packed;
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/* engine id and context id is packed into guc_execlist_context.context_id*/
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#define GUC_ELC_CTXID_OFFSET 0
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#define GUC_ELC_ENGINE_OFFSET 29
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/* The execlist context including software and HW information */
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struct guc_execlist_context {
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u32 context_desc;
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u32 context_id;
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u32 ring_status;
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u32 ring_lcra;
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u32 ring_begin;
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u32 ring_end;
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u32 ring_next_free_location;
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u32 ring_current_tail_pointer_value;
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u8 engine_state_submit_value;
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u8 engine_state_wait_value;
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u16 pagefault_count;
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u16 engine_submit_queue_count;
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} __packed;
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/*Context descriptor for communicating between uKernel and Driver*/
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struct guc_context_desc {
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u32 sched_common_area;
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u32 context_id;
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u32 pas_id;
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u8 engines_used;
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u64 db_trigger_cpu;
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u32 db_trigger_uk;
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u64 db_trigger_phy;
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u16 db_id;
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struct guc_execlist_context lrc[I915_NUM_RINGS];
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u8 attribute;
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u32 priority;
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u32 wq_sampled_tail_offset;
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u32 wq_total_submit_enqueues;
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u32 process_desc;
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u32 wq_addr;
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u32 wq_size;
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u32 engine_presence;
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u8 engine_suspended;
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u8 reserved0[3];
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u64 reserved1[1];
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u64 desc_private;
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} __packed;
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#define GUC_FORCEWAKE_RENDER (1 << 0)
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#define GUC_FORCEWAKE_MEDIA (1 << 1)
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#define GUC_POWER_UNSPECIFIED 0
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#define GUC_POWER_D0 1
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#define GUC_POWER_D1 2
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#define GUC_POWER_D2 3
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#define GUC_POWER_D3 4
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/* This Action will be programmed in C180 - SOFT_SCRATCH_O_REG */
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enum host2guc_action {
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HOST2GUC_ACTION_DEFAULT = 0x0,
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HOST2GUC_ACTION_SAMPLE_FORCEWAKE = 0x6,
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HOST2GUC_ACTION_ALLOCATE_DOORBELL = 0x10,
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HOST2GUC_ACTION_DEALLOCATE_DOORBELL = 0x20,
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HOST2GUC_ACTION_ENTER_S_STATE = 0x501,
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HOST2GUC_ACTION_EXIT_S_STATE = 0x502,
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HOST2GUC_ACTION_SLPC_REQUEST = 0x3003,
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HOST2GUC_ACTION_LIMIT
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};
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/*
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* The GuC sends its response to a command by overwriting the
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* command in SS0. The response is distinguishable from a command
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* by the fact that all the MASK bits are set. The remaining bits
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* give more detail.
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*/
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#define GUC2HOST_RESPONSE_MASK ((u32)0xF0000000)
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#define GUC2HOST_IS_RESPONSE(x) ((u32)(x) >= GUC2HOST_RESPONSE_MASK)
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#define GUC2HOST_STATUS(x) (GUC2HOST_RESPONSE_MASK | (x))
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/* GUC will return status back to SOFT_SCRATCH_O_REG */
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enum guc2host_status {
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GUC2HOST_STATUS_SUCCESS = GUC2HOST_STATUS(0x0),
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GUC2HOST_STATUS_ALLOCATE_DOORBELL_FAIL = GUC2HOST_STATUS(0x10),
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GUC2HOST_STATUS_DEALLOCATE_DOORBELL_FAIL = GUC2HOST_STATUS(0x20),
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GUC2HOST_STATUS_GENERIC_FAIL = GUC2HOST_STATUS(0x0000F000)
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};
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#endif
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