483 lines
14 KiB
C
483 lines
14 KiB
C
/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
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*/
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/*
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*
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* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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//#include <linux/device.h>
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#include "drmP.h"
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#include "drm.h"
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#include "i915_drm.h"
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#include "i915_drv.h"
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#include "intel_drv.h"
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mod_devicetable.h>
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#include <errno-base.h>
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#include <linux/pci.h>
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#include <syscall.h>
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#define __read_mostly
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int init_display_kms(struct drm_device *dev);
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struct drm_device *main_device;
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int i915_panel_ignore_lid __read_mostly = 0;
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unsigned int i915_powersave __read_mostly = 0;
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unsigned int i915_enable_rc6 __read_mostly = -1;
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unsigned int i915_enable_fbc __read_mostly = 0;
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unsigned int i915_lvds_downclock __read_mostly = 0;
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unsigned int i915_panel_use_ssc __read_mostly = 1;
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int i915_vbt_sdvo_panel_type __read_mostly = -1;
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#define PCI_VENDOR_ID_INTEL 0x8086
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#define INTEL_VGA_DEVICE(id, info) { \
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.class = PCI_BASE_CLASS_DISPLAY << 16, \
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.class_mask = 0xff0000, \
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.vendor = 0x8086, \
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.device = id, \
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.subvendor = PCI_ANY_ID, \
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.subdevice = PCI_ANY_ID, \
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.driver_data = (unsigned long) info }
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static const struct intel_device_info intel_i915g_info = {
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.gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
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.has_overlay = 1, .overlay_needs_physical = 1,
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};
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static const struct intel_device_info intel_i915gm_info = {
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.gen = 3, .is_mobile = 1,
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.cursor_needs_physical = 1,
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.has_overlay = 1, .overlay_needs_physical = 1,
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.supports_tv = 1,
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};
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static const struct intel_device_info intel_i945g_info = {
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.gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
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.has_overlay = 1, .overlay_needs_physical = 1,
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};
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static const struct intel_device_info intel_i945gm_info = {
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.gen = 3, .is_i945gm = 1, .is_mobile = 1,
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.has_hotplug = 1, .cursor_needs_physical = 1,
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.has_overlay = 1, .overlay_needs_physical = 1,
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.supports_tv = 1,
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};
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static const struct intel_device_info intel_i965g_info = {
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.gen = 4, .is_broadwater = 1,
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.has_hotplug = 1,
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.has_overlay = 1,
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};
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static const struct intel_device_info intel_i965gm_info = {
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.gen = 4, .is_crestline = 1,
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.is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
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.has_overlay = 1,
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.supports_tv = 1,
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};
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static const struct intel_device_info intel_g33_info = {
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.gen = 3, .is_g33 = 1,
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.need_gfx_hws = 1, .has_hotplug = 1,
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.has_overlay = 1,
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};
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static const struct intel_device_info intel_g45_info = {
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.gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
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.has_pipe_cxsr = 1, .has_hotplug = 1,
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.has_bsd_ring = 1,
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};
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static const struct intel_device_info intel_gm45_info = {
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.gen = 4, .is_g4x = 1,
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.is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
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.has_pipe_cxsr = 1, .has_hotplug = 1,
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.supports_tv = 1,
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.has_bsd_ring = 1,
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};
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static const struct intel_device_info intel_pineview_info = {
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.gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
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.need_gfx_hws = 1, .has_hotplug = 1,
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.has_overlay = 1,
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};
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static const struct intel_device_info intel_ironlake_d_info = {
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.gen = 5,
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.need_gfx_hws = 1, .has_pipe_cxsr = 1, .has_hotplug = 1,
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.has_bsd_ring = 1,
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};
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static const struct intel_device_info intel_ironlake_m_info = {
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.gen = 5, .is_mobile = 1,
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.need_gfx_hws = 1, .has_hotplug = 1,
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.has_fbc = 1,
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.has_bsd_ring = 1,
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};
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static const struct intel_device_info intel_sandybridge_d_info = {
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.gen = 6,
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.need_gfx_hws = 1, .has_hotplug = 1,
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.has_bsd_ring = 1,
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.has_blt_ring = 1,
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};
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static const struct intel_device_info intel_sandybridge_m_info = {
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.gen = 6, .is_mobile = 1,
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.need_gfx_hws = 1, .has_hotplug = 1,
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.has_fbc = 1,
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.has_bsd_ring = 1,
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.has_blt_ring = 1,
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};
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static const struct intel_device_info intel_ivybridge_d_info = {
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.is_ivybridge = 1, .gen = 7,
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.need_gfx_hws = 1, .has_hotplug = 1,
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.has_bsd_ring = 1,
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.has_blt_ring = 1,
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};
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static const struct intel_device_info intel_ivybridge_m_info = {
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.is_ivybridge = 1, .gen = 7, .is_mobile = 1,
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.need_gfx_hws = 1, .has_hotplug = 1,
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.has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */
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.has_bsd_ring = 1,
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.has_blt_ring = 1,
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};
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static const struct pci_device_id pciidlist[] = { /* aka */
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INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */
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INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */
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INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */
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INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */
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INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */
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INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */
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INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */
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INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */
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INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */
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INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */
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INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */
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INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */
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INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */
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INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */
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INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */
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INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */
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INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */
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INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */
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INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */
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INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */
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INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */
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INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */
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INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
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INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
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INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
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INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
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INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
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INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
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INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
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INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
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INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
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INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
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INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
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INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
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INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
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INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
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INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
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INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
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{0, 0, 0}
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};
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#define INTEL_PCH_DEVICE_ID_MASK 0xff00
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#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
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#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
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#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
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void intel_detect_pch(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct pci_dev *pch;
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/*
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* The reason to probe ISA bridge instead of Dev31:Fun0 is to
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* make graphics device passthrough work easy for VMM, that only
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* need to expose ISA bridge to let driver know the real hardware
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* underneath. This is a requirement from virtualization team.
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*/
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pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
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if (pch) {
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if (pch->vendor == PCI_VENDOR_ID_INTEL) {
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int id;
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id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
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if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
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dev_priv->pch_type = PCH_IBX;
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DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
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} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
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dev_priv->pch_type = PCH_CPT;
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DRM_DEBUG_KMS("Found CougarPoint PCH\n");
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} else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
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/* PantherPoint is CPT compatible */
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dev_priv->pch_type = PCH_CPT;
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DRM_DEBUG_KMS("Found PatherPoint PCH\n");
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}
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}
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}
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}
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void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
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{
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int count;
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count = 0;
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while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
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udelay(10);
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I915_WRITE_NOTRACE(FORCEWAKE, 1);
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POSTING_READ(FORCEWAKE);
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count = 0;
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while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0)
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udelay(10);
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}
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void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
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{
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int count;
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count = 0;
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while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1))
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udelay(10);
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I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 1);
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POSTING_READ(FORCEWAKE_MT);
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count = 0;
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while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0)
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udelay(10);
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}
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/*
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* Generally this is called implicitly by the register read function. However,
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* if some sequence requires the GT to not power down then this function should
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* be called at the beginning of the sequence followed by a call to
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* gen6_gt_force_wake_put() at the end of the sequence.
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*/
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void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
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{
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unsigned long irqflags;
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spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
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if (dev_priv->forcewake_count++ == 0)
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dev_priv->display.force_wake_get(dev_priv);
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spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
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}
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void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
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{
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I915_WRITE_NOTRACE(FORCEWAKE, 0);
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POSTING_READ(FORCEWAKE);
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}
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void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
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{
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I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 0);
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POSTING_READ(FORCEWAKE_MT);
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}
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/*
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* see gen6_gt_force_wake_get()
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*/
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void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
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{
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unsigned long irqflags;
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spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
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if (--dev_priv->forcewake_count == 0)
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dev_priv->display.force_wake_put(dev_priv);
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spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
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}
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void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
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{
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if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
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int loop = 500;
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u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
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while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
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udelay(10);
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fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
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}
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// WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES);
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dev_priv->gt_fifo_count = fifo;
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}
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dev_priv->gt_fifo_count--;
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}
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int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent);
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int i915_init(void)
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{
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static pci_dev_t device;
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const struct pci_device_id *ent;
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int err;
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if( init_agp() != 0)
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{
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DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
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return 0;
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};
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ent = find_pci_device(&device, pciidlist);
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if( unlikely(ent == NULL) )
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{
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dbgprintf("device not found\n");
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return 0;
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};
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dbgprintf("device %x:%x\n", device.pci_dev.vendor,
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device.pci_dev.device);
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err = drm_get_dev(&device.pci_dev, ent);
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return err;
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}
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int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent)
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{
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struct drm_device *dev;
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int ret;
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ENTER();
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dev = kzalloc(sizeof(*dev), 0);
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if (!dev)
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return -ENOMEM;
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// ret = pci_enable_device(pdev);
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// if (ret)
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// goto err_g1;
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// pci_set_master(pdev);
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// if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) {
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// printk(KERN_ERR "DRM: Fill_in_dev failed.\n");
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// goto err_g2;
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// }
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dev->pdev = pdev;
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dev->pci_device = pdev->device;
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dev->pci_vendor = pdev->vendor;
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INIT_LIST_HEAD(&dev->filelist);
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INIT_LIST_HEAD(&dev->ctxlist);
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INIT_LIST_HEAD(&dev->vmalist);
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INIT_LIST_HEAD(&dev->maplist);
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spin_lock_init(&dev->count_lock);
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mutex_init(&dev->struct_mutex);
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mutex_init(&dev->ctxlist_mutex);
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ret = i915_driver_load(dev, ent->driver_data );
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if (ret)
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goto err_g4;
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ret = init_display_kms(dev);
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if (ret)
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goto err_g4;
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LEAVE();
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return 0;
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err_g4:
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// drm_put_minor(&dev->primary);
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//err_g3:
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// if (drm_core_check_feature(dev, DRIVER_MODESET))
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// drm_put_minor(&dev->control);
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//err_g2:
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// pci_disable_device(pdev);
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//err_g1:
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free(dev);
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LEAVE();
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return ret;
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}
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#define __i915_read(x, y) \
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u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
|
|
u##x val = 0; \
|
|
if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
|
|
unsigned long irqflags; \
|
|
spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
|
|
if (dev_priv->forcewake_count == 0) \
|
|
dev_priv->display.force_wake_get(dev_priv); \
|
|
val = read##y(dev_priv->regs + reg); \
|
|
if (dev_priv->forcewake_count == 0) \
|
|
dev_priv->display.force_wake_put(dev_priv); \
|
|
spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
|
|
} else { \
|
|
val = read##y(dev_priv->regs + reg); \
|
|
} \
|
|
return val; \
|
|
}
|
|
|
|
__i915_read(8, b)
|
|
__i915_read(16, w)
|
|
__i915_read(32, l)
|
|
__i915_read(64, q)
|
|
#undef __i915_read
|
|
|
|
#define __i915_write(x, y) \
|
|
void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
|
|
if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
|
|
__gen6_gt_wait_for_fifo(dev_priv); \
|
|
} \
|
|
write##y(val, dev_priv->regs + reg); \
|
|
}
|
|
__i915_write(8, b)
|
|
__i915_write(16, w)
|
|
__i915_write(32, l)
|
|
__i915_write(64, q)
|
|
#undef __i915_write
|