1002 lines
28 KiB
C
1002 lines
28 KiB
C
/*
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* Copyright 2007-8 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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#include <drm/drmP.h>
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#include <drm/radeon_drm.h>
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#include "radeon.h"
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#include "atom.h"
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#include "atom-bits.h"
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#include <drm/drm_dp_helper.h>
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/* move these to drm_dp_helper.c/h */
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#define DP_LINK_CONFIGURATION_SIZE 9
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#define DP_LINK_STATUS_SIZE 6
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#define DP_DPCD_SIZE 8
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static char *voltage_names[] = {
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"0.4V", "0.6V", "0.8V", "1.2V"
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};
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static char *pre_emph_names[] = {
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"0dB", "3.5dB", "6dB", "9.5dB"
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};
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/***** radeon AUX functions *****/
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union aux_channel_transaction {
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PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
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PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
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};
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static int radeon_process_aux_ch(struct radeon_i2c_chan *chan,
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u8 *send, int send_bytes,
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u8 *recv, int recv_size,
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u8 delay, u8 *ack)
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{
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struct drm_device *dev = chan->dev;
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struct radeon_device *rdev = dev->dev_private;
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union aux_channel_transaction args;
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int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
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unsigned char *base;
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int recv_bytes;
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memset(&args, 0, sizeof(args));
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base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1);
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memcpy(base, send, send_bytes);
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args.v1.lpAuxRequest = 0 + 4;
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args.v1.lpDataOut = 16 + 4;
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args.v1.ucDataOutLen = 0;
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args.v1.ucChannelID = chan->rec.i2c_id;
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args.v1.ucDelay = delay / 10;
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if (ASIC_IS_DCE4(rdev))
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args.v2.ucHPD_ID = chan->rec.hpd;
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atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
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*ack = args.v1.ucReplyStatus;
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/* timeout */
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if (args.v1.ucReplyStatus == 1) {
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DRM_DEBUG_KMS("dp_aux_ch timeout\n");
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return -ETIMEDOUT;
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}
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/* flags not zero */
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if (args.v1.ucReplyStatus == 2) {
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DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
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return -EBUSY;
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}
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/* error */
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if (args.v1.ucReplyStatus == 3) {
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DRM_DEBUG_KMS("dp_aux_ch error\n");
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return -EIO;
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}
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recv_bytes = args.v1.ucDataOutLen;
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if (recv_bytes > recv_size)
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recv_bytes = recv_size;
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if (recv && recv_size)
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memcpy(recv, base + 16, recv_bytes);
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return recv_bytes;
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}
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static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector,
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u16 address, u8 *send, u8 send_bytes, u8 delay)
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{
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struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
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int ret;
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u8 msg[20];
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int msg_bytes = send_bytes + 4;
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u8 ack;
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unsigned retry;
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if (send_bytes > 16)
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return -1;
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msg[0] = address;
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msg[1] = address >> 8;
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msg[2] = AUX_NATIVE_WRITE << 4;
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msg[3] = (msg_bytes << 4) | (send_bytes - 1);
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memcpy(&msg[4], send, send_bytes);
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for (retry = 0; retry < 4; retry++) {
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ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
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msg, msg_bytes, NULL, 0, delay, &ack);
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if (ret == -EBUSY)
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continue;
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else if (ret < 0)
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return ret;
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if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
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return send_bytes;
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else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
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udelay(400);
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else
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return -EIO;
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}
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return -EIO;
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}
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static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector,
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u16 address, u8 *recv, int recv_bytes, u8 delay)
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{
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struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
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u8 msg[4];
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int msg_bytes = 4;
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u8 ack;
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int ret;
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unsigned retry;
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msg[0] = address;
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msg[1] = address >> 8;
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msg[2] = AUX_NATIVE_READ << 4;
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msg[3] = (msg_bytes << 4) | (recv_bytes - 1);
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for (retry = 0; retry < 4; retry++) {
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ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
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msg, msg_bytes, recv, recv_bytes, delay, &ack);
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if (ret == -EBUSY)
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continue;
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else if (ret < 0)
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return ret;
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if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
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return ret;
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else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
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udelay(400);
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else if (ret == 0)
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return -EPROTO;
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else
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return -EIO;
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}
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return -EIO;
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}
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static void radeon_write_dpcd_reg(struct radeon_connector *radeon_connector,
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u16 reg, u8 val)
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{
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radeon_dp_aux_native_write(radeon_connector, reg, &val, 1, 0);
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}
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static u8 radeon_read_dpcd_reg(struct radeon_connector *radeon_connector,
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u16 reg)
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{
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u8 val = 0;
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radeon_dp_aux_native_read(radeon_connector, reg, &val, 1, 0);
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return val;
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}
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int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
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u8 write_byte, u8 *read_byte)
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{
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struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
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struct radeon_i2c_chan *auxch = (struct radeon_i2c_chan *)adapter;
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u16 address = algo_data->address;
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u8 msg[5];
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u8 reply[2];
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unsigned retry;
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int msg_bytes;
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int reply_bytes = 1;
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int ret;
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u8 ack;
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/* Set up the command byte */
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if (mode & MODE_I2C_READ)
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msg[2] = AUX_I2C_READ << 4;
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else
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msg[2] = AUX_I2C_WRITE << 4;
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if (!(mode & MODE_I2C_STOP))
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msg[2] |= AUX_I2C_MOT << 4;
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msg[0] = address;
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msg[1] = address >> 8;
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switch (mode) {
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case MODE_I2C_WRITE:
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msg_bytes = 5;
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msg[3] = msg_bytes << 4;
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msg[4] = write_byte;
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break;
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case MODE_I2C_READ:
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msg_bytes = 4;
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msg[3] = msg_bytes << 4;
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break;
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default:
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msg_bytes = 4;
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msg[3] = 3 << 4;
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break;
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}
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for (retry = 0; retry < 4; retry++) {
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ret = radeon_process_aux_ch(auxch,
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msg, msg_bytes, reply, reply_bytes, 0, &ack);
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if (ret == -EBUSY)
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continue;
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else if (ret < 0) {
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DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
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return ret;
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}
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switch (ack & AUX_NATIVE_REPLY_MASK) {
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case AUX_NATIVE_REPLY_ACK:
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/* I2C-over-AUX Reply field is only valid
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* when paired with AUX ACK.
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*/
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break;
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case AUX_NATIVE_REPLY_NACK:
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DRM_DEBUG_KMS("aux_ch native nack\n");
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return -EREMOTEIO;
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case AUX_NATIVE_REPLY_DEFER:
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DRM_DEBUG_KMS("aux_ch native defer\n");
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udelay(400);
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continue;
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default:
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DRM_ERROR("aux_ch invalid native reply 0x%02x\n", ack);
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return -EREMOTEIO;
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}
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switch (ack & AUX_I2C_REPLY_MASK) {
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case AUX_I2C_REPLY_ACK:
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if (mode == MODE_I2C_READ)
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*read_byte = reply[0];
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return ret;
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case AUX_I2C_REPLY_NACK:
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DRM_DEBUG_KMS("aux_i2c nack\n");
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return -EREMOTEIO;
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case AUX_I2C_REPLY_DEFER:
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DRM_DEBUG_KMS("aux_i2c defer\n");
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udelay(400);
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break;
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default:
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DRM_ERROR("aux_i2c invalid reply 0x%02x\n", ack);
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return -EREMOTEIO;
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}
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}
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DRM_DEBUG_KMS("aux i2c too many retries, giving up\n");
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return -EREMOTEIO;
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}
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/***** general DP utility functions *****/
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static u8 dp_link_status(u8 link_status[DP_LINK_STATUS_SIZE], int r)
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{
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return link_status[r - DP_LANE0_1_STATUS];
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}
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static u8 dp_get_lane_status(u8 link_status[DP_LINK_STATUS_SIZE],
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int lane)
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{
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int i = DP_LANE0_1_STATUS + (lane >> 1);
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int s = (lane & 1) * 4;
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u8 l = dp_link_status(link_status, i);
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return (l >> s) & 0xf;
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}
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static bool dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE],
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int lane_count)
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{
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int lane;
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u8 lane_status;
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for (lane = 0; lane < lane_count; lane++) {
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lane_status = dp_get_lane_status(link_status, lane);
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if ((lane_status & DP_LANE_CR_DONE) == 0)
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return false;
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}
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return true;
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}
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static bool dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE],
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int lane_count)
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{
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u8 lane_align;
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u8 lane_status;
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int lane;
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lane_align = dp_link_status(link_status,
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DP_LANE_ALIGN_STATUS_UPDATED);
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if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
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return false;
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for (lane = 0; lane < lane_count; lane++) {
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lane_status = dp_get_lane_status(link_status, lane);
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if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
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return false;
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}
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return true;
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}
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static u8 dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE],
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int lane)
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{
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int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
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int s = ((lane & 1) ?
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DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
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DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
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u8 l = dp_link_status(link_status, i);
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return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
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}
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static u8 dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE],
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int lane)
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{
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int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
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int s = ((lane & 1) ?
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DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
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DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
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u8 l = dp_link_status(link_status, i);
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return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
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}
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#define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200
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#define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPHASIS_9_5
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static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE],
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int lane_count,
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u8 train_set[4])
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{
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u8 v = 0;
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u8 p = 0;
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int lane;
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for (lane = 0; lane < lane_count; lane++) {
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u8 this_v = dp_get_adjust_request_voltage(link_status, lane);
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u8 this_p = dp_get_adjust_request_pre_emphasis(link_status, lane);
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DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
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lane,
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voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
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pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
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if (this_v > v)
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v = this_v;
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if (this_p > p)
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p = this_p;
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}
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if (v >= DP_VOLTAGE_MAX)
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v |= DP_TRAIN_MAX_SWING_REACHED;
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if (p >= DP_PRE_EMPHASIS_MAX)
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p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
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DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
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voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
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pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
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for (lane = 0; lane < 4; lane++)
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train_set[lane] = v | p;
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}
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/* convert bits per color to bits per pixel */
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/* get bpc from the EDID */
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static int convert_bpc_to_bpp(int bpc)
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{
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if (bpc == 0)
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return 24;
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else
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return bpc * 3;
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}
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/* get the max pix clock supported by the link rate and lane num */
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static int dp_get_max_dp_pix_clock(int link_rate,
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int lane_num,
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int bpp)
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{
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return (link_rate * lane_num * 8) / bpp;
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}
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static int dp_get_max_link_rate(u8 dpcd[DP_DPCD_SIZE])
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{
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switch (dpcd[DP_MAX_LINK_RATE]) {
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case DP_LINK_BW_1_62:
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default:
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return 162000;
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case DP_LINK_BW_2_7:
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return 270000;
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case DP_LINK_BW_5_4:
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return 540000;
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}
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}
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static u8 dp_get_max_lane_number(u8 dpcd[DP_DPCD_SIZE])
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{
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return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
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}
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static u8 dp_get_dp_link_rate_coded(int link_rate)
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{
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switch (link_rate) {
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case 162000:
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default:
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return DP_LINK_BW_1_62;
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case 270000:
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return DP_LINK_BW_2_7;
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case 540000:
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return DP_LINK_BW_5_4;
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}
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}
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/***** radeon specific DP functions *****/
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/* First get the min lane# when low rate is used according to pixel clock
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* (prefer low rate), second check max lane# supported by DP panel,
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* if the max lane# < low rate lane# then use max lane# instead.
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*/
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static int radeon_dp_get_dp_lane_number(struct drm_connector *connector,
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u8 dpcd[DP_DPCD_SIZE],
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int pix_clock)
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{
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int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
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int max_link_rate = dp_get_max_link_rate(dpcd);
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int max_lane_num = dp_get_max_lane_number(dpcd);
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int lane_num;
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int max_dp_pix_clock;
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for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) {
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max_dp_pix_clock = dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp);
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if (pix_clock <= max_dp_pix_clock)
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break;
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}
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return lane_num;
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}
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static int radeon_dp_get_dp_link_clock(struct drm_connector *connector,
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u8 dpcd[DP_DPCD_SIZE],
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int pix_clock)
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{
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int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
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int lane_num, max_pix_clock;
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if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
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ENCODER_OBJECT_ID_NUTMEG)
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return 270000;
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lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock);
|
|
max_pix_clock = dp_get_max_dp_pix_clock(162000, lane_num, bpp);
|
|
if (pix_clock <= max_pix_clock)
|
|
return 162000;
|
|
max_pix_clock = dp_get_max_dp_pix_clock(270000, lane_num, bpp);
|
|
if (pix_clock <= max_pix_clock)
|
|
return 270000;
|
|
if (radeon_connector_is_dp12_capable(connector)) {
|
|
max_pix_clock = dp_get_max_dp_pix_clock(540000, lane_num, bpp);
|
|
if (pix_clock <= max_pix_clock)
|
|
return 540000;
|
|
}
|
|
|
|
return dp_get_max_link_rate(dpcd);
|
|
}
|
|
|
|
static u8 radeon_dp_encoder_service(struct radeon_device *rdev,
|
|
int action, int dp_clock,
|
|
u8 ucconfig, u8 lane_num)
|
|
{
|
|
DP_ENCODER_SERVICE_PARAMETERS args;
|
|
int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
|
|
|
|
memset(&args, 0, sizeof(args));
|
|
args.ucLinkClock = dp_clock / 10;
|
|
args.ucConfig = ucconfig;
|
|
args.ucAction = action;
|
|
args.ucLaneNum = lane_num;
|
|
args.ucStatus = 0;
|
|
|
|
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
|
|
return args.ucStatus;
|
|
}
|
|
|
|
u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector)
|
|
{
|
|
struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
|
|
struct drm_device *dev = radeon_connector->base.dev;
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
|
|
return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
|
|
dig_connector->dp_i2c_bus->rec.i2c_id, 0);
|
|
}
|
|
|
|
static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector)
|
|
{
|
|
struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
|
|
u8 buf[3];
|
|
|
|
if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
|
|
return;
|
|
|
|
if (radeon_dp_aux_native_read(radeon_connector, DP_SINK_OUI, buf, 3, 0))
|
|
DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
|
|
buf[0], buf[1], buf[2]);
|
|
|
|
if (radeon_dp_aux_native_read(radeon_connector, DP_BRANCH_OUI, buf, 3, 0))
|
|
DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
|
|
buf[0], buf[1], buf[2]);
|
|
}
|
|
|
|
bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
|
|
{
|
|
struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
|
|
u8 msg[25];
|
|
int ret, i;
|
|
|
|
ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, msg, 8, 0);
|
|
if (ret > 0) {
|
|
memcpy(dig_connector->dpcd, msg, 8);
|
|
DRM_DEBUG_KMS("DPCD: ");
|
|
for (i = 0; i < 8; i++)
|
|
DRM_DEBUG_KMS("%02x ", msg[i]);
|
|
DRM_DEBUG_KMS("\n");
|
|
|
|
radeon_dp_probe_oui(radeon_connector);
|
|
|
|
return true;
|
|
}
|
|
dig_connector->dpcd[0] = 0;
|
|
return false;
|
|
}
|
|
|
|
int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
|
|
struct drm_connector *connector)
|
|
{
|
|
struct drm_device *dev = encoder->dev;
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
|
|
int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
|
|
u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector);
|
|
u8 tmp;
|
|
|
|
if (!ASIC_IS_DCE4(rdev))
|
|
return panel_mode;
|
|
|
|
if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
|
|
/* DP bridge chips */
|
|
tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP);
|
|
if (tmp & 1)
|
|
panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
|
|
else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
|
|
(dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
|
|
panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
|
|
else
|
|
panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
|
|
} else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
|
|
/* eDP */
|
|
tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP);
|
|
if (tmp & 1)
|
|
panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
|
|
}
|
|
|
|
return panel_mode;
|
|
}
|
|
|
|
void radeon_dp_set_link_config(struct drm_connector *connector,
|
|
const struct drm_display_mode *mode)
|
|
{
|
|
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
|
|
struct radeon_connector_atom_dig *dig_connector;
|
|
|
|
if (!radeon_connector->con_priv)
|
|
return;
|
|
dig_connector = radeon_connector->con_priv;
|
|
|
|
if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
|
|
(dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
|
|
dig_connector->dp_clock =
|
|
radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
|
|
dig_connector->dp_lane_count =
|
|
radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock);
|
|
}
|
|
}
|
|
|
|
int radeon_dp_mode_valid_helper(struct drm_connector *connector,
|
|
struct drm_display_mode *mode)
|
|
{
|
|
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
|
|
struct radeon_connector_atom_dig *dig_connector;
|
|
int dp_clock;
|
|
|
|
if (!radeon_connector->con_priv)
|
|
return MODE_CLOCK_HIGH;
|
|
dig_connector = radeon_connector->con_priv;
|
|
|
|
dp_clock =
|
|
radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
|
|
|
|
if ((dp_clock == 540000) &&
|
|
(!radeon_connector_is_dp12_capable(connector)))
|
|
return MODE_CLOCK_HIGH;
|
|
|
|
return MODE_OK;
|
|
}
|
|
|
|
static bool radeon_dp_get_link_status(struct radeon_connector *radeon_connector,
|
|
u8 link_status[DP_LINK_STATUS_SIZE])
|
|
{
|
|
int ret;
|
|
ret = radeon_dp_aux_native_read(radeon_connector, DP_LANE0_1_STATUS,
|
|
link_status, DP_LINK_STATUS_SIZE, 100);
|
|
if (ret <= 0) {
|
|
return false;
|
|
}
|
|
|
|
DRM_DEBUG_KMS("link status %*ph\n", 6, link_status);
|
|
return true;
|
|
}
|
|
|
|
bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector)
|
|
{
|
|
u8 link_status[DP_LINK_STATUS_SIZE];
|
|
struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
|
|
|
|
if (!radeon_dp_get_link_status(radeon_connector, link_status))
|
|
return false;
|
|
if (dp_channel_eq_ok(link_status, dig->dp_lane_count))
|
|
return false;
|
|
return true;
|
|
}
|
|
|
|
struct radeon_dp_link_train_info {
|
|
struct radeon_device *rdev;
|
|
struct drm_encoder *encoder;
|
|
struct drm_connector *connector;
|
|
struct radeon_connector *radeon_connector;
|
|
int enc_id;
|
|
int dp_clock;
|
|
int dp_lane_count;
|
|
int rd_interval;
|
|
bool tp3_supported;
|
|
u8 dpcd[8];
|
|
u8 train_set[4];
|
|
u8 link_status[DP_LINK_STATUS_SIZE];
|
|
u8 tries;
|
|
bool use_dpencoder;
|
|
};
|
|
|
|
static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info)
|
|
{
|
|
/* set the initial vs/emph on the source */
|
|
atombios_dig_transmitter_setup(dp_info->encoder,
|
|
ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
|
|
0, dp_info->train_set[0]); /* sets all lanes at once */
|
|
|
|
/* set the vs/emph on the sink */
|
|
radeon_dp_aux_native_write(dp_info->radeon_connector, DP_TRAINING_LANE0_SET,
|
|
dp_info->train_set, dp_info->dp_lane_count, 0);
|
|
}
|
|
|
|
static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp)
|
|
{
|
|
int rtp = 0;
|
|
|
|
/* set training pattern on the source */
|
|
if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) {
|
|
switch (tp) {
|
|
case DP_TRAINING_PATTERN_1:
|
|
rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1;
|
|
break;
|
|
case DP_TRAINING_PATTERN_2:
|
|
rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2;
|
|
break;
|
|
case DP_TRAINING_PATTERN_3:
|
|
rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3;
|
|
break;
|
|
}
|
|
atombios_dig_encoder_setup(dp_info->encoder, rtp, 0);
|
|
} else {
|
|
switch (tp) {
|
|
case DP_TRAINING_PATTERN_1:
|
|
rtp = 0;
|
|
break;
|
|
case DP_TRAINING_PATTERN_2:
|
|
rtp = 1;
|
|
break;
|
|
}
|
|
radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
|
|
dp_info->dp_clock, dp_info->enc_id, rtp);
|
|
}
|
|
|
|
/* enable training pattern on the sink */
|
|
radeon_write_dpcd_reg(dp_info->radeon_connector, DP_TRAINING_PATTERN_SET, tp);
|
|
}
|
|
|
|
static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)
|
|
{
|
|
struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder);
|
|
struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
|
|
u8 tmp;
|
|
|
|
/* power up the sink */
|
|
if (dp_info->dpcd[0] >= 0x11)
|
|
radeon_write_dpcd_reg(dp_info->radeon_connector,
|
|
DP_SET_POWER, DP_SET_POWER_D0);
|
|
|
|
/* possibly enable downspread on the sink */
|
|
if (dp_info->dpcd[3] & 0x1)
|
|
radeon_write_dpcd_reg(dp_info->radeon_connector,
|
|
DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);
|
|
else
|
|
radeon_write_dpcd_reg(dp_info->radeon_connector,
|
|
DP_DOWNSPREAD_CTRL, 0);
|
|
|
|
if ((dp_info->connector->connector_type == DRM_MODE_CONNECTOR_eDP) &&
|
|
(dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) {
|
|
radeon_write_dpcd_reg(dp_info->radeon_connector, DP_EDP_CONFIGURATION_SET, 1);
|
|
}
|
|
|
|
/* set the lane count on the sink */
|
|
tmp = dp_info->dp_lane_count;
|
|
if (dp_info->dpcd[DP_DPCD_REV] >= 0x11 &&
|
|
dp_info->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)
|
|
tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
|
|
radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LANE_COUNT_SET, tmp);
|
|
|
|
/* set the link rate on the sink */
|
|
tmp = dp_get_dp_link_rate_coded(dp_info->dp_clock);
|
|
radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LINK_BW_SET, tmp);
|
|
|
|
/* start training on the source */
|
|
if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
|
|
atombios_dig_encoder_setup(dp_info->encoder,
|
|
ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0);
|
|
else
|
|
radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START,
|
|
dp_info->dp_clock, dp_info->enc_id, 0);
|
|
|
|
/* disable the training pattern on the sink */
|
|
radeon_write_dpcd_reg(dp_info->radeon_connector,
|
|
DP_TRAINING_PATTERN_SET,
|
|
DP_TRAINING_PATTERN_DISABLE);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info)
|
|
{
|
|
udelay(400);
|
|
|
|
/* disable the training pattern on the sink */
|
|
radeon_write_dpcd_reg(dp_info->radeon_connector,
|
|
DP_TRAINING_PATTERN_SET,
|
|
DP_TRAINING_PATTERN_DISABLE);
|
|
|
|
/* disable the training pattern on the source */
|
|
if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
|
|
atombios_dig_encoder_setup(dp_info->encoder,
|
|
ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0);
|
|
else
|
|
radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
|
|
dp_info->dp_clock, dp_info->enc_id, 0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info)
|
|
{
|
|
bool clock_recovery;
|
|
u8 voltage;
|
|
int i;
|
|
|
|
radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);
|
|
memset(dp_info->train_set, 0, 4);
|
|
radeon_dp_update_vs_emph(dp_info);
|
|
|
|
udelay(400);
|
|
|
|
/* clock recovery loop */
|
|
clock_recovery = false;
|
|
dp_info->tries = 0;
|
|
voltage = 0xff;
|
|
while (1) {
|
|
if (dp_info->rd_interval == 0)
|
|
udelay(100);
|
|
else
|
|
mdelay(dp_info->rd_interval * 4);
|
|
|
|
if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) {
|
|
DRM_ERROR("displayport link status failed\n");
|
|
break;
|
|
}
|
|
|
|
if (dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {
|
|
clock_recovery = true;
|
|
break;
|
|
}
|
|
|
|
for (i = 0; i < dp_info->dp_lane_count; i++) {
|
|
if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
|
|
break;
|
|
}
|
|
if (i == dp_info->dp_lane_count) {
|
|
DRM_ERROR("clock recovery reached max voltage\n");
|
|
break;
|
|
}
|
|
|
|
if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
|
|
++dp_info->tries;
|
|
if (dp_info->tries == 5) {
|
|
DRM_ERROR("clock recovery tried 5 times\n");
|
|
break;
|
|
}
|
|
} else
|
|
dp_info->tries = 0;
|
|
|
|
voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
|
|
|
|
/* Compute new train_set as requested by sink */
|
|
dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
|
|
|
|
radeon_dp_update_vs_emph(dp_info);
|
|
}
|
|
if (!clock_recovery) {
|
|
DRM_ERROR("clock recovery failed\n");
|
|
return -1;
|
|
} else {
|
|
DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
|
|
dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
|
|
(dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
|
|
DP_TRAIN_PRE_EMPHASIS_SHIFT);
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info)
|
|
{
|
|
bool channel_eq;
|
|
|
|
if (dp_info->tp3_supported)
|
|
radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);
|
|
else
|
|
radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);
|
|
|
|
/* channel equalization loop */
|
|
dp_info->tries = 0;
|
|
channel_eq = false;
|
|
while (1) {
|
|
if (dp_info->rd_interval == 0)
|
|
udelay(400);
|
|
else
|
|
mdelay(dp_info->rd_interval * 4);
|
|
|
|
if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) {
|
|
DRM_ERROR("displayport link status failed\n");
|
|
break;
|
|
}
|
|
|
|
if (dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
|
|
channel_eq = true;
|
|
break;
|
|
}
|
|
|
|
/* Try 5 times */
|
|
if (dp_info->tries > 5) {
|
|
DRM_ERROR("channel eq failed: 5 tries\n");
|
|
break;
|
|
}
|
|
|
|
/* Compute new train_set as requested by sink */
|
|
dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
|
|
|
|
radeon_dp_update_vs_emph(dp_info);
|
|
dp_info->tries++;
|
|
}
|
|
|
|
if (!channel_eq) {
|
|
DRM_ERROR("channel eq failed\n");
|
|
return -1;
|
|
} else {
|
|
DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
|
|
dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
|
|
(dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
|
|
>> DP_TRAIN_PRE_EMPHASIS_SHIFT);
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
void radeon_dp_link_train(struct drm_encoder *encoder,
|
|
struct drm_connector *connector)
|
|
{
|
|
struct drm_device *dev = encoder->dev;
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
|
|
struct radeon_encoder_atom_dig *dig;
|
|
struct radeon_connector *radeon_connector;
|
|
struct radeon_connector_atom_dig *dig_connector;
|
|
struct radeon_dp_link_train_info dp_info;
|
|
int index;
|
|
u8 tmp, frev, crev;
|
|
|
|
if (!radeon_encoder->enc_priv)
|
|
return;
|
|
dig = radeon_encoder->enc_priv;
|
|
|
|
radeon_connector = to_radeon_connector(connector);
|
|
if (!radeon_connector->con_priv)
|
|
return;
|
|
dig_connector = radeon_connector->con_priv;
|
|
|
|
if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) &&
|
|
(dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP))
|
|
return;
|
|
|
|
/* DPEncoderService newer than 1.1 can't program properly the
|
|
* training pattern. When facing such version use the
|
|
* DIGXEncoderControl (X== 1 | 2)
|
|
*/
|
|
dp_info.use_dpencoder = true;
|
|
index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
|
|
if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) {
|
|
if (crev > 1) {
|
|
dp_info.use_dpencoder = false;
|
|
}
|
|
}
|
|
|
|
dp_info.enc_id = 0;
|
|
if (dig->dig_encoder)
|
|
dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
|
|
else
|
|
dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
|
|
if (dig->linkb)
|
|
dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B;
|
|
else
|
|
dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A;
|
|
|
|
dp_info.rd_interval = radeon_read_dpcd_reg(radeon_connector, DP_TRAINING_AUX_RD_INTERVAL);
|
|
tmp = radeon_read_dpcd_reg(radeon_connector, DP_MAX_LANE_COUNT);
|
|
if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))
|
|
dp_info.tp3_supported = true;
|
|
else
|
|
dp_info.tp3_supported = false;
|
|
|
|
memcpy(dp_info.dpcd, dig_connector->dpcd, 8);
|
|
dp_info.rdev = rdev;
|
|
dp_info.encoder = encoder;
|
|
dp_info.connector = connector;
|
|
dp_info.radeon_connector = radeon_connector;
|
|
dp_info.dp_lane_count = dig_connector->dp_lane_count;
|
|
dp_info.dp_clock = dig_connector->dp_clock;
|
|
|
|
if (radeon_dp_link_train_init(&dp_info))
|
|
goto done;
|
|
if (radeon_dp_link_train_cr(&dp_info))
|
|
goto done;
|
|
if (radeon_dp_link_train_ce(&dp_info))
|
|
goto done;
|
|
done:
|
|
if (radeon_dp_link_train_finish(&dp_info))
|
|
return;
|
|
}
|