1124 lines
29 KiB
C
1124 lines
29 KiB
C
/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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//#include <linux/console.h>
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#include <drm/drmP.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/radeon_drm.h>
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#include "radeon_reg.h"
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#include "radeon.h"
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#include "atom.h"
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#include "display.h"
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#include <drm/drm_pciids.h>
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int radeon_no_wb = 1;
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int radeon_modeset = -1;
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int radeon_dynclks = -1;
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int radeon_r4xx_atom = 0;
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int radeon_agpmode = 0;
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int radeon_vram_limit = 0;
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int radeon_gart_size = 512; /* default gart size */
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int radeon_benchmarking = 0;
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int radeon_testing = 0;
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int radeon_connector_table = 0;
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int radeon_tv = 1;
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int radeon_new_pll = -1;
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int radeon_dynpm = -1;
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int radeon_audio = 1;
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int radeon_hw_i2c = 0;
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int radeon_pcie_gen2 = 0;
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int radeon_disp_priority = 0;
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int irq_override = 0;
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extern display_t *rdisplay;
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void parse_cmdline(char *cmdline, videomode_t *mode, char *log, int *kms);
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int init_display(struct radeon_device *rdev, videomode_t *mode);
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int init_display_kms(struct radeon_device *rdev, videomode_t *mode);
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int get_modes(videomode_t *mode, int *count);
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int set_user_mode(videomode_t *mode);
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int r100_2D_test(struct radeon_device *rdev);
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/* Legacy VGA regions */
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#define VGA_RSRC_NONE 0x00
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#define VGA_RSRC_LEGACY_IO 0x01
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#define VGA_RSRC_LEGACY_MEM 0x02
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#define VGA_RSRC_LEGACY_MASK (VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM)
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/* Non-legacy access */
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#define VGA_RSRC_NORMAL_IO 0x04
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#define VGA_RSRC_NORMAL_MEM 0x08
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static const char radeon_family_name[][16] = {
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"R100",
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"RV100",
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"RS100",
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"RV200",
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"RS200",
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"R200",
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"RV250",
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"RS300",
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"RV280",
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"R300",
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"R350",
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"RV350",
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"RV380",
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"R420",
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"R423",
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"RV410",
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"RS400",
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"RS480",
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"RS600",
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"RS690",
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"RS740",
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"RV515",
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"R520",
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"RV530",
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"RV560",
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"RV570",
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"R580",
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"R600",
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"RV610",
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"RV630",
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"RV670",
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"RV620",
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"RV635",
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"RS780",
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"RS880",
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"RV770",
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"RV730",
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"RV710",
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"RV740",
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"CEDAR",
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"REDWOOD",
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"JUNIPER",
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"CYPRESS",
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"HEMLOCK",
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"PALM",
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"SUMO",
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"SUMO2",
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"BARTS",
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"TURKS",
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"CAICOS",
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"CAYMAN",
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"LAST",
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};
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/*
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* Clear GPU surface registers.
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*/
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void radeon_surface_init(struct radeon_device *rdev)
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{
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/* FIXME: check this out */
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if (rdev->family < CHIP_R600) {
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int i;
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for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
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radeon_clear_surface_reg(rdev, i);
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}
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/* enable surfaces */
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WREG32(RADEON_SURFACE_CNTL, 0);
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}
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}
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/*
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* GPU scratch registers helpers function.
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*/
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void radeon_scratch_init(struct radeon_device *rdev)
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{
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int i;
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/* FIXME: check this out */
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if (rdev->family < CHIP_R300) {
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rdev->scratch.num_reg = 5;
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} else {
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rdev->scratch.num_reg = 7;
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}
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rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
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for (i = 0; i < rdev->scratch.num_reg; i++) {
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rdev->scratch.free[i] = true;
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rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
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}
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}
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int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
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{
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int i;
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for (i = 0; i < rdev->scratch.num_reg; i++) {
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if (rdev->scratch.free[i]) {
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rdev->scratch.free[i] = false;
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*reg = rdev->scratch.reg[i];
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return 0;
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}
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}
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return -EINVAL;
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}
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void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
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{
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int i;
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for (i = 0; i < rdev->scratch.num_reg; i++) {
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if (rdev->scratch.reg[i] == reg) {
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rdev->scratch.free[i] = true;
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return;
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}
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}
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}
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void radeon_wb_disable(struct radeon_device *rdev)
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{
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int r;
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if (rdev->wb.wb_obj) {
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r = radeon_bo_reserve(rdev->wb.wb_obj, false);
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if (unlikely(r != 0))
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return;
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radeon_bo_kunmap(rdev->wb.wb_obj);
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radeon_bo_unpin(rdev->wb.wb_obj);
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radeon_bo_unreserve(rdev->wb.wb_obj);
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}
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rdev->wb.enabled = false;
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}
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void radeon_wb_fini(struct radeon_device *rdev)
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{
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radeon_wb_disable(rdev);
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if (rdev->wb.wb_obj) {
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radeon_bo_unref(&rdev->wb.wb_obj);
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rdev->wb.wb = NULL;
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rdev->wb.wb_obj = NULL;
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}
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}
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int radeon_wb_init(struct radeon_device *rdev)
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{
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int r;
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if (rdev->wb.wb_obj == NULL) {
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r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
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RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj);
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if (r) {
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dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
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return r;
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}
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}
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r = radeon_bo_reserve(rdev->wb.wb_obj, false);
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if (unlikely(r != 0)) {
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radeon_wb_fini(rdev);
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return r;
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}
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r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
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&rdev->wb.gpu_addr);
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if (r) {
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radeon_bo_unreserve(rdev->wb.wb_obj);
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dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
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radeon_wb_fini(rdev);
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return r;
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}
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r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
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radeon_bo_unreserve(rdev->wb.wb_obj);
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if (r) {
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dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
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radeon_wb_fini(rdev);
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return r;
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}
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/* clear wb memory */
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memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE);
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/* disable event_write fences */
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rdev->wb.use_event = false;
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/* disabled via module param */
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if (radeon_no_wb == 1)
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rdev->wb.enabled = false;
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else {
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/* often unreliable on AGP */
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// if (rdev->flags & RADEON_IS_AGP) {
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// rdev->wb.enabled = false;
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// } else {
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rdev->wb.enabled = true;
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/* event_write fences are only available on r600+ */
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if (rdev->family >= CHIP_R600)
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rdev->wb.use_event = true;
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// }
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}
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/* always use writeback/events on NI */
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if (ASIC_IS_DCE5(rdev)) {
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rdev->wb.enabled = true;
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rdev->wb.use_event = true;
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}
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dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");
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return 0;
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}
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/**
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* radeon_vram_location - try to find VRAM location
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* @rdev: radeon device structure holding all necessary informations
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* @mc: memory controller structure holding memory informations
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* @base: base address at which to put VRAM
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*
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* Function will place try to place VRAM at base address provided
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* as parameter (which is so far either PCI aperture address or
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* for IGP TOM base address).
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*
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* If there is not enough space to fit the unvisible VRAM in the 32bits
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* address space then we limit the VRAM size to the aperture.
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*
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* If we are using AGP and if the AGP aperture doesn't allow us to have
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* room for all the VRAM than we restrict the VRAM to the PCI aperture
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* size and print a warning.
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*
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* This function will never fails, worst case are limiting VRAM.
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*
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* Note: GTT start, end, size should be initialized before calling this
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* function on AGP platform.
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*
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* Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
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* this shouldn't be a problem as we are using the PCI aperture as a reference.
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* Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
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* not IGP.
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*
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* Note: we use mc_vram_size as on some board we need to program the mc to
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* cover the whole aperture even if VRAM size is inferior to aperture size
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* Novell bug 204882 + along with lots of ubuntu ones
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*
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* Note: when limiting vram it's safe to overwritte real_vram_size because
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* we are not in case where real_vram_size is inferior to mc_vram_size (ie
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* note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
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* ones)
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*
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* Note: IGP TOM addr should be the same as the aperture addr, we don't
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* explicitly check for that thought.
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*
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* FIXME: when reducing VRAM size align new size on power of 2.
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*/
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void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
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{
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mc->vram_start = base;
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if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) {
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dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
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mc->real_vram_size = mc->aper_size;
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mc->mc_vram_size = mc->aper_size;
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}
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mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
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if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
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dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
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mc->real_vram_size = mc->aper_size;
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mc->mc_vram_size = mc->aper_size;
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}
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mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
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dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
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mc->mc_vram_size >> 20, mc->vram_start,
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mc->vram_end, mc->real_vram_size >> 20);
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}
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/**
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* radeon_gtt_location - try to find GTT location
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* @rdev: radeon device structure holding all necessary informations
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* @mc: memory controller structure holding memory informations
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*
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* Function will place try to place GTT before or after VRAM.
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*
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* If GTT size is bigger than space left then we ajust GTT size.
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* Thus function will never fails.
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*
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* FIXME: when reducing GTT size align new size on power of 2.
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*/
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void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
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{
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u64 size_af, size_bf;
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size_af = ((0xFFFFFFFF - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
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size_bf = mc->vram_start & ~mc->gtt_base_align;
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if (size_bf > size_af) {
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if (mc->gtt_size > size_bf) {
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dev_warn(rdev->dev, "limiting GTT\n");
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mc->gtt_size = size_bf;
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}
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mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
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} else {
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if (mc->gtt_size > size_af) {
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dev_warn(rdev->dev, "limiting GTT\n");
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mc->gtt_size = size_af;
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}
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mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
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}
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mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
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dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
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mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
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}
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/*
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* GPU helpers function.
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*/
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bool radeon_card_posted(struct radeon_device *rdev)
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{
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uint32_t reg;
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/* first check CRTCs */
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if (ASIC_IS_DCE41(rdev)) {
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reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
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RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
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if (reg & EVERGREEN_CRTC_MASTER_EN)
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return true;
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} else if (ASIC_IS_DCE4(rdev)) {
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reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
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RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
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RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
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RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
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RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
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RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
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if (reg & EVERGREEN_CRTC_MASTER_EN)
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return true;
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} else if (ASIC_IS_AVIVO(rdev)) {
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reg = RREG32(AVIVO_D1CRTC_CONTROL) |
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RREG32(AVIVO_D2CRTC_CONTROL);
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if (reg & AVIVO_CRTC_EN) {
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return true;
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}
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} else {
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reg = RREG32(RADEON_CRTC_GEN_CNTL) |
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RREG32(RADEON_CRTC2_GEN_CNTL);
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if (reg & RADEON_CRTC_EN) {
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return true;
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}
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}
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/* then check MEM_SIZE, in case the crtcs are off */
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if (rdev->family >= CHIP_R600)
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reg = RREG32(R600_CONFIG_MEMSIZE);
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else
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reg = RREG32(RADEON_CONFIG_MEMSIZE);
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if (reg)
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return true;
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return false;
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}
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void radeon_update_bandwidth_info(struct radeon_device *rdev)
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{
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fixed20_12 a;
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u32 sclk = rdev->pm.current_sclk;
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u32 mclk = rdev->pm.current_mclk;
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/* sclk/mclk in Mhz */
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a.full = dfixed_const(100);
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rdev->pm.sclk.full = dfixed_const(sclk);
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rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
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rdev->pm.mclk.full = dfixed_const(mclk);
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rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
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if (rdev->flags & RADEON_IS_IGP) {
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a.full = dfixed_const(16);
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/* core_bandwidth = sclk(Mhz) * 16 */
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rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
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}
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}
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bool radeon_boot_test_post_card(struct radeon_device *rdev)
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{
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if (radeon_card_posted(rdev))
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return true;
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if (rdev->bios) {
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DRM_INFO("GPU not posted. posting now...\n");
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if (rdev->is_atom_bios)
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atom_asic_init(rdev->mode_info.atom_context);
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else
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radeon_combios_asic_init(rdev->ddev);
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return true;
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} else {
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dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
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return false;
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}
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}
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int radeon_dummy_page_init(struct radeon_device *rdev)
|
|
{
|
|
if (rdev->dummy_page.page)
|
|
return 0;
|
|
rdev->dummy_page.page = AllocPage();
|
|
if (rdev->dummy_page.page == NULL)
|
|
return -ENOMEM;
|
|
rdev->dummy_page.addr = MapIoMem(rdev->dummy_page.page, 4096, 5);
|
|
if (!rdev->dummy_page.addr) {
|
|
// __free_page(rdev->dummy_page.page);
|
|
rdev->dummy_page.page = NULL;
|
|
return -ENOMEM;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
void radeon_dummy_page_fini(struct radeon_device *rdev)
|
|
{
|
|
if (rdev->dummy_page.page == NULL)
|
|
return;
|
|
KernelFree(rdev->dummy_page.addr);
|
|
rdev->dummy_page.page = NULL;
|
|
}
|
|
|
|
|
|
/* ATOM accessor methods */
|
|
static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
|
|
{
|
|
struct radeon_device *rdev = info->dev->dev_private;
|
|
uint32_t r;
|
|
|
|
r = rdev->pll_rreg(rdev, reg);
|
|
return r;
|
|
}
|
|
|
|
static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
|
|
{
|
|
struct radeon_device *rdev = info->dev->dev_private;
|
|
|
|
rdev->pll_wreg(rdev, reg, val);
|
|
}
|
|
|
|
static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
|
|
{
|
|
struct radeon_device *rdev = info->dev->dev_private;
|
|
uint32_t r;
|
|
|
|
r = rdev->mc_rreg(rdev, reg);
|
|
return r;
|
|
}
|
|
|
|
static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
|
|
{
|
|
struct radeon_device *rdev = info->dev->dev_private;
|
|
|
|
rdev->mc_wreg(rdev, reg, val);
|
|
}
|
|
|
|
static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
|
|
{
|
|
struct radeon_device *rdev = info->dev->dev_private;
|
|
|
|
WREG32(reg*4, val);
|
|
}
|
|
|
|
static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
|
|
{
|
|
struct radeon_device *rdev = info->dev->dev_private;
|
|
uint32_t r;
|
|
|
|
r = RREG32(reg*4);
|
|
return r;
|
|
}
|
|
|
|
static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
|
|
{
|
|
struct radeon_device *rdev = info->dev->dev_private;
|
|
|
|
WREG32_IO(reg*4, val);
|
|
}
|
|
|
|
static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
|
|
{
|
|
struct radeon_device *rdev = info->dev->dev_private;
|
|
uint32_t r;
|
|
|
|
r = RREG32_IO(reg*4);
|
|
return r;
|
|
}
|
|
|
|
int radeon_atombios_init(struct radeon_device *rdev)
|
|
{
|
|
struct card_info *atom_card_info =
|
|
kzalloc(sizeof(struct card_info), GFP_KERNEL);
|
|
|
|
if (!atom_card_info)
|
|
return -ENOMEM;
|
|
|
|
rdev->mode_info.atom_card_info = atom_card_info;
|
|
atom_card_info->dev = rdev->ddev;
|
|
atom_card_info->reg_read = cail_reg_read;
|
|
atom_card_info->reg_write = cail_reg_write;
|
|
/* needed for iio ops */
|
|
if (rdev->rio_mem) {
|
|
atom_card_info->ioreg_read = cail_ioreg_read;
|
|
atom_card_info->ioreg_write = cail_ioreg_write;
|
|
} else {
|
|
DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
|
|
atom_card_info->ioreg_read = cail_reg_read;
|
|
atom_card_info->ioreg_write = cail_reg_write;
|
|
}
|
|
atom_card_info->mc_read = cail_mc_read;
|
|
atom_card_info->mc_write = cail_mc_write;
|
|
atom_card_info->pll_read = cail_pll_read;
|
|
atom_card_info->pll_write = cail_pll_write;
|
|
|
|
rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
|
|
mutex_init(&rdev->mode_info.atom_context->mutex);
|
|
radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
|
|
atom_allocate_fb_scratch(rdev->mode_info.atom_context);
|
|
return 0;
|
|
}
|
|
|
|
void radeon_atombios_fini(struct radeon_device *rdev)
|
|
{
|
|
if (rdev->mode_info.atom_context) {
|
|
kfree(rdev->mode_info.atom_context->scratch);
|
|
kfree(rdev->mode_info.atom_context);
|
|
}
|
|
kfree(rdev->mode_info.atom_card_info);
|
|
}
|
|
|
|
int radeon_combios_init(struct radeon_device *rdev)
|
|
{
|
|
radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
|
|
return 0;
|
|
}
|
|
|
|
void radeon_combios_fini(struct radeon_device *rdev)
|
|
{
|
|
}
|
|
|
|
/* if we get transitioned to only one device, tak VGA back */
|
|
static unsigned int radeon_vga_set_decode(void *cookie, bool state)
|
|
{
|
|
struct radeon_device *rdev = cookie;
|
|
radeon_vga_set_state(rdev, state);
|
|
if (state)
|
|
return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
|
|
VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
|
|
else
|
|
return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
|
|
}
|
|
|
|
void radeon_check_arguments(struct radeon_device *rdev)
|
|
{
|
|
/* vramlimit must be a power of two */
|
|
switch (radeon_vram_limit) {
|
|
case 0:
|
|
case 4:
|
|
case 8:
|
|
case 16:
|
|
case 32:
|
|
case 64:
|
|
case 128:
|
|
case 256:
|
|
case 512:
|
|
case 1024:
|
|
case 2048:
|
|
case 4096:
|
|
break;
|
|
default:
|
|
dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
|
|
radeon_vram_limit);
|
|
radeon_vram_limit = 0;
|
|
break;
|
|
}
|
|
radeon_vram_limit = radeon_vram_limit << 20;
|
|
/* gtt size must be power of two and greater or equal to 32M */
|
|
switch (radeon_gart_size) {
|
|
case 4:
|
|
case 8:
|
|
case 16:
|
|
dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n",
|
|
radeon_gart_size);
|
|
radeon_gart_size = 512;
|
|
break;
|
|
case 32:
|
|
case 64:
|
|
case 128:
|
|
case 256:
|
|
case 512:
|
|
case 1024:
|
|
case 2048:
|
|
case 4096:
|
|
break;
|
|
default:
|
|
dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
|
|
radeon_gart_size);
|
|
radeon_gart_size = 512;
|
|
break;
|
|
}
|
|
rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
|
|
/* AGP mode can only be -1, 1, 2, 4, 8 */
|
|
switch (radeon_agpmode) {
|
|
case -1:
|
|
case 0:
|
|
case 1:
|
|
case 2:
|
|
case 4:
|
|
case 8:
|
|
break;
|
|
default:
|
|
dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
|
|
"-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
|
|
radeon_agpmode = 0;
|
|
break;
|
|
}
|
|
}
|
|
|
|
int radeon_device_init(struct radeon_device *rdev,
|
|
struct drm_device *ddev,
|
|
struct pci_dev *pdev,
|
|
uint32_t flags)
|
|
{
|
|
int r, i;
|
|
int dma_bits;
|
|
|
|
rdev->shutdown = false;
|
|
rdev->ddev = ddev;
|
|
rdev->pdev = pdev;
|
|
rdev->flags = flags;
|
|
rdev->family = flags & RADEON_FAMILY_MASK;
|
|
rdev->is_atom_bios = false;
|
|
rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
|
|
rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
|
|
rdev->gpu_lockup = false;
|
|
rdev->accel_working = false;
|
|
|
|
DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X).\n",
|
|
radeon_family_name[rdev->family], pdev->vendor, pdev->device);
|
|
|
|
/* mutex initialization are all done here so we
|
|
* can recall function without having locking issues */
|
|
mutex_init(&rdev->cs_mutex);
|
|
mutex_init(&rdev->ib_pool.mutex);
|
|
mutex_init(&rdev->cp.mutex);
|
|
mutex_init(&rdev->dc_hw_i2c_mutex);
|
|
if (rdev->family >= CHIP_R600)
|
|
spin_lock_init(&rdev->ih.lock);
|
|
mutex_init(&rdev->gem.mutex);
|
|
mutex_init(&rdev->pm.mutex);
|
|
mutex_init(&rdev->vram_mutex);
|
|
rwlock_init(&rdev->fence_drv.lock);
|
|
INIT_LIST_HEAD(&rdev->gem.objects);
|
|
|
|
/* Set asic functions */
|
|
r = radeon_asic_init(rdev);
|
|
if (r)
|
|
return r;
|
|
radeon_check_arguments(rdev);
|
|
|
|
/* all of the newer IGP chips have an internal gart
|
|
* However some rs4xx report as AGP, so remove that here.
|
|
*/
|
|
if ((rdev->family >= CHIP_RS400) &&
|
|
(rdev->flags & RADEON_IS_IGP)) {
|
|
rdev->flags &= ~RADEON_IS_AGP;
|
|
}
|
|
|
|
if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
|
|
radeon_agp_disable(rdev);
|
|
}
|
|
|
|
/* set DMA mask + need_dma32 flags.
|
|
* PCIE - can handle 40-bits.
|
|
* IGP - can handle 40-bits (in theory)
|
|
* AGP - generally dma32 is safest
|
|
* PCI - only dma32
|
|
*/
|
|
rdev->need_dma32 = false;
|
|
if (rdev->flags & RADEON_IS_AGP)
|
|
rdev->need_dma32 = true;
|
|
if (rdev->flags & RADEON_IS_PCI)
|
|
rdev->need_dma32 = true;
|
|
|
|
dma_bits = rdev->need_dma32 ? 32 : 40;
|
|
r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
|
|
if (r) {
|
|
rdev->need_dma32 = true;
|
|
printk(KERN_WARNING "radeon: No suitable DMA available.\n");
|
|
}
|
|
|
|
/* Registers mapping */
|
|
/* TODO: block userspace mapping of io register */
|
|
rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
|
|
rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
|
|
|
|
rdev->rmmio = (void*)MapIoMem(rdev->rmmio_base, rdev->rmmio_size,
|
|
PG_SW+PG_NOCACHE);
|
|
|
|
if (rdev->rmmio == NULL) {
|
|
return -ENOMEM;
|
|
}
|
|
DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
|
|
DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
|
|
|
|
r = radeon_init(rdev);
|
|
if (r)
|
|
return r;
|
|
|
|
if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
|
|
/* Acceleration not working on AGP card try again
|
|
* with fallback to PCI or PCIE GART
|
|
*/
|
|
radeon_asic_reset(rdev);
|
|
radeon_fini(rdev);
|
|
radeon_agp_disable(rdev);
|
|
r = radeon_init(rdev);
|
|
if (r)
|
|
return r;
|
|
}
|
|
// if (radeon_testing) {
|
|
// radeon_test_moves(rdev);
|
|
// }
|
|
if (radeon_benchmarking) {
|
|
radeon_benchmark(rdev);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
|
|
/*
|
|
* Driver load/unload
|
|
*/
|
|
int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
|
|
{
|
|
struct radeon_device *rdev;
|
|
int r;
|
|
|
|
ENTER();
|
|
|
|
rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
|
|
if (rdev == NULL) {
|
|
return -ENOMEM;
|
|
};
|
|
|
|
dev->dev_private = (void *)rdev;
|
|
|
|
/* update BUS flag */
|
|
if (drm_device_is_agp(dev)) {
|
|
flags |= RADEON_IS_AGP;
|
|
} else if (drm_device_is_pcie(dev)) {
|
|
flags |= RADEON_IS_PCIE;
|
|
} else {
|
|
flags |= RADEON_IS_PCI;
|
|
}
|
|
|
|
/* radeon_device_init should report only fatal error
|
|
* like memory allocation failure or iomapping failure,
|
|
* or memory manager initialization failure, it must
|
|
* properly initialize the GPU MC controller and permit
|
|
* VRAM allocation
|
|
*/
|
|
r = radeon_device_init(rdev, dev, dev->pdev, flags);
|
|
if (r) {
|
|
DRM_ERROR("Fatal error while trying to initialize radeon.\n");
|
|
return r;
|
|
}
|
|
/* Again modeset_init should fail only on fatal error
|
|
* otherwise it should provide enough functionalities
|
|
* for shadowfb to run
|
|
*/
|
|
if( radeon_modeset )
|
|
{
|
|
r = radeon_modeset_init(rdev);
|
|
if (r) {
|
|
return r;
|
|
}
|
|
};
|
|
return 0;
|
|
}
|
|
|
|
videomode_t usermode;
|
|
|
|
|
|
int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|
{
|
|
static struct drm_device *dev;
|
|
int ret;
|
|
|
|
ENTER();
|
|
|
|
dev = kzalloc(sizeof(*dev), 0);
|
|
if (!dev)
|
|
return -ENOMEM;
|
|
|
|
// ret = pci_enable_device(pdev);
|
|
// if (ret)
|
|
// goto err_g1;
|
|
|
|
// pci_set_master(pdev);
|
|
|
|
// if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) {
|
|
// printk(KERN_ERR "DRM: Fill_in_dev failed.\n");
|
|
// goto err_g2;
|
|
// }
|
|
|
|
dev->pdev = pdev;
|
|
dev->pci_device = pdev->device;
|
|
dev->pci_vendor = pdev->vendor;
|
|
|
|
INIT_LIST_HEAD(&dev->filelist);
|
|
INIT_LIST_HEAD(&dev->ctxlist);
|
|
INIT_LIST_HEAD(&dev->vmalist);
|
|
INIT_LIST_HEAD(&dev->maplist);
|
|
|
|
spin_lock_init(&dev->count_lock);
|
|
mutex_init(&dev->struct_mutex);
|
|
mutex_init(&dev->ctxlist_mutex);
|
|
|
|
|
|
ret = radeon_driver_load_kms(dev, ent->driver_data );
|
|
if (ret)
|
|
goto err_g4;
|
|
|
|
if( radeon_modeset )
|
|
init_display_kms(dev->dev_private, &usermode);
|
|
else
|
|
init_display(dev->dev_private, &usermode);
|
|
|
|
|
|
uint32_t route0 = PciRead32(0, 31<<3, 0x60);
|
|
|
|
uint32_t route1 = PciRead32(0, 31<<3, 0x68);
|
|
|
|
uint8_t elcr0 = in8(0x4D0);
|
|
uint8_t elcr1 = in8(0x4D1);
|
|
|
|
dbgprintf("pci route: %x %x elcr: %x %x\n", route0, route1, elcr0, elcr1);
|
|
|
|
LEAVE();
|
|
|
|
return 0;
|
|
|
|
err_g4:
|
|
// drm_put_minor(&dev->primary);
|
|
//err_g3:
|
|
// if (drm_core_check_feature(dev, DRIVER_MODESET))
|
|
// drm_put_minor(&dev->control);
|
|
//err_g2:
|
|
// pci_disable_device(pdev);
|
|
//err_g1:
|
|
free(dev);
|
|
|
|
LEAVE();
|
|
|
|
return ret;
|
|
}
|
|
|
|
resource_size_t drm_get_resource_start(struct drm_device *dev, unsigned int resource)
|
|
{
|
|
return pci_resource_start(dev->pdev, resource);
|
|
}
|
|
|
|
resource_size_t drm_get_resource_len(struct drm_device *dev, unsigned int resource)
|
|
{
|
|
return pci_resource_len(dev->pdev, resource);
|
|
}
|
|
|
|
|
|
uint32_t __div64_32(uint64_t *n, uint32_t base)
|
|
{
|
|
uint64_t rem = *n;
|
|
uint64_t b = base;
|
|
uint64_t res, d = 1;
|
|
uint32_t high = rem >> 32;
|
|
|
|
/* Reduce the thing a bit first */
|
|
res = 0;
|
|
if (high >= base) {
|
|
high /= base;
|
|
res = (uint64_t) high << 32;
|
|
rem -= (uint64_t) (high*base) << 32;
|
|
}
|
|
|
|
while ((int64_t)b > 0 && b < rem) {
|
|
b = b+b;
|
|
d = d+d;
|
|
}
|
|
|
|
do {
|
|
if (rem >= b) {
|
|
rem -= b;
|
|
res += d;
|
|
}
|
|
b >>= 1;
|
|
d >>= 1;
|
|
} while (d);
|
|
|
|
*n = res;
|
|
return rem;
|
|
}
|
|
|
|
|
|
static struct pci_device_id pciidlist[] = {
|
|
radeon_PCI_IDS
|
|
};
|
|
|
|
|
|
#define API_VERSION 0x01000100
|
|
|
|
#define SRV_GETVERSION 0
|
|
#define SRV_ENUM_MODES 1
|
|
#define SRV_SET_MODE 2
|
|
|
|
#define SRV_CREATE_VIDEO 9
|
|
#define SRV_BLIT_VIDEO 10
|
|
#define SRV_CREATE_BITMAP 11
|
|
|
|
|
|
int r600_video_blit(uint64_t src_offset, int x, int y,
|
|
int w, int h, int pitch);
|
|
|
|
#define check_input(size) \
|
|
if( unlikely((inp==NULL)||(io->inp_size != (size))) ) \
|
|
break;
|
|
|
|
#define check_output(size) \
|
|
if( unlikely((outp==NULL)||(io->out_size != (size))) ) \
|
|
break;
|
|
|
|
int _stdcall display_handler(ioctl_t *io)
|
|
{
|
|
int retval = -1;
|
|
u32_t *inp;
|
|
u32_t *outp;
|
|
|
|
inp = io->input;
|
|
outp = io->output;
|
|
|
|
switch(io->io_code)
|
|
{
|
|
case SRV_GETVERSION:
|
|
check_output(4);
|
|
*outp = API_VERSION;
|
|
retval = 0;
|
|
break;
|
|
|
|
case SRV_ENUM_MODES:
|
|
dbgprintf("SRV_ENUM_MODES inp %x inp_size %x out_size %x\n",
|
|
inp, io->inp_size, io->out_size );
|
|
check_output(4);
|
|
check_input(*outp * sizeof(videomode_t));
|
|
if( radeon_modeset)
|
|
retval = get_modes((videomode_t*)inp, outp);
|
|
break;
|
|
|
|
case SRV_SET_MODE:
|
|
dbgprintf("SRV_SET_MODE inp %x inp_size %x\n",
|
|
inp, io->inp_size);
|
|
check_input(sizeof(videomode_t));
|
|
if( radeon_modeset )
|
|
retval = set_user_mode((videomode_t*)inp);
|
|
break;
|
|
|
|
case SRV_CREATE_VIDEO:
|
|
retval = r600_create_video(inp[0], inp[1], outp);
|
|
break;
|
|
|
|
case SRV_BLIT_VIDEO:
|
|
r600_video_blit( ((uint64_t*)inp)[0], inp[2], inp[3],
|
|
inp[4], inp[5], inp[6]);
|
|
|
|
retval = 0;
|
|
break;
|
|
|
|
case SRV_CREATE_BITMAP:
|
|
check_input(8);
|
|
check_output(4);
|
|
retval = create_bitmap(outp, inp[0], inp[1]);
|
|
break;
|
|
|
|
};
|
|
|
|
return retval;
|
|
}
|
|
|
|
static char log[256];
|
|
static pci_dev_t device;
|
|
|
|
u32_t drvEntry(int action, char *cmdline)
|
|
{
|
|
struct radeon_device *rdev = NULL;
|
|
|
|
struct pci_device_id *ent;
|
|
|
|
int err;
|
|
u32_t retval = 0;
|
|
|
|
if(action != 1)
|
|
return 0;
|
|
|
|
if( GetService("DISPLAY") != 0 )
|
|
return 0;
|
|
|
|
if( cmdline && *cmdline )
|
|
parse_cmdline(cmdline, &usermode, log, &radeon_modeset);
|
|
|
|
if(!dbg_open(log))
|
|
{
|
|
strcpy(log, "/RD/1/DRIVERS/atikms.log");
|
|
|
|
if(!dbg_open(log))
|
|
{
|
|
printf("Can't open %s\nExit\n", log);
|
|
return 0;
|
|
};
|
|
}
|
|
dbgprintf("Radeon RC11 cmdline %s\n", cmdline);
|
|
|
|
enum_pci_devices();
|
|
|
|
ent = find_pci_device(&device, pciidlist);
|
|
|
|
if( unlikely(ent == NULL) )
|
|
{
|
|
dbgprintf("device not found\n");
|
|
return 0;
|
|
};
|
|
|
|
dbgprintf("device %x:%x\n", device.pci_dev.vendor,
|
|
device.pci_dev.device);
|
|
|
|
err = drm_get_dev(&device.pci_dev, ent);
|
|
|
|
rdev = rdisplay->ddev->dev_private;
|
|
|
|
err = RegService("DISPLAY", display_handler);
|
|
|
|
if( err != 0)
|
|
dbgprintf("Set DISPLAY handler\n");
|
|
|
|
return err;
|
|
};
|
|
|
|
void drm_vblank_post_modeset(struct drm_device *dev, int crtc)
|
|
{};
|
|
|
|
void drm_vblank_pre_modeset(struct drm_device *dev, int crtc)
|
|
{};
|
|
|