288 lines
13 KiB
PHP
288 lines
13 KiB
PHP
; Vendor ids
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INTEL_VID = 0x8086
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SIS_VID = 0x1039
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NVIDIA_VID = 0x10DE
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AMD_VID = 0x1022
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; Device ids
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ICH_DID = 0x2415
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ICH0_DID = 0x2425
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ICH2_DID = 0x2445
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ICH3_DID = 0x2485
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ICH4_DID = 0x24C5
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ICH5_DID = 0x24D5
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MX440_DID = 0x7195
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SI7012_DID = 0x7012
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NFORCE_DID = 0x01B1
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NFORCE2_DID = 0x006A
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AMD8111_DID = 0x764D
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AMD768_DID = 0x7445
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NAMBAR_REG = 0x10 ; native audio mixer BAR
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NAM_SIZE = 256 ; 256 bytes required.
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NABMBAR_REG = 0x14 ; native audio bus mastering BAR
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NABM_SIZE = 64 ; 64 bytes
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IRQ_REG = 0x3c ; IRQ holder for PCI
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INT_REG = 0x3d ; INT pin
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ICH4_CFG_REG = 0x41 ; ICH4 config register
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; BUS master registers, accessed via NABMBAR+offset
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; ICH supports 3 different types of register sets for three types of things
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; it can do, thus:
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;
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; PCM in (for recording) aka PI
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; PCM out (for playback) aka PO
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; MIC in (for recording) aka MC
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PI_BDBAR_REG = 0 ; PCM in buffer descriptor BAR
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PO_BDBAR_REG = 10h ; PCM out buffer descriptor BAR
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MC_BDBAR_REG = 20h ; MIC in buffer descriptor BAR
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; each buffer descriptor BAR holds a pointer which has entries to the buffer
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; contents of the .WAV file we're going to play. Each entry is 8 bytes long
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; (more on that later) and can contain 32 entries total, so each BAR is
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; 256 bytes in length, thus:
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BDL_SIZE = 32*8 ; Buffer Descriptor List size
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INDEX_MASK = 31 ; indexes must be 0-31
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PI_CIV_REG = 4 ; PCM in current Index value (RO)
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PO_CIV_REG = 14h ; PCM out current Index value (RO)
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MC_CIV_REG = 24h ; MIC in current Index value (RO)
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;8bit read only
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; each current index value is simply a pointer showing us which buffer
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; (0-31) the codec is currently processing. Once this counter hits 31, it
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; wraps back to 0.
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; this can be handy to know, as once it hits 31, we're almost out of data to
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; play back or room to record!
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PI_LVI_REG = 5 ; PCM in Last Valid Index
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PO_LVI_REG = 15h ; PCM out Last Valid Index
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MC_LVI_REG = 25h ; MIC in Last Valid Index
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;8bit read/write
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; The Last Valid Index is a number (0-31) to let the codec know what buffer
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; number to stop on after processing. It could be very nasty to play audio
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; from buffers that aren't filled with the audio we want to play.
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PI_SR_REG = 6 ; PCM in Status register
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PO_SR_REG = 16h ; PCM out Status register
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MC_SR_REG = 26h ; MIC in Status register
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;16bit read/write
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; status registers. Bitfields follow:
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FIFO_ERR = BIT4 ; FIFO Over/Underrun W1TC.
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BCIS = BIT3 ; buffer completion interrupt status.
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; Set whenever the last sample in ANY
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; buffer is finished. Bit is only
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; set when the Interrupt on Complete
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; (BIT4 of control reg) is set.
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LVBCI = BIT2 ; Set whenever the codec has processed
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; the last buffer in the buffer list.
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; Will fire an interrupt if IOC bit is
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; set. Probably set after the last
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; sample in the last buffer is
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; processed. W1TC
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CELV = BIT1 ; Current buffer == last valid.
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; Bit is RO and remains set until LVI is
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; cleared. Probably set up the start
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; of processing for the last buffer.
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DCH = BIT0 ; DMA controller halted.
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; set whenever audio stream is stopped
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; or something else goes wrong.
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PI_PICB_REG = 8 ; PCM in position in current buffer(RO)
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PO_PICB_REG = 18h ; PCM out position in current buffer(RO)
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MC_PICB_REG = 28h ; MIC in position in current buffer (RO)
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;16bit read only
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; position in current buffer regs show the number of dwords left to be
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; processed in the current buffer.
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;
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PI_PIV_REG = 0ah ; PCM in Prefected index value
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PO_PIV_REG = 1ah ; PCM out Prefected index value
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MC_PIV_REG = 2ah ; MIC in Prefected index value
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;8bit, read only
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; Prefetched index value register.
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; tells which buffer number (0-31) has be prefetched. I'd imagine this
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; value follows the current index value fairly closely. (CIV+1)
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;
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PI_CR_REG = 0bh ; PCM in Control Register
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PO_CR_REG = 1bh ; PCM out Control Register
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MC_CR_REG = 2bh ; MIC in Control Register
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; 8bit
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; Control register *MUST* only be accessed as an 8bit value.
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; Control register. See bitfields below.
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;
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IOCE = BIT4 ; interrupt on complete enable.
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; set this bit if you want an intrtpt
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; to fire whenever LVBCI is set.
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FEIFE = BIT3 ; set if you want an interrupt to fire
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; whenever there is a FIFO (over or
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; under) error.
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LVBIE = BIT2 ; last valid buffer interrupt enable.
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; set if you want an interrupt to fire
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; whenever the completion of the last
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; valid buffer.
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RR = BIT1 ; reset registers. Nukes all regs
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; except bits 4:2 of this register.
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; Only set this bit if BIT 0 is 0
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RPBM = BIT0 ; Run/Pause
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; set this bit to start the codec!
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GLOB_CNT_REG = 2ch ; Global control register
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SEC_RES_EN = BIT5 ; secondary codec resume event
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; interrupt enable. Not used here.
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PRI_RES_EN = BIT4 ; ditto for primary. Not used here.
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ACLINK_OFF = BIT3 ; Turn off the AC97 link
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ACWARM_RESET = BIT2 ; Awaken the AC97 link from sleep.
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; registers preserved, bit self clears
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ACCOLD_RESET = BIT1 ; Reset everything in the AC97 and
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; reset all registers. Not self clearin
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;g
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GPIIE = BIT0 ; GPI Interrupt enable.
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; set if you want an interrupt to
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; fire upon ANY of the bits in the
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; GPI (general pursose inputs?) not used
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;.
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GLOB_STS_REG = 30h ; Global Status register (RO)
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MD3 = BIT17 ; modem powerdown status (yawn)
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AD3 = BIT16 ; Audio powerdown status (yawn)
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RD_COMPLETE_STS = BIT15 ; Codec read timed out. 0=normal
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BIT3SLOT12 = BIT14 ; shadowed status of bit 3 in slot 12
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BIT2SLOT12 = BIT13 ; shadowed status of bit 2 in slot 12
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BIT1SLOT12 = BIT12 ; shadowed status of bit 1 in slot 12
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SEC_RESUME_STS = BIT11 ; secondary codec has resumed (and irqed)
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PRI_RESUME_STS = BIT10 ; primary codec has resumed (and irqed)
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SEC_CODEC_RDY = BIT9 ; secondary codec is ready for action
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PRI_CODEC_RDY = BIT8 ; Primary codec is ready for action
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; software must check these bits before
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; starting the codec!
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MIC_IN_IRQ = BIT7 ; MIC in caused an interrupt
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PCM_OUT_IRQ = BIT6 ; One of the PCM out channels IRQed
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PCM_IN_IRQ = BIT5 ; One of the PCM in channels IRQed
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MODEM_OUT_IRQ = BIT2 ; modem out channel IRQed
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MODEM_IN_IRQ = BIT1 ; modem in channel IRQed
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GPI_STS_CHANGE = BIT0 ; set whenever GPI's have changed.
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; BIT0 of slot 12 also reflects this.
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ACC_SEMA_REG = 34h ; Codec write semiphore register
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CODEC_BUSY = BIT0 ; codec register I/O is happening
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; self clearing
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;
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; Buffer Descriptors List
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; As stated earlier, each buffer descriptor list is a set of (up to) 32
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; descriptors, each 8 bytes in length. Bytes 0-3 of a descriptor entry point
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; to a chunk of memory to either play from or record to. Bytes 4-7 of an
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; entry describe various control things detailed below.
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;
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; Buffer pointers must always be aligned on a Dword boundry.
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;
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;
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IOC = BIT31 ; Fire an interrupt whenever this
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; buffer is complete.
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BUP = BIT30 ; Buffer Underrun Policy.
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; if this buffer is the last buffer
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; in a playback, fill the remaining
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; samples with 0 (silence) or not.
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; It's a good idea to set this to 1
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; for the last buffer in playback,
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; otherwise you're likely to get a lot
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; of noise at the end of the sound.
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;
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; Bits 15:0 contain the length of the buffer, in number of samples, which
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; are 16 bits each, coupled in left and right pairs, or 32bits each.
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; Luckily for us, that's the same format as .wav files.
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;
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; A value of FFFF is 65536 samples. Running at 44.1Khz, that's just about
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; 1.5 seconds of sample time. FFFF * 32bits is 1FFFFh bytes or 128k of data.
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;
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; A value of 0 in these bits means play no samples.
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;
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;*****************************************************************************
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;* AC97 Codec registers include (based on Jeff Leyda AC97 wav player SDK :-)
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;*****************************************************************************
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; Not all codecs are created =al. Refer to the spec for your specific codec.
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; All registers are 16bits wide. Access to codec registers over the AC97 link
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; is defined by the OEM.
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; Secondary codec's are accessed by ORing in BIT7 of all register accesses.
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; each codec/mixer register is 16bits
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CODEC_RESET_REG = 00 ; reset codec
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CODEC_MASTER_VOL_REG = 02 ; master volume
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CODEC_HP_VOL_REG = 04 ; headphone volume
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CODEC_MASTER_MONO_VOL_REG = 06 ; master mono volume
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CODEC_MASTER_TONE_REG = 08 ; master tone (R+L)
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CODEC_PCBEEP_VOL_REG = 0ah ; PC beep volume
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CODEC_PHONE_VOL_REG = 0ch ; phone volume
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CODEC_MIC_VOL_REG = 0eh ; MIC volume
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CODEC_LINE_IN_VOL_REG = 10h ; line input volume
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CODEC_CD_VOL_REG = 12h ; CD volume
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CODEC_VID_VOL_REG = 14h ; video volume
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CODEC_AUX_VOL_REG = 16h ; aux volume
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CODEC_PCM_OUT_REG = 18h ; PCM output volume
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CODEC_RECORD_SELECT_REG = 1ah ; record select input
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CODEC_RECORD_VOL_REG = 1ch ; record volume
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CODEC_RECORD_MIC_VOL_REG = 1eh ; record mic volume
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CODEC_GP_REG = 20h ; general purpose
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CODEC_3D_CONTROL_REG = 22h ; 3D control
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; 24h is reserved
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CODEC_POWER_CTRL_REG = 26h ; powerdown control
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CODEC_EXT_AUDIO_REG = 28h ; extended audio
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CODEC_EXT_AUDIO_CTRL_REG = 2ah ; extended audio control
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CODEC_PCM_FRONT_DACRATE_REG = 2ch ; PCM out sample rate
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CODEC_PCM_SURND_DACRATE_REG = 2eh ; surround sound sample rate
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CODEC_PCM_LFE_DACRATE_REG = 30h ; LFE sample rate
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CODEC_LR_ADCRATE_REG = 32h ; PCM in sample rate
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CODEC_MIC_ADCRATE_REG = 34h ; mic in sample rate
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; registers 36-7a are reserved on the ICH
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CODEC_VENDORID1_REG = 7ch ; codec vendor ID 1
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CODEC_VENDORID2_REG = 7eh ; codec vendor ID 2
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; When 2 codecs are present in the system, use BIT7 to access the 2nd
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; set of registers, ie 80h-feh
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SECONDARY_CODEC = BIT7 ; 80-8f registers for 2nda |