949 lines
25 KiB
C
949 lines
25 KiB
C
/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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//#include <linux/console.h>
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#include <drm/drmP.h>
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#include <drm/drm_crtc_helper.h>
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#include "radeon_drm.h"
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#include "radeon_reg.h"
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#include "radeon.h"
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#include "radeon_asic.h"
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#include "atom.h"
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#include <syscall.h>
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int radeon_dynclks = -1;
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int radeon_r4xx_atom = 0;
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int radeon_agpmode = -1;
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int radeon_gart_size = 512; /* default gart size */
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int radeon_benchmarking = 0;
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int radeon_connector_table = 0;
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int radeon_tv = 1;
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/*
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* Clear GPU surface registers.
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*/
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void radeon_surface_init(struct radeon_device *rdev)
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{
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ENTER();
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/* FIXME: check this out */
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if (rdev->family < CHIP_R600) {
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int i;
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for (i = 0; i < 8; i++) {
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WREG32(RADEON_SURFACE0_INFO +
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i * (RADEON_SURFACE1_INFO - RADEON_SURFACE0_INFO),
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0);
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}
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/* enable surfaces */
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WREG32(RADEON_SURFACE_CNTL, 0);
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}
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}
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/*
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* GPU scratch registers helpers function.
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*/
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void radeon_scratch_init(struct radeon_device *rdev)
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{
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int i;
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/* FIXME: check this out */
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if (rdev->family < CHIP_R300) {
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rdev->scratch.num_reg = 5;
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} else {
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rdev->scratch.num_reg = 7;
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}
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for (i = 0; i < rdev->scratch.num_reg; i++) {
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rdev->scratch.free[i] = true;
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rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4);
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}
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}
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int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
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{
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int i;
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for (i = 0; i < rdev->scratch.num_reg; i++) {
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if (rdev->scratch.free[i]) {
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rdev->scratch.free[i] = false;
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*reg = rdev->scratch.reg[i];
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return 0;
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}
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}
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return -EINVAL;
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}
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void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
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{
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int i;
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for (i = 0; i < rdev->scratch.num_reg; i++) {
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if (rdev->scratch.reg[i] == reg) {
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rdev->scratch.free[i] = true;
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return;
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}
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}
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}
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/*
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* MC common functions
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*/
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int radeon_mc_setup(struct radeon_device *rdev)
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{
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uint32_t tmp;
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/* Some chips have an "issue" with the memory controller, the
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* location must be aligned to the size. We just align it down,
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* too bad if we walk over the top of system memory, we don't
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* use DMA without a remapped anyway.
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* Affected chips are rv280, all r3xx, and all r4xx, but not IGP
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*/
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/* FGLRX seems to setup like this, VRAM a 0, then GART.
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*/
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/*
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* Note: from R6xx the address space is 40bits but here we only
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* use 32bits (still have to see a card which would exhaust 4G
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* address space).
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*/
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if (rdev->mc.vram_location != 0xFFFFFFFFUL) {
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/* vram location was already setup try to put gtt after
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* if it fits */
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tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
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tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
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if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
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rdev->mc.gtt_location = tmp;
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} else {
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if (rdev->mc.gtt_size >= rdev->mc.vram_location) {
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printk(KERN_ERR "[drm] GTT too big to fit "
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"before or after vram location.\n");
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return -EINVAL;
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}
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rdev->mc.gtt_location = 0;
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}
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} else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) {
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/* gtt location was already setup try to put vram before
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* if it fits */
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if (rdev->mc.mc_vram_size < rdev->mc.gtt_location) {
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rdev->mc.vram_location = 0;
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} else {
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tmp = rdev->mc.gtt_location + rdev->mc.gtt_size;
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tmp += (rdev->mc.mc_vram_size - 1);
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tmp &= ~(rdev->mc.mc_vram_size - 1);
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if ((0xFFFFFFFFUL - tmp) >= rdev->mc.mc_vram_size) {
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rdev->mc.vram_location = tmp;
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} else {
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printk(KERN_ERR "[drm] vram too big to fit "
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"before or after GTT location.\n");
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return -EINVAL;
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}
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}
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} else {
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rdev->mc.vram_location = 0;
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tmp = rdev->mc.mc_vram_size;
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tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
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rdev->mc.gtt_location = tmp;
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}
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rdev->mc.vram_start = rdev->mc.vram_location;
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rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
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rdev->mc.gtt_start = rdev->mc.gtt_location;
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rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
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DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev->mc.mc_vram_size >> 20));
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DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
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(unsigned)rdev->mc.vram_location,
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(unsigned)(rdev->mc.vram_location + rdev->mc.mc_vram_size - 1));
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DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev->mc.gtt_size >> 20));
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DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",
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(unsigned)rdev->mc.gtt_location,
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(unsigned)(rdev->mc.gtt_location + rdev->mc.gtt_size - 1));
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return 0;
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}
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/*
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* GPU helpers function.
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*/
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bool radeon_card_posted(struct radeon_device *rdev)
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{
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uint32_t reg;
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ENTER();
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/* first check CRTCs */
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if (ASIC_IS_AVIVO(rdev)) {
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reg = RREG32(AVIVO_D1CRTC_CONTROL) |
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RREG32(AVIVO_D2CRTC_CONTROL);
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if (reg & AVIVO_CRTC_EN) {
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return true;
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}
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} else {
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reg = RREG32(RADEON_CRTC_GEN_CNTL) |
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RREG32(RADEON_CRTC2_GEN_CNTL);
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if (reg & RADEON_CRTC_EN) {
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return true;
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}
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}
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/* then check MEM_SIZE, in case the crtcs are off */
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if (rdev->family >= CHIP_R600)
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reg = RREG32(R600_CONFIG_MEMSIZE);
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else
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reg = RREG32(RADEON_CONFIG_MEMSIZE);
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if (reg)
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return true;
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return false;
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}
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/*
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* Registers accessors functions.
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*/
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uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
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{
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DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
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BUG_ON(1);
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return 0;
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}
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void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
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{
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DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
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reg, v);
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BUG_ON(1);
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}
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void radeon_register_accessor_init(struct radeon_device *rdev)
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{
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rdev->mc_rreg = &radeon_invalid_rreg;
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rdev->mc_wreg = &radeon_invalid_wreg;
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rdev->pll_rreg = &radeon_invalid_rreg;
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rdev->pll_wreg = &radeon_invalid_wreg;
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rdev->pciep_rreg = &radeon_invalid_rreg;
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rdev->pciep_wreg = &radeon_invalid_wreg;
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/* Don't change order as we are overridding accessor. */
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if (rdev->family < CHIP_RV515) {
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rdev->pcie_reg_mask = 0xff;
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} else {
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rdev->pcie_reg_mask = 0x7ff;
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}
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/* FIXME: not sure here */
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if (rdev->family <= CHIP_R580) {
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rdev->pll_rreg = &r100_pll_rreg;
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rdev->pll_wreg = &r100_pll_wreg;
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}
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if (rdev->family >= CHIP_R420) {
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rdev->mc_rreg = &r420_mc_rreg;
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rdev->mc_wreg = &r420_mc_wreg;
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}
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if (rdev->family >= CHIP_RV515) {
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rdev->mc_rreg = &rv515_mc_rreg;
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rdev->mc_wreg = &rv515_mc_wreg;
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}
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if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
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rdev->mc_rreg = &rs400_mc_rreg;
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rdev->mc_wreg = &rs400_mc_wreg;
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}
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// if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
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// rdev->mc_rreg = &rs690_mc_rreg;
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// rdev->mc_wreg = &rs690_mc_wreg;
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// }
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// if (rdev->family == CHIP_RS600) {
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// rdev->mc_rreg = &rs600_mc_rreg;
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// rdev->mc_wreg = &rs600_mc_wreg;
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// }
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// if (rdev->family >= CHIP_R600) {
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// rdev->pciep_rreg = &r600_pciep_rreg;
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// rdev->pciep_wreg = &r600_pciep_wreg;
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// }
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}
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/*
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* ASIC
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*/
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int radeon_asic_init(struct radeon_device *rdev)
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{
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radeon_register_accessor_init(rdev);
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switch (rdev->family) {
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case CHIP_R100:
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case CHIP_RV100:
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case CHIP_RS100:
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case CHIP_RV200:
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case CHIP_RS200:
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case CHIP_R200:
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case CHIP_RV250:
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case CHIP_RS300:
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case CHIP_RV280:
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rdev->asic = &r100_asic;
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break;
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case CHIP_R300:
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case CHIP_R350:
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case CHIP_RV350:
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case CHIP_RV380:
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rdev->asic = &r300_asic;
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if (rdev->flags & RADEON_IS_PCIE) {
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rdev->asic->gart_init = &rv370_pcie_gart_init;
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rdev->asic->gart_fini = &rv370_pcie_gart_fini;
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rdev->asic->gart_enable = &rv370_pcie_gart_enable;
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rdev->asic->gart_disable = &rv370_pcie_gart_disable;
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rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
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rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
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}
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break;
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case CHIP_R420:
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case CHIP_R423:
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case CHIP_RV410:
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rdev->asic = &r420_asic;
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break;
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case CHIP_RS400:
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case CHIP_RS480:
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rdev->asic = &rs400_asic;
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break;
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case CHIP_RS600:
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// rdev->asic = &rs600_asic;
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break;
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case CHIP_RS690:
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case CHIP_RS740:
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// rdev->asic = &rs690_asic;
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break;
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case CHIP_RV515:
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rdev->asic = &rv515_asic;
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break;
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case CHIP_R520:
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case CHIP_RV530:
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case CHIP_RV560:
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case CHIP_RV570:
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case CHIP_R580:
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rdev->asic = &r520_asic;
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break;
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case CHIP_R600:
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case CHIP_RV610:
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case CHIP_RV630:
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case CHIP_RV620:
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case CHIP_RV635:
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case CHIP_RV670:
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case CHIP_RS780:
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case CHIP_RV770:
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case CHIP_RV730:
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case CHIP_RV710:
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default:
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/* FIXME: not supported yet */
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return -EINVAL;
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}
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return 0;
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}
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/*
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* Wrapper around modesetting bits.
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*/
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int radeon_clocks_init(struct radeon_device *rdev)
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{
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int r;
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ENTER();
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r = radeon_static_clocks_init(rdev->ddev);
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if (r) {
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return r;
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}
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DRM_INFO("Clocks initialized !\n");
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return 0;
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}
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void radeon_clocks_fini(struct radeon_device *rdev)
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{
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}
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/* ATOM accessor methods */
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static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
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{
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struct radeon_device *rdev = info->dev->dev_private;
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uint32_t r;
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r = rdev->pll_rreg(rdev, reg);
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return r;
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}
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static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
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{
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struct radeon_device *rdev = info->dev->dev_private;
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rdev->pll_wreg(rdev, reg, val);
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}
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static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
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{
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struct radeon_device *rdev = info->dev->dev_private;
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uint32_t r;
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r = rdev->mc_rreg(rdev, reg);
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return r;
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}
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static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
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{
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struct radeon_device *rdev = info->dev->dev_private;
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rdev->mc_wreg(rdev, reg, val);
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}
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static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
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{
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struct radeon_device *rdev = info->dev->dev_private;
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WREG32(reg*4, val);
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}
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static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
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{
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struct radeon_device *rdev = info->dev->dev_private;
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uint32_t r;
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r = RREG32(reg*4);
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return r;
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}
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static struct card_info atom_card_info = {
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.dev = NULL,
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.reg_read = cail_reg_read,
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.reg_write = cail_reg_write,
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.mc_read = cail_mc_read,
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.mc_write = cail_mc_write,
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.pll_read = cail_pll_read,
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.pll_write = cail_pll_write,
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};
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int radeon_atombios_init(struct radeon_device *rdev)
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{
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ENTER();
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atom_card_info.dev = rdev->ddev;
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rdev->mode_info.atom_context = atom_parse(&atom_card_info, rdev->bios);
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radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
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return 0;
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}
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void radeon_atombios_fini(struct radeon_device *rdev)
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{
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kfree(rdev->mode_info.atom_context);
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}
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int radeon_combios_init(struct radeon_device *rdev)
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{
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radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
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return 0;
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}
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void radeon_combios_fini(struct radeon_device *rdev)
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{
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}
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int radeon_modeset_init(struct radeon_device *rdev);
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void radeon_modeset_fini(struct radeon_device *rdev);
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/*
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* Radeon device.
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*/
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int radeon_device_init(struct radeon_device *rdev,
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struct drm_device *ddev,
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struct pci_dev *pdev,
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uint32_t flags)
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{
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int r, ret;
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int dma_bits;
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ENTER();
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DRM_INFO("radeon: Initializing kernel modesetting.\n");
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rdev->shutdown = false;
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rdev->ddev = ddev;
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rdev->pdev = pdev;
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rdev->flags = flags;
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rdev->family = flags & RADEON_FAMILY_MASK;
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rdev->is_atom_bios = false;
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|
rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
|
|
rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
|
|
rdev->gpu_lockup = false;
|
|
/* mutex initialization are all done here so we
|
|
* can recall function without having locking issues */
|
|
// mutex_init(&rdev->cs_mutex);
|
|
// mutex_init(&rdev->ib_pool.mutex);
|
|
// mutex_init(&rdev->cp.mutex);
|
|
// rwlock_init(&rdev->fence_drv.lock);
|
|
|
|
/* Set asic functions */
|
|
r = radeon_asic_init(rdev);
|
|
if (r) {
|
|
return r;
|
|
}
|
|
|
|
if (radeon_agpmode == -1) {
|
|
rdev->flags &= ~RADEON_IS_AGP;
|
|
if (rdev->family >= CHIP_RV515 ||
|
|
rdev->family == CHIP_RV380 ||
|
|
rdev->family == CHIP_RV410 ||
|
|
rdev->family == CHIP_R423) {
|
|
DRM_INFO("Forcing AGP to PCIE mode\n");
|
|
rdev->flags |= RADEON_IS_PCIE;
|
|
rdev->asic->gart_init = &rv370_pcie_gart_init;
|
|
rdev->asic->gart_fini = &rv370_pcie_gart_fini;
|
|
rdev->asic->gart_enable = &rv370_pcie_gart_enable;
|
|
rdev->asic->gart_disable = &rv370_pcie_gart_disable;
|
|
rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
|
|
rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
|
|
} else {
|
|
DRM_INFO("Forcing AGP to PCI mode\n");
|
|
rdev->flags |= RADEON_IS_PCI;
|
|
rdev->asic->gart_init = &r100_pci_gart_init;
|
|
rdev->asic->gart_fini = &r100_pci_gart_fini;
|
|
rdev->asic->gart_enable = &r100_pci_gart_enable;
|
|
rdev->asic->gart_disable = &r100_pci_gart_disable;
|
|
rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
|
|
rdev->asic->gart_set_page = &r100_pci_gart_set_page;
|
|
}
|
|
}
|
|
|
|
/* set DMA mask + need_dma32 flags.
|
|
* PCIE - can handle 40-bits.
|
|
* IGP - can handle 40-bits (in theory)
|
|
* AGP - generally dma32 is safest
|
|
* PCI - only dma32
|
|
*/
|
|
rdev->need_dma32 = false;
|
|
if (rdev->flags & RADEON_IS_AGP)
|
|
rdev->need_dma32 = true;
|
|
if (rdev->flags & RADEON_IS_PCI)
|
|
rdev->need_dma32 = true;
|
|
|
|
dma_bits = rdev->need_dma32 ? 32 : 40;
|
|
r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
|
|
if (r) {
|
|
printk(KERN_WARNING "radeon: No suitable DMA available.\n");
|
|
}
|
|
|
|
/* Registers mapping */
|
|
/* TODO: block userspace mapping of io register */
|
|
rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
|
|
|
|
rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
|
|
|
|
rdev->rmmio = (void*)MapIoMem(rdev->rmmio_base, rdev->rmmio_size,
|
|
PG_SW+PG_NOCACHE);
|
|
|
|
if (rdev->rmmio == NULL) {
|
|
return -ENOMEM;
|
|
}
|
|
DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
|
|
DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
|
|
|
|
rdev->new_init_path = false;
|
|
r = radeon_init(rdev);
|
|
if (r) {
|
|
return r;
|
|
}
|
|
|
|
if (!rdev->new_init_path) {
|
|
/* Setup errata flags */
|
|
radeon_errata(rdev);
|
|
/* Initialize scratch registers */
|
|
radeon_scratch_init(rdev);
|
|
/* Initialize surface registers */
|
|
radeon_surface_init(rdev);
|
|
|
|
/* BIOS*/
|
|
if (!radeon_get_bios(rdev)) {
|
|
if (ASIC_IS_AVIVO(rdev))
|
|
return -EINVAL;
|
|
}
|
|
if (rdev->is_atom_bios) {
|
|
r = radeon_atombios_init(rdev);
|
|
if (r) {
|
|
return r;
|
|
}
|
|
} else {
|
|
r = radeon_combios_init(rdev);
|
|
if (r) {
|
|
return r;
|
|
}
|
|
}
|
|
/* Reset gpu before posting otherwise ATOM will enter infinite loop */
|
|
if (radeon_gpu_reset(rdev)) {
|
|
/* FIXME: what do we want to do here ? */
|
|
}
|
|
/* check if cards are posted or not */
|
|
if (!radeon_card_posted(rdev) && rdev->bios) {
|
|
DRM_INFO("GPU not posted. posting now...\n");
|
|
if (rdev->is_atom_bios) {
|
|
atom_asic_init(rdev->mode_info.atom_context);
|
|
} else {
|
|
radeon_combios_asic_init(rdev->ddev);
|
|
}
|
|
}
|
|
/* Get clock & vram information */
|
|
radeon_get_clock_info(rdev->ddev);
|
|
radeon_vram_info(rdev);
|
|
/* Initialize clocks */
|
|
r = radeon_clocks_init(rdev);
|
|
if (r) {
|
|
return r;
|
|
}
|
|
|
|
/* Initialize memory controller (also test AGP) */
|
|
r = radeon_mc_init(rdev);
|
|
if (r) {
|
|
return r;
|
|
}
|
|
/* Memory manager */
|
|
r = radeon_object_init(rdev);
|
|
if (r) {
|
|
return r;
|
|
}
|
|
r = radeon_gpu_gart_init(rdev);
|
|
if (r)
|
|
return r;
|
|
/* Initialize GART (initialize after TTM so we can allocate
|
|
* memory through TTM but finalize after TTM) */
|
|
r = radeon_gart_enable(rdev);
|
|
if (r)
|
|
return 0;
|
|
r = radeon_gem_init(rdev);
|
|
if (r)
|
|
return 0;
|
|
|
|
/* 1M ring buffer */
|
|
// r = radeon_cp_init(rdev, 1024 * 1024);
|
|
// if (r)
|
|
// return 0;
|
|
#if 0
|
|
r = radeon_wb_init(rdev);
|
|
if (r)
|
|
DRM_ERROR("radeon: failled initializing WB (%d).\n", r);
|
|
r = radeon_ib_pool_init(rdev);
|
|
if (r)
|
|
return 0;
|
|
r = radeon_ib_test(rdev);
|
|
if (r)
|
|
return 0;
|
|
#endif
|
|
rdev->accel_working = true;
|
|
}
|
|
DRM_INFO("radeon: kernel modesetting successfully initialized.\n");
|
|
// if (radeon_testing) {
|
|
// radeon_test_moves(rdev);
|
|
// }
|
|
// if (radeon_benchmarking) {
|
|
// radeon_benchmark(rdev);
|
|
// }
|
|
return 0;
|
|
}
|
|
|
|
|
|
static struct pci_device_id pciidlist[] = {
|
|
radeon_PCI_IDS
|
|
};
|
|
|
|
|
|
u32_t drvEntry(int action, char *cmdline)
|
|
{
|
|
struct pci_device_id *ent;
|
|
|
|
dev_t device;
|
|
int err;
|
|
u32_t retval = 0;
|
|
|
|
if(action != 1)
|
|
return 0;
|
|
|
|
if(!dbg_open("/hd0/2/atikms.log"))
|
|
{
|
|
printf("Can't open /hd0/2/atikms.log\nExit\n");
|
|
return 0;
|
|
}
|
|
|
|
if(cmdline)
|
|
dbgprintf("cmdline: %s\n", cmdline);
|
|
|
|
enum_pci_devices();
|
|
|
|
ent = find_pci_device(&device, pciidlist);
|
|
|
|
if( unlikely(ent == NULL) )
|
|
{
|
|
dbgprintf("device not found\n");
|
|
return 0;
|
|
};
|
|
|
|
dbgprintf("device %x:%x\n", device.pci_dev.vendor,
|
|
device.pci_dev.device);
|
|
|
|
err = drm_get_dev(&device.pci_dev, ent);
|
|
|
|
return retval;
|
|
};
|
|
|
|
/*
|
|
static struct drm_driver kms_driver = {
|
|
.driver_features =
|
|
DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_SG |
|
|
DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED | DRIVER_GEM,
|
|
.dev_priv_size = 0,
|
|
.load = radeon_driver_load_kms,
|
|
.firstopen = radeon_driver_firstopen_kms,
|
|
.open = radeon_driver_open_kms,
|
|
.preclose = radeon_driver_preclose_kms,
|
|
.postclose = radeon_driver_postclose_kms,
|
|
.lastclose = radeon_driver_lastclose_kms,
|
|
.unload = radeon_driver_unload_kms,
|
|
.suspend = radeon_suspend_kms,
|
|
.resume = radeon_resume_kms,
|
|
.get_vblank_counter = radeon_get_vblank_counter_kms,
|
|
.enable_vblank = radeon_enable_vblank_kms,
|
|
.disable_vblank = radeon_disable_vblank_kms,
|
|
.master_create = radeon_master_create_kms,
|
|
.master_destroy = radeon_master_destroy_kms,
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
.debugfs_init = radeon_debugfs_init,
|
|
.debugfs_cleanup = radeon_debugfs_cleanup,
|
|
#endif
|
|
.irq_preinstall = radeon_driver_irq_preinstall_kms,
|
|
.irq_postinstall = radeon_driver_irq_postinstall_kms,
|
|
.irq_uninstall = radeon_driver_irq_uninstall_kms,
|
|
.irq_handler = radeon_driver_irq_handler_kms,
|
|
.reclaim_buffers = drm_core_reclaim_buffers,
|
|
.get_map_ofs = drm_core_get_map_ofs,
|
|
.get_reg_ofs = drm_core_get_reg_ofs,
|
|
.ioctls = radeon_ioctls_kms,
|
|
.gem_init_object = radeon_gem_object_init,
|
|
.gem_free_object = radeon_gem_object_free,
|
|
.dma_ioctl = radeon_dma_ioctl_kms,
|
|
.fops = {
|
|
.owner = THIS_MODULE,
|
|
.open = drm_open,
|
|
.release = drm_release,
|
|
.ioctl = drm_ioctl,
|
|
.mmap = radeon_mmap,
|
|
.poll = drm_poll,
|
|
.fasync = drm_fasync,
|
|
#ifdef CONFIG_COMPAT
|
|
.compat_ioctl = NULL,
|
|
#endif
|
|
},
|
|
|
|
.pci_driver = {
|
|
.name = DRIVER_NAME,
|
|
.id_table = pciidlist,
|
|
.probe = radeon_pci_probe,
|
|
.remove = radeon_pci_remove,
|
|
.suspend = radeon_pci_suspend,
|
|
.resume = radeon_pci_resume,
|
|
},
|
|
|
|
.name = DRIVER_NAME,
|
|
.desc = DRIVER_DESC,
|
|
.date = DRIVER_DATE,
|
|
.major = KMS_DRIVER_MAJOR,
|
|
.minor = KMS_DRIVER_MINOR,
|
|
.patchlevel = KMS_DRIVER_PATCHLEVEL,
|
|
};
|
|
*/
|
|
|
|
|
|
/*
|
|
* Driver load/unload
|
|
*/
|
|
int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
|
|
{
|
|
struct radeon_device *rdev;
|
|
int r;
|
|
|
|
ENTER();
|
|
|
|
rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
|
|
if (rdev == NULL) {
|
|
return -ENOMEM;
|
|
};
|
|
|
|
dev->dev_private = (void *)rdev;
|
|
|
|
/* update BUS flag */
|
|
// if (drm_device_is_agp(dev)) {
|
|
flags |= RADEON_IS_AGP;
|
|
// } else if (drm_device_is_pcie(dev)) {
|
|
// flags |= RADEON_IS_PCIE;
|
|
// } else {
|
|
// flags |= RADEON_IS_PCI;
|
|
// }
|
|
|
|
/* radeon_device_init should report only fatal error
|
|
* like memory allocation failure or iomapping failure,
|
|
* or memory manager initialization failure, it must
|
|
* properly initialize the GPU MC controller and permit
|
|
* VRAM allocation
|
|
*/
|
|
r = radeon_device_init(rdev, dev, dev->pdev, flags);
|
|
if (r) {
|
|
DRM_ERROR("Fatal error while trying to initialize radeon.\n");
|
|
return r;
|
|
}
|
|
/* Again modeset_init should fail only on fatal error
|
|
* otherwise it should provide enough functionalities
|
|
* for shadowfb to run
|
|
*/
|
|
r = radeon_modeset_init(rdev);
|
|
if (r) {
|
|
return r;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|
{
|
|
struct drm_device *dev;
|
|
int ret;
|
|
|
|
dbgprintf("%s\n",__FUNCTION__);
|
|
|
|
dev = malloc(sizeof(*dev));
|
|
if (!dev)
|
|
return -ENOMEM;
|
|
|
|
// ret = pci_enable_device(pdev);
|
|
// if (ret)
|
|
// goto err_g1;
|
|
|
|
// pci_set_master(pdev);
|
|
|
|
// if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) {
|
|
// printk(KERN_ERR "DRM: Fill_in_dev failed.\n");
|
|
// goto err_g2;
|
|
// }
|
|
|
|
dev->pdev = pdev;
|
|
dev->pci_device = pdev->device;
|
|
dev->pci_vendor = pdev->vendor;
|
|
|
|
// if (drm_core_check_feature(dev, DRIVER_MODESET)) {
|
|
// pci_set_drvdata(pdev, dev);
|
|
// ret = drm_get_minor(dev, &dev->control, DRM_MINOR_CONTROL);
|
|
// if (ret)
|
|
// goto err_g2;
|
|
// }
|
|
|
|
// if ((ret = drm_get_minor(dev, &dev->primary, DRM_MINOR_LEGACY)))
|
|
// goto err_g3;
|
|
|
|
// if (dev->driver->load) {
|
|
// ret = dev->driver->load(dev, ent->driver_data);
|
|
// if (ret)
|
|
// goto err_g4;
|
|
// }
|
|
|
|
ret = radeon_driver_load_kms(dev, ent->driver_data );
|
|
if (ret)
|
|
goto err_g4;
|
|
|
|
// list_add_tail(&dev->driver_item, &driver->device_list);
|
|
|
|
// DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
|
|
// driver->name, driver->major, driver->minor, driver->patchlevel,
|
|
// driver->date, pci_name(pdev), dev->primary->index);
|
|
|
|
set_mode(dev, 1280, 1024);
|
|
|
|
return 0;
|
|
|
|
err_g4:
|
|
// drm_put_minor(&dev->primary);
|
|
//err_g3:
|
|
// if (drm_core_check_feature(dev, DRIVER_MODESET))
|
|
// drm_put_minor(&dev->control);
|
|
//err_g2:
|
|
// pci_disable_device(pdev);
|
|
//err_g1:
|
|
free(dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
resource_size_t drm_get_resource_start(struct drm_device *dev, unsigned int resource)
|
|
{
|
|
return pci_resource_start(dev->pdev, resource);
|
|
}
|
|
|
|
resource_size_t drm_get_resource_len(struct drm_device *dev, unsigned int resource)
|
|
{
|
|
return pci_resource_len(dev->pdev, resource);
|
|
}
|
|
|
|
|
|
uint32_t __div64_32(uint64_t *n, uint32_t base)
|
|
{
|
|
uint64_t rem = *n;
|
|
uint64_t b = base;
|
|
uint64_t res, d = 1;
|
|
uint32_t high = rem >> 32;
|
|
|
|
/* Reduce the thing a bit first */
|
|
res = 0;
|
|
if (high >= base) {
|
|
high /= base;
|
|
res = (uint64_t) high << 32;
|
|
rem -= (uint64_t) (high*base) << 32;
|
|
}
|
|
|
|
while ((int64_t)b > 0 && b < rem) {
|
|
b = b+b;
|
|
d = d+d;
|
|
}
|
|
|
|
do {
|
|
if (rem >= b) {
|
|
rem -= b;
|
|
res += d;
|
|
}
|
|
b >>= 1;
|
|
d >>= 1;
|
|
} while (d);
|
|
|
|
*n = res;
|
|
return rem;
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|