510 lines
14 KiB
C
510 lines
14 KiB
C
#ifndef _ASM_X86_BITOPS_H
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#define _ASM_X86_BITOPS_H
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/*
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* Copyright 1992, Linus Torvalds.
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*
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* Note: inlines with more than a single statement should be marked
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* __always_inline to avoid problems with older gcc's inlining heuristics.
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*/
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#ifndef _LINUX_BITOPS_H
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#error only <linux/bitops.h> can be included directly
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#endif
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#include <linux/compiler.h>
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#include <asm/alternative.h>
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#include <asm/rmwcc.h>
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#include <asm/barrier.h>
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#if BITS_PER_LONG == 32
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# define _BITOPS_LONG_SHIFT 5
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#elif BITS_PER_LONG == 64
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# define _BITOPS_LONG_SHIFT 6
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#else
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# error "Unexpected BITS_PER_LONG"
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#endif
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#define BIT_64(n) (U64_C(1) << (n))
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/*
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* These have to be done with inline assembly: that way the bit-setting
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* is guaranteed to be atomic. All bit operations return 0 if the bit
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* was cleared before the operation and != 0 if it was not.
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*
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* bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
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*/
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#if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ < 1)
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/* Technically wrong, but this avoids compilation errors on some gcc
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versions. */
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#define BITOP_ADDR(x) "=m" (*(volatile long *) (x))
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#else
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#define BITOP_ADDR(x) "+m" (*(volatile long *) (x))
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#endif
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#define ADDR BITOP_ADDR(addr)
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/*
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* We do the locked ops that don't return the old value as
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* a mask operation on a byte.
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*/
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#define IS_IMMEDIATE(nr) (__builtin_constant_p(nr))
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#define CONST_MASK_ADDR(nr, addr) BITOP_ADDR((void *)(addr) + ((nr)>>3))
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#define CONST_MASK(nr) (1 << ((nr) & 7))
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/**
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* set_bit - Atomically set a bit in memory
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* @nr: the bit to set
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* @addr: the address to start counting from
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*
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* This function is atomic and may not be reordered. See __set_bit()
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* if you do not require the atomic guarantees.
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*
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* Note: there are no guarantees that this function will not be reordered
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* on non x86 architectures, so if you are writing portable code,
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* make sure not to rely on its reordering guarantees.
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*
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* Note that @nr may be almost arbitrarily large; this function is not
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* restricted to acting on a single-word quantity.
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*/
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static __always_inline void
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set_bit(long nr, volatile unsigned long *addr)
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{
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if (IS_IMMEDIATE(nr)) {
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asm volatile(LOCK_PREFIX "orb %1,%0"
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: CONST_MASK_ADDR(nr, addr)
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: "iq" ((u8)CONST_MASK(nr))
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: "memory");
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} else {
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asm volatile(LOCK_PREFIX "bts %1,%0"
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: BITOP_ADDR(addr) : "Ir" (nr) : "memory");
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}
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}
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/**
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* __set_bit - Set a bit in memory
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* @nr: the bit to set
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* @addr: the address to start counting from
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*
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* Unlike set_bit(), this function is non-atomic and may be reordered.
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* If it's called on the same region of memory simultaneously, the effect
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* may be that only one operation succeeds.
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*/
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static __always_inline void __set_bit(long nr, volatile unsigned long *addr)
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{
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asm volatile("bts %1,%0" : ADDR : "Ir" (nr) : "memory");
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}
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/**
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* clear_bit - Clears a bit in memory
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* @nr: Bit to clear
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* @addr: Address to start counting from
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*
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* clear_bit() is atomic and may not be reordered. However, it does
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* not contain a memory barrier, so if it is used for locking purposes,
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* you should call smp_mb__before_atomic() and/or smp_mb__after_atomic()
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* in order to ensure changes are visible on other processors.
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*/
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static __always_inline void
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clear_bit(long nr, volatile unsigned long *addr)
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{
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if (IS_IMMEDIATE(nr)) {
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asm volatile(LOCK_PREFIX "andb %1,%0"
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: CONST_MASK_ADDR(nr, addr)
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: "iq" ((u8)~CONST_MASK(nr)));
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} else {
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asm volatile(LOCK_PREFIX "btr %1,%0"
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: BITOP_ADDR(addr)
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: "Ir" (nr));
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}
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}
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/*
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* clear_bit_unlock - Clears a bit in memory
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* @nr: Bit to clear
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* @addr: Address to start counting from
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*
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* clear_bit() is atomic and implies release semantics before the memory
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* operation. It can be used for an unlock.
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*/
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static __always_inline void clear_bit_unlock(long nr, volatile unsigned long *addr)
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{
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barrier();
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clear_bit(nr, addr);
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}
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static __always_inline void __clear_bit(long nr, volatile unsigned long *addr)
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{
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asm volatile("btr %1,%0" : ADDR : "Ir" (nr));
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}
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/*
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* __clear_bit_unlock - Clears a bit in memory
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* @nr: Bit to clear
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* @addr: Address to start counting from
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*
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* __clear_bit() is non-atomic and implies release semantics before the memory
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* operation. It can be used for an unlock if no other CPUs can concurrently
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* modify other bits in the word.
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*
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* No memory barrier is required here, because x86 cannot reorder stores past
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* older loads. Same principle as spin_unlock.
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*/
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static __always_inline void __clear_bit_unlock(long nr, volatile unsigned long *addr)
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{
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barrier();
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__clear_bit(nr, addr);
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}
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/**
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* __change_bit - Toggle a bit in memory
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* @nr: the bit to change
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* @addr: the address to start counting from
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*
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* Unlike change_bit(), this function is non-atomic and may be reordered.
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* If it's called on the same region of memory simultaneously, the effect
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* may be that only one operation succeeds.
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*/
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static __always_inline void __change_bit(long nr, volatile unsigned long *addr)
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{
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asm volatile("btc %1,%0" : ADDR : "Ir" (nr));
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}
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/**
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* change_bit - Toggle a bit in memory
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* @nr: Bit to change
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* @addr: Address to start counting from
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*
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* change_bit() is atomic and may not be reordered.
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* Note that @nr may be almost arbitrarily large; this function is not
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* restricted to acting on a single-word quantity.
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*/
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static __always_inline void change_bit(long nr, volatile unsigned long *addr)
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{
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if (IS_IMMEDIATE(nr)) {
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asm volatile(LOCK_PREFIX "xorb %1,%0"
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: CONST_MASK_ADDR(nr, addr)
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: "iq" ((u8)CONST_MASK(nr)));
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} else {
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asm volatile(LOCK_PREFIX "btc %1,%0"
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: BITOP_ADDR(addr)
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: "Ir" (nr));
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}
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}
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/**
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* test_and_set_bit - Set a bit and return its old value
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* @nr: Bit to set
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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*/
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static __always_inline int test_and_set_bit(long nr, volatile unsigned long *addr)
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{
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GEN_BINARY_RMWcc(LOCK_PREFIX "bts", *addr, "Ir", nr, "%0", "c");
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}
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/**
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* test_and_set_bit_lock - Set a bit and return its old value for lock
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* @nr: Bit to set
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* @addr: Address to count from
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*
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* This is the same as test_and_set_bit on x86.
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*/
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static __always_inline int
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test_and_set_bit_lock(long nr, volatile unsigned long *addr)
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{
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return test_and_set_bit(nr, addr);
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}
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/**
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* __test_and_set_bit - Set a bit and return its old value
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* @nr: Bit to set
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* @addr: Address to count from
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*
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* This operation is non-atomic and can be reordered.
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* If two examples of this operation race, one can appear to succeed
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* but actually fail. You must protect multiple accesses with a lock.
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*/
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static __always_inline int __test_and_set_bit(long nr, volatile unsigned long *addr)
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{
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int oldbit;
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asm("bts %2,%1\n\t"
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"sbb %0,%0"
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: "=r" (oldbit), ADDR
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: "Ir" (nr));
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return oldbit;
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}
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/**
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* test_and_clear_bit - Clear a bit and return its old value
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* @nr: Bit to clear
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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*/
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static __always_inline int test_and_clear_bit(long nr, volatile unsigned long *addr)
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{
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GEN_BINARY_RMWcc(LOCK_PREFIX "btr", *addr, "Ir", nr, "%0", "c");
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}
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/**
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* __test_and_clear_bit - Clear a bit and return its old value
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* @nr: Bit to clear
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* @addr: Address to count from
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*
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* This operation is non-atomic and can be reordered.
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* If two examples of this operation race, one can appear to succeed
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* but actually fail. You must protect multiple accesses with a lock.
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*
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* Note: the operation is performed atomically with respect to
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* the local CPU, but not other CPUs. Portable code should not
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* rely on this behaviour.
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* KVM relies on this behaviour on x86 for modifying memory that is also
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* accessed from a hypervisor on the same CPU if running in a VM: don't change
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* this without also updating arch/x86/kernel/kvm.c
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*/
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static __always_inline int __test_and_clear_bit(long nr, volatile unsigned long *addr)
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{
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int oldbit;
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asm volatile("btr %2,%1\n\t"
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"sbb %0,%0"
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: "=r" (oldbit), ADDR
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: "Ir" (nr));
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return oldbit;
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}
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/* WARNING: non atomic and it can be reordered! */
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static __always_inline int __test_and_change_bit(long nr, volatile unsigned long *addr)
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{
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int oldbit;
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asm volatile("btc %2,%1\n\t"
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"sbb %0,%0"
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: "=r" (oldbit), ADDR
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: "Ir" (nr) : "memory");
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return oldbit;
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}
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/**
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* test_and_change_bit - Change a bit and return its old value
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* @nr: Bit to change
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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*/
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static __always_inline int test_and_change_bit(long nr, volatile unsigned long *addr)
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{
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GEN_BINARY_RMWcc(LOCK_PREFIX "btc", *addr, "Ir", nr, "%0", "c");
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}
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static __always_inline int constant_test_bit(long nr, const volatile unsigned long *addr)
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{
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return ((1UL << (nr & (BITS_PER_LONG-1))) &
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(addr[nr >> _BITOPS_LONG_SHIFT])) != 0;
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}
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static __always_inline int variable_test_bit(long nr, volatile const unsigned long *addr)
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{
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int oldbit;
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asm volatile("bt %2,%1\n\t"
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"sbb %0,%0"
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: "=r" (oldbit)
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: "m" (*(unsigned long *)addr), "Ir" (nr));
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return oldbit;
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}
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#if 0 /* Fool kernel-doc since it doesn't do macros yet */
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/**
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* test_bit - Determine whether a bit is set
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* @nr: bit number to test
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* @addr: Address to start counting from
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*/
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static int test_bit(int nr, const volatile unsigned long *addr);
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#endif
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#define test_bit(nr, addr) \
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(__builtin_constant_p((nr)) \
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? constant_test_bit((nr), (addr)) \
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: variable_test_bit((nr), (addr)))
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/**
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* __ffs - find first set bit in word
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* @word: The word to search
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*
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* Undefined if no bit exists, so code should check against 0 first.
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*/
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static __always_inline unsigned long __ffs(unsigned long word)
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{
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asm("rep; bsf %1,%0"
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: "=r" (word)
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: "rm" (word));
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return word;
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}
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/**
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* ffz - find first zero bit in word
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* @word: The word to search
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*
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* Undefined if no zero exists, so code should check against ~0UL first.
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*/
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static __always_inline unsigned long ffz(unsigned long word)
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{
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asm("rep; bsf %1,%0"
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: "=r" (word)
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: "r" (~word));
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return word;
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}
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/*
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* __fls: find last set bit in word
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* @word: The word to search
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*
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* Undefined if no set bit exists, so code should check against 0 first.
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*/
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static __always_inline unsigned long __fls(unsigned long word)
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{
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asm("bsr %1,%0"
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: "=r" (word)
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: "rm" (word));
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return word;
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}
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#undef ADDR
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#ifdef __KERNEL__
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/**
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* ffs - find first set bit in word
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* @x: the word to search
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*
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* This is defined the same way as the libc and compiler builtin ffs
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* routines, therefore differs in spirit from the other bitops.
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*
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* ffs(value) returns 0 if value is 0 or the position of the first
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* set bit if value is nonzero. The first (least significant) bit
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* is at position 1.
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*/
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static __always_inline int ffs(int x)
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{
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int r;
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#ifdef CONFIG_X86_64
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/*
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* AMD64 says BSFL won't clobber the dest reg if x==0; Intel64 says the
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* dest reg is undefined if x==0, but their CPU architect says its
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* value is written to set it to the same as before, except that the
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* top 32 bits will be cleared.
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*
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* We cannot do this on 32 bits because at the very least some
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* 486 CPUs did not behave this way.
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*/
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asm("bsfl %1,%0"
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: "=r" (r)
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: "rm" (x), "0" (-1));
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#elif defined(CONFIG_X86_CMOV)
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asm("bsfl %1,%0\n\t"
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"cmovzl %2,%0"
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: "=&r" (r) : "rm" (x), "r" (-1));
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#else
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asm("bsfl %1,%0\n\t"
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"jnz 1f\n\t"
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"movl $-1,%0\n"
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"1:" : "=r" (r) : "rm" (x));
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#endif
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return r + 1;
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}
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/**
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* fls - find last set bit in word
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* @x: the word to search
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*
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* This is defined in a similar way as the libc and compiler builtin
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* ffs, but returns the position of the most significant set bit.
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*
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* fls(value) returns 0 if value is 0 or the position of the last
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* set bit if value is nonzero. The last (most significant) bit is
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* at position 32.
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*/
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static __always_inline int fls(int x)
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{
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int r;
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#ifdef CONFIG_X86_64
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/*
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* AMD64 says BSRL won't clobber the dest reg if x==0; Intel64 says the
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* dest reg is undefined if x==0, but their CPU architect says its
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* value is written to set it to the same as before, except that the
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* top 32 bits will be cleared.
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*
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* We cannot do this on 32 bits because at the very least some
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* 486 CPUs did not behave this way.
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*/
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asm("bsrl %1,%0"
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: "=r" (r)
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: "rm" (x), "0" (-1));
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#elif defined(CONFIG_X86_CMOV)
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asm("bsrl %1,%0\n\t"
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"cmovzl %2,%0"
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: "=&r" (r) : "rm" (x), "rm" (-1));
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#else
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asm("bsrl %1,%0\n\t"
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"jnz 1f\n\t"
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"movl $-1,%0\n"
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"1:" : "=r" (r) : "rm" (x));
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#endif
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return r + 1;
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}
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/**
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* fls64 - find last set bit in a 64-bit word
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* @x: the word to search
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*
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* This is defined in a similar way as the libc and compiler builtin
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* ffsll, but returns the position of the most significant set bit.
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*
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* fls64(value) returns 0 if value is 0 or the position of the last
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* set bit if value is nonzero. The last (most significant) bit is
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* at position 64.
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*/
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#ifdef CONFIG_X86_64
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static __always_inline int fls64(__u64 x)
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{
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int bitpos = -1;
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/*
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* AMD64 says BSRQ won't clobber the dest reg if x==0; Intel64 says the
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* dest reg is undefined if x==0, but their CPU architect says its
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* value is written to set it to the same as before.
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*/
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asm("bsrq %1,%q0"
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: "+r" (bitpos)
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: "rm" (x));
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return bitpos + 1;
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}
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#else
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#include <asm-generic/bitops/fls64.h>
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#endif
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#include <asm-generic/bitops/find.h>
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#include <asm-generic/bitops/sched.h>
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#include <asm/arch_hweight.h>
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#include <asm-generic/bitops/const_hweight.h>
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#include <asm-generic/bitops/le.h>
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#include <asm-generic/bitops/ext2-atomic-setbit.h>
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#endif /* __KERNEL__ */
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#endif /* _ASM_X86_BITOPS_H */
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