348 lines
9.2 KiB
C
348 lines
9.2 KiB
C
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#include <ddk.h>
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#include <linux/errno.h>
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#include <mutex.h>
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#include <pci.h>
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#include <syscall.h>
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extern struct list_head pci_root_buses;
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#define IO_SPACE_LIMIT 0xffff
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#define PCIBIOS_SUCCESSFUL 0x00
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struct resource ioport_resource = {
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.name = "PCI IO",
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.start = 0,
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.end = IO_SPACE_LIMIT,
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.flags = IORESOURCE_IO,
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};
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struct resource iomem_resource = {
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.name = "PCI mem",
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.start = 0,
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.end = -1,
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.flags = IORESOURCE_MEM,
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};
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#define PCI_FIND_CAP_TTL 48
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static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
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u8 pos, int cap, int *ttl)
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{
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u8 id;
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while ((*ttl)--) {
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pci_bus_read_config_byte(bus, devfn, pos, &pos);
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if (pos < 0x40)
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break;
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pos &= ~3;
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pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
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&id);
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if (id == 0xff)
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break;
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if (id == cap)
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return pos;
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pos += PCI_CAP_LIST_NEXT;
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}
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return 0;
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}
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static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
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u8 pos, int cap)
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{
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int ttl = PCI_FIND_CAP_TTL;
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return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
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}
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static int __pci_bus_find_cap_start(struct pci_bus *bus,
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unsigned int devfn, u8 hdr_type)
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{
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u16 status;
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pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
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if (!(status & PCI_STATUS_CAP_LIST))
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return 0;
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switch (hdr_type) {
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case PCI_HEADER_TYPE_NORMAL:
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case PCI_HEADER_TYPE_BRIDGE:
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return PCI_CAPABILITY_LIST;
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case PCI_HEADER_TYPE_CARDBUS:
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return PCI_CB_CAPABILITY_LIST;
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default:
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return 0;
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}
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return 0;
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}
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/**
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* pci_find_capability - query for devices' capabilities
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* @dev: PCI device to query
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* @cap: capability code
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*
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* Tell if a device supports a given PCI capability.
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* Returns the address of the requested capability structure within the
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* device's PCI configuration space or 0 in case the device does not
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* support it. Possible values for @cap:
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*
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* %PCI_CAP_ID_PM Power Management
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* %PCI_CAP_ID_AGP Accelerated Graphics Port
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* %PCI_CAP_ID_VPD Vital Product Data
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* %PCI_CAP_ID_SLOTID Slot Identification
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* %PCI_CAP_ID_MSI Message Signalled Interrupts
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* %PCI_CAP_ID_CHSWP CompactPCI HotSwap
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* %PCI_CAP_ID_PCIX PCI-X
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* %PCI_CAP_ID_EXP PCI Express
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*/
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int pci_find_capability(struct pci_dev *dev, int cap)
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{
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int pos;
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pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
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if (pos)
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pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
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return pos;
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}
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static struct pci_bus *pci_do_find_bus(struct pci_bus *bus, unsigned char busnr)
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{
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struct pci_bus* child;
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struct list_head *tmp;
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if(bus->number == busnr)
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return bus;
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list_for_each(tmp, &bus->children) {
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child = pci_do_find_bus(pci_bus_b(tmp), busnr);
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if(child)
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return child;
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}
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return NULL;
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}
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/**
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* pci_find_bus - locate PCI bus from a given domain and bus number
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* @domain: number of PCI domain to search
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* @busnr: number of desired PCI bus
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*
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* Given a PCI bus number and domain number, the desired PCI bus is located
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* in the global list of PCI buses. If the bus is found, a pointer to its
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* data structure is returned. If no bus is found, %NULL is returned.
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*/
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struct pci_bus * pci_find_bus(int domain, int busnr)
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{
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struct pci_bus *bus = NULL;
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struct pci_bus *tmp_bus;
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while ((bus = pci_find_next_bus(bus)) != NULL) {
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if (pci_domain_nr(bus) != domain)
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continue;
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tmp_bus = pci_do_find_bus(bus, busnr);
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if (tmp_bus)
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return tmp_bus;
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}
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return NULL;
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}
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/**
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* pci_find_next_bus - begin or continue searching for a PCI bus
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* @from: Previous PCI bus found, or %NULL for new search.
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*
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* Iterates through the list of known PCI busses. A new search is
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* initiated by passing %NULL as the @from argument. Otherwise if
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* @from is not %NULL, searches continue from next device on the
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* global list.
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*/
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struct pci_bus *
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pci_find_next_bus(const struct pci_bus *from)
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{
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struct list_head *n;
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struct pci_bus *b = NULL;
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// WARN_ON(in_interrupt());
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// down_read(&pci_bus_sem);
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n = from ? from->node.next : pci_root_buses.next;
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if (n != &pci_root_buses)
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b = pci_bus_b(n);
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// up_read(&pci_bus_sem);
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return b;
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}
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/**
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* pci_get_slot - locate PCI device for a given PCI slot
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* @bus: PCI bus on which desired PCI device resides
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* @devfn: encodes number of PCI slot in which the desired PCI
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* device resides and the logical device number within that slot
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* in case of multi-function devices.
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*
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* Given a PCI bus and slot/function number, the desired PCI device
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* is located in the list of PCI devices.
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* If the device is found, its reference count is increased and this
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* function returns a pointer to its data structure. The caller must
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* decrement the reference count by calling pci_dev_put().
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* If no device is found, %NULL is returned.
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*/
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struct pci_dev * pci_get_slot(struct pci_bus *bus, unsigned int devfn)
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{
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struct list_head *tmp;
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struct pci_dev *dev;
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// WARN_ON(in_interrupt());
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// down_read(&pci_bus_sem);
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list_for_each(tmp, &bus->devices) {
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dev = pci_dev_b(tmp);
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if (dev->devfn == devfn)
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goto out;
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}
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dev = NULL;
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out:
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// pci_dev_get(dev);
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// up_read(&pci_bus_sem);
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return dev;
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}
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/**
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* pci_find_ext_capability - Find an extended capability
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* @dev: PCI device to query
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* @cap: capability code
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*
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* Returns the address of the requested extended capability structure
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* within the device's PCI configuration space or 0 if the device does
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* not support it. Possible values for @cap:
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*
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* %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
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* %PCI_EXT_CAP_ID_VC Virtual Channel
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* %PCI_EXT_CAP_ID_DSN Device Serial Number
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* %PCI_EXT_CAP_ID_PWR Power Budgeting
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*/
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int pci_find_ext_capability(struct pci_dev *dev, int cap)
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{
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u32 header;
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int ttl;
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int pos = PCI_CFG_SPACE_SIZE;
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/* minimum 8 bytes per capability */
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ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
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if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
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return 0;
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if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
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return 0;
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/*
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* If we have no capabilities, this is indicated by cap ID,
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* cap version and next pointer all being 0.
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*/
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if (header == 0)
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return 0;
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while (ttl-- > 0) {
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if (PCI_EXT_CAP_ID(header) == cap)
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return pos;
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pos = PCI_EXT_CAP_NEXT(header);
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if (pos < PCI_CFG_SPACE_SIZE)
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break;
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if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
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break;
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}
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return 0;
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}
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/**
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* pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
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* @dev: the PCI device
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* @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
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*
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* Perform INTx swizzling for a device behind one level of bridge. This is
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* required by section 9.1 of the PCI-to-PCI bridge specification for devices
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* behind bridges on add-in cards. For devices with ARI enabled, the slot
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* number is always 0 (see the Implementation Note in section 2.2.8.1 of
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* the PCI Express Base Specification, Revision 2.1)
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*/
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u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin)
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{
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int slot;
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// if (pci_ari_enabled(dev->bus))
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// slot = 0;
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// else
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slot = PCI_SLOT(dev->devfn);
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return (((pin - 1) + slot) % 4) + 1;
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}
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#if 0
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u32 pci_probe = 0;
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#define PCI_NOASSIGN_ROMS 0x80000
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#define PCI_NOASSIGN_BARS 0x200000
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static void pcibios_fixup_device_resources(struct pci_dev *dev)
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{
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struct resource *rom_r = &dev->resource[PCI_ROM_RESOURCE];
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struct resource *bar_r;
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int bar;
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if (pci_probe & PCI_NOASSIGN_BARS) {
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/*
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* If the BIOS did not assign the BAR, zero out the
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* resource so the kernel doesn't attmept to assign
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* it later on in pci_assign_unassigned_resources
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*/
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for (bar = 0; bar <= PCI_STD_RESOURCE_END; bar++) {
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bar_r = &dev->resource[bar];
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if (bar_r->start == 0 && bar_r->end != 0) {
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bar_r->flags = 0;
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bar_r->end = 0;
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}
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}
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}
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if (pci_probe & PCI_NOASSIGN_ROMS) {
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if (rom_r->parent)
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return;
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if (rom_r->start) {
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/* we deal with BIOS assigned ROM later */
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return;
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}
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rom_r->start = rom_r->end = rom_r->flags = 0;
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}
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}
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/*
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* Called after each bus is probed, but before its children
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* are examined.
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*/
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void pcibios_fixup_bus(struct pci_bus *b)
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{
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struct pci_dev *dev;
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/* root bus? */
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// if (!b->parent)
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// x86_pci_root_bus_res_quirks(b);
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pci_read_bridge_bases(b);
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list_for_each_entry(dev, &b->devices, bus_list)
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pcibios_fixup_device_resources(dev);
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}
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#endif
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