389 lines
11 KiB
C
389 lines
11 KiB
C
/*
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* Copyright © 2010 Daniel Vetter
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include <drm/drmP.h>
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#include <drm/i915_drm.h>
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#include "i915_drv.h"
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#include "i915_trace.h"
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#include "intel_drv.h"
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#define AGP_USER_TYPES (1 << 16)
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#define AGP_USER_MEMORY (AGP_USER_TYPES)
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#define AGP_USER_CACHED_MEMORY (AGP_USER_TYPES + 1)
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/* PPGTT support for Sandybdrige/Gen6 and later */
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static void i915_ppgtt_clear_range(struct i915_hw_ppgtt *ppgtt,
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unsigned first_entry,
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unsigned num_entries)
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{
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uint32_t *pt_vaddr;
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uint32_t scratch_pte;
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unsigned act_pd = first_entry / I915_PPGTT_PT_ENTRIES;
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unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
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unsigned last_pte, i;
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scratch_pte = GEN6_PTE_ADDR_ENCODE(ppgtt->scratch_page_dma_addr);
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scratch_pte |= GEN6_PTE_VALID | GEN6_PTE_CACHE_LLC;
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pt_vaddr = AllocKernelSpace(4096);
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if(pt_vaddr != NULL)
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{
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while (num_entries)
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{
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last_pte = first_pte + num_entries;
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if (last_pte > I915_PPGTT_PT_ENTRIES)
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last_pte = I915_PPGTT_PT_ENTRIES;
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MapPage(pt_vaddr,ppgtt->pt_pages[act_pd], 3);
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for (i = first_pte; i < last_pte; i++)
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pt_vaddr[i] = scratch_pte;
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num_entries -= last_pte - first_pte;
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first_pte = 0;
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act_pd++;
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}
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FreeKernelSpace(pt_vaddr);
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};
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}
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int i915_gem_init_aliasing_ppgtt(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct i915_hw_ppgtt *ppgtt;
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unsigned first_pd_entry_in_global_pt;
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int i;
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int ret = -ENOMEM;
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/* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024
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* entries. For aliasing ppgtt support we just steal them at the end for
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* now. */
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first_pd_entry_in_global_pt = dev_priv->mm.gtt->gtt_total_entries - I915_PPGTT_PD_ENTRIES;
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ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
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if (!ppgtt)
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return ret;
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ppgtt->num_pd_entries = I915_PPGTT_PD_ENTRIES;
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ppgtt->pt_pages = kzalloc(sizeof(dma_addr_t)*ppgtt->num_pd_entries,
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GFP_KERNEL);
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if (!ppgtt->pt_pages)
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goto err_ppgtt;
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for (i = 0; i < ppgtt->num_pd_entries; i++) {
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ppgtt->pt_pages[i] = AllocPage();
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if (!ppgtt->pt_pages[i])
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goto err_pt_alloc;
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}
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/*
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if (dev_priv->mm.gtt->needs_dmar) {
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ppgtt->pt_dma_addr = kzalloc(sizeof(dma_addr_t)
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*ppgtt->num_pd_entries,
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GFP_KERNEL);
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if (!ppgtt->pt_dma_addr)
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goto err_pt_alloc;
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for (i = 0; i < ppgtt->num_pd_entries; i++) {
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dma_addr_t pt_addr;
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pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i],
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0, 4096,
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PCI_DMA_BIDIRECTIONAL);
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if (pci_dma_mapping_error(dev->pdev,
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pt_addr)) {
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ret = -EIO;
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goto err_pd_pin;
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}
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ppgtt->pt_dma_addr[i] = pt_addr;
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}
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}
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*/
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ppgtt->scratch_page_dma_addr = dev_priv->mm.gtt->scratch_page_dma;
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i915_ppgtt_clear_range(ppgtt, 0,
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ppgtt->num_pd_entries*I915_PPGTT_PT_ENTRIES);
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ppgtt->pd_offset = (first_pd_entry_in_global_pt)*sizeof(uint32_t);
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dev_priv->mm.aliasing_ppgtt = ppgtt;
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return 0;
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err_pd_pin:
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// if (ppgtt->pt_dma_addr) {
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// for (i--; i >= 0; i--)
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// pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i],
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// 4096, PCI_DMA_BIDIRECTIONAL);
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// }
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err_pt_alloc:
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// kfree(ppgtt->pt_dma_addr);
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for (i = 0; i < ppgtt->num_pd_entries; i++) {
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if (ppgtt->pt_pages[i])
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FreePage(ppgtt->pt_pages[i]);
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}
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kfree(ppgtt->pt_pages);
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err_ppgtt:
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kfree(ppgtt);
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return ret;
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}
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void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
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int i;
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if (!ppgtt)
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return;
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// if (ppgtt->pt_dma_addr) {
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// for (i = 0; i < ppgtt->num_pd_entries; i++)
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// pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i],
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// 4096, PCI_DMA_BIDIRECTIONAL);
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// }
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// kfree(ppgtt->pt_dma_addr);
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for (i = 0; i < ppgtt->num_pd_entries; i++)
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FreePage(ppgtt->pt_pages[i]);
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kfree(ppgtt->pt_pages);
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kfree(ppgtt);
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}
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static void i915_ppgtt_insert_sg_entries(struct i915_hw_ppgtt *ppgtt,
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const struct pagelist *pages,
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unsigned first_entry,
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uint32_t pte_flags)
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{
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uint32_t *pt_vaddr, pte;
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unsigned act_pd = first_entry / I915_PPGTT_PT_ENTRIES;
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unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
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unsigned i, j;
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dma_addr_t page_addr;
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i = 0;
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pt_vaddr = AllocKernelSpace(4096);
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if( pt_vaddr != NULL)
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{
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while (i < pages->nents)
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{
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MapPage(pt_vaddr, ppgtt->pt_pages[act_pd], 3);
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for (j = first_pte; j < I915_PPGTT_PT_ENTRIES; j++, i++) {
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page_addr = pages->page[i];
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pte = GEN6_PTE_ADDR_ENCODE(page_addr);
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pt_vaddr[j] = pte | pte_flags;
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}
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first_pte = 0;
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act_pd++;
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}
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FreeKernelSpace(pt_vaddr);
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};
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}
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void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
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struct drm_i915_gem_object *obj,
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enum i915_cache_level cache_level)
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{
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uint32_t pte_flags = GEN6_PTE_VALID;
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switch (cache_level) {
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case I915_CACHE_LLC_MLC:
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pte_flags |= GEN6_PTE_CACHE_LLC_MLC;
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break;
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case I915_CACHE_LLC:
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pte_flags |= GEN6_PTE_CACHE_LLC;
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break;
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case I915_CACHE_NONE:
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if (IS_HASWELL(obj->base.dev))
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pte_flags |= HSW_PTE_UNCACHED;
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else
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pte_flags |= GEN6_PTE_UNCACHED;
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break;
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default:
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BUG();
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}
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i915_ppgtt_insert_sg_entries(ppgtt,
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&obj->pages,
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obj->gtt_space->start >> PAGE_SHIFT,
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pte_flags);
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}
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void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
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struct drm_i915_gem_object *obj)
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{
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i915_ppgtt_clear_range(ppgtt,
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obj->gtt_space->start >> PAGE_SHIFT,
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obj->base.size >> PAGE_SHIFT);
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}
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/* XXX kill agp_type! */
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static unsigned int cache_level_to_agp_type(struct drm_device *dev,
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enum i915_cache_level cache_level)
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{
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switch (cache_level) {
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case I915_CACHE_LLC_MLC:
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if (INTEL_INFO(dev)->gen >= 6)
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return AGP_USER_CACHED_MEMORY_LLC_MLC;
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/* Older chipsets do not have this extra level of CPU
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* cacheing, so fallthrough and request the PTE simply
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* as cached.
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*/
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case I915_CACHE_LLC:
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return AGP_USER_CACHED_MEMORY;
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default:
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case I915_CACHE_NONE:
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return AGP_USER_MEMORY;
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}
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}
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static bool do_idling(struct drm_i915_private *dev_priv)
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{
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bool ret = dev_priv->mm.interruptible;
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if (unlikely(dev_priv->mm.gtt->do_idle_maps)) {
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dev_priv->mm.interruptible = false;
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if (i915_gpu_idle(dev_priv->dev)) {
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DRM_ERROR("Couldn't idle GPU\n");
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/* Wait a bit, in hopes it avoids the hang */
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udelay(10);
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}
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}
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return ret;
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}
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static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
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{
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if (unlikely(dev_priv->mm.gtt->do_idle_maps))
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dev_priv->mm.interruptible = interruptible;
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}
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#if 0
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void i915_gem_restore_gtt_mappings(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_i915_gem_object *obj;
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/* First fill our portion of the GTT with scratch pages */
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intel_gtt_clear_range(dev_priv->mm.gtt_start / PAGE_SIZE,
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(dev_priv->mm.gtt_end - dev_priv->mm.gtt_start) / PAGE_SIZE);
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list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
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i915_gem_clflush_object(obj);
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i915_gem_gtt_bind_object(obj, obj->cache_level);
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}
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intel_gtt_chipset_flush();
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}
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#endif
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int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
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{
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return 0;
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}
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void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
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enum i915_cache_level cache_level)
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{
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struct drm_device *dev = obj->base.dev;
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unsigned int agp_type = cache_level_to_agp_type(dev, cache_level);
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intel_gtt_insert_sg_entries(&obj->pages,
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obj->gtt_space->start >> PAGE_SHIFT,
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agp_type);
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obj->has_global_gtt_mapping = 1;
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}
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void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj)
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{
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intel_gtt_clear_range(obj->gtt_space->start >> PAGE_SHIFT,
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obj->base.size >> PAGE_SHIFT);
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obj->has_global_gtt_mapping = 0;
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}
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void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
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{
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struct drm_device *dev = obj->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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bool interruptible;
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interruptible = do_idling(dev_priv);
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// if (!obj->has_dma_mapping)
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// dma_unmap_sg(&dev->pdev->dev,
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// obj->pages->sgl, obj->pages->nents,
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// PCI_DMA_BIDIRECTIONAL);
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undo_idling(dev_priv, interruptible);
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}
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static void i915_gtt_color_adjust(struct drm_mm_node *node,
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unsigned long color,
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unsigned long *start,
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unsigned long *end)
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{
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if (node->color != color)
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*start += 4096;
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if (!list_empty(&node->node_list)) {
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node = list_entry(node->node_list.next,
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struct drm_mm_node,
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node_list);
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if (node->allocated && node->color != color)
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*end -= 4096;
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}
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}
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void i915_gem_init_global_gtt(struct drm_device *dev,
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unsigned long start,
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unsigned long mappable_end,
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unsigned long end)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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/* Substract the guard page ... */
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drm_mm_init(&dev_priv->mm.gtt_space, start, end - start - PAGE_SIZE);
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if (!HAS_LLC(dev))
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dev_priv->mm.gtt_space.color_adjust = i915_gtt_color_adjust;
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dev_priv->mm.gtt_start = start;
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dev_priv->mm.gtt_mappable_end = mappable_end;
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dev_priv->mm.gtt_end = end;
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dev_priv->mm.gtt_total = end - start;
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dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start;
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/* ... but ensure that we clear the entire range. */
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intel_gtt_clear_range(start / PAGE_SIZE, (end-start) / PAGE_SIZE);
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}
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