332 lines
9.3 KiB
C
332 lines
9.3 KiB
C
#ifndef _ASM_X86_MSR_H
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#define _ASM_X86_MSR_H
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#include "msr-index.h"
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#ifndef __ASSEMBLY__
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#include <asm/asm.h>
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#include <asm/errno.h>
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#include <asm/cpumask.h>
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#include <uapi/asm/msr.h>
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struct msr {
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union {
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struct {
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u32 l;
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u32 h;
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};
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u64 q;
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};
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};
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struct msr_info {
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u32 msr_no;
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struct msr reg;
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struct msr *msrs;
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int err;
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};
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struct msr_regs_info {
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u32 *regs;
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int err;
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};
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struct saved_msr {
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bool valid;
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struct msr_info info;
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};
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struct saved_msrs {
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unsigned int num;
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struct saved_msr *array;
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};
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/*
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* both i386 and x86_64 returns 64-bit value in edx:eax, but gcc's "A"
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* constraint has different meanings. For i386, "A" means exactly
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* edx:eax, while for x86_64 it doesn't mean rdx:rax or edx:eax. Instead,
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* it means rax *or* rdx.
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*/
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#ifdef CONFIG_X86_64
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/* Using 64-bit values saves one instruction clearing the high half of low */
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#define DECLARE_ARGS(val, low, high) unsigned long low, high
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#define EAX_EDX_VAL(val, low, high) ((low) | (high) << 32)
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#define EAX_EDX_RET(val, low, high) "=a" (low), "=d" (high)
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#else
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#define DECLARE_ARGS(val, low, high) unsigned long long val
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#define EAX_EDX_VAL(val, low, high) (val)
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#define EAX_EDX_RET(val, low, high) "=A" (val)
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#endif
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#ifdef CONFIG_TRACEPOINTS
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/*
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* Be very careful with includes. This header is prone to include loops.
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*/
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#include <asm/atomic.h>
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#include <linux/tracepoint-defs.h>
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extern struct tracepoint __tracepoint_read_msr;
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extern struct tracepoint __tracepoint_write_msr;
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extern struct tracepoint __tracepoint_rdpmc;
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#define msr_tracepoint_active(t) static_key_false(&(t).key)
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extern void do_trace_write_msr(unsigned msr, u64 val, int failed);
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extern void do_trace_read_msr(unsigned msr, u64 val, int failed);
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extern void do_trace_rdpmc(unsigned msr, u64 val, int failed);
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#else
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#define msr_tracepoint_active(t) false
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static inline void do_trace_write_msr(unsigned msr, u64 val, int failed) {}
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static inline void do_trace_read_msr(unsigned msr, u64 val, int failed) {}
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static inline void do_trace_rdpmc(unsigned msr, u64 val, int failed) {}
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#endif
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static inline unsigned long long native_read_msr(unsigned int msr)
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{
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DECLARE_ARGS(val, low, high);
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asm volatile("rdmsr" : EAX_EDX_RET(val, low, high) : "c" (msr));
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if (msr_tracepoint_active(__tracepoint_read_msr))
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do_trace_read_msr(msr, EAX_EDX_VAL(val, low, high), 0);
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return EAX_EDX_VAL(val, low, high);
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}
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static inline unsigned long long native_read_msr_safe(unsigned int msr,
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int *err)
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{
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#warning "FIXME: native_read_msr_safe always return err = 0!"
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*err = 0;
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return native_read_msr(msr);
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}
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static inline void native_write_msr(unsigned int msr,
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unsigned low, unsigned high)
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{
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asm volatile("wrmsr" : : "c" (msr), "a"(low), "d" (high) : "memory");
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if (msr_tracepoint_active(__tracepoint_write_msr))
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do_trace_write_msr(msr, ((u64)high << 32 | low), 0);
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}
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/* Can be uninlined because referenced by paravirt */
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notrace static inline int native_write_msr_safe(unsigned int msr,
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unsigned low, unsigned high)
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{
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#warning "FIXME: native_write_msr_safe always return 0!"
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native_write_msr(msr, low, high);
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return 0;
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}
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extern int rdmsr_safe_regs(u32 regs[8]);
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extern int wrmsr_safe_regs(u32 regs[8]);
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/**
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* rdtsc() - returns the current TSC without ordering constraints
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*
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* rdtsc() returns the result of RDTSC as a 64-bit integer. The
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* only ordering constraint it supplies is the ordering implied by
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* "asm volatile": it will put the RDTSC in the place you expect. The
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* CPU can and will speculatively execute that RDTSC, though, so the
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* results can be non-monotonic if compared on different CPUs.
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*/
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static __always_inline unsigned long long rdtsc(void)
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{
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DECLARE_ARGS(val, low, high);
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asm volatile("rdtsc" : EAX_EDX_RET(val, low, high));
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return EAX_EDX_VAL(val, low, high);
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}
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/**
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* rdtsc_ordered() - read the current TSC in program order
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*
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* rdtsc_ordered() returns the result of RDTSC as a 64-bit integer.
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* It is ordered like a load to a global in-memory counter. It should
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* be impossible to observe non-monotonic rdtsc_unordered() behavior
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* across multiple CPUs as long as the TSC is synced.
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*/
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static __always_inline unsigned long long rdtsc_ordered(void)
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{
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/*
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* The RDTSC instruction is not ordered relative to memory
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* access. The Intel SDM and the AMD APM are both vague on this
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* point, but empirically an RDTSC instruction can be
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* speculatively executed before prior loads. An RDTSC
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* immediately after an appropriate barrier appears to be
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* ordered as a normal load, that is, it provides the same
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* ordering guarantees as reading from a global memory location
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* that some other imaginary CPU is updating continuously with a
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* time stamp.
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*/
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alternative_2("", "mfence", X86_FEATURE_MFENCE_RDTSC,
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"lfence", X86_FEATURE_LFENCE_RDTSC);
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return rdtsc();
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}
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/* Deprecated, keep it for a cycle for easier merging: */
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#define rdtscll(now) do { (now) = rdtsc_ordered(); } while (0)
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static inline unsigned long long native_read_pmc(int counter)
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{
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DECLARE_ARGS(val, low, high);
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asm volatile("rdpmc" : EAX_EDX_RET(val, low, high) : "c" (counter));
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if (msr_tracepoint_active(__tracepoint_rdpmc))
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do_trace_rdpmc(counter, EAX_EDX_VAL(val, low, high), 0);
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return EAX_EDX_VAL(val, low, high);
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}
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#ifdef CONFIG_PARAVIRT
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#include <asm/paravirt.h>
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#else
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#include <linux/errno.h>
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/*
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* Access to machine-specific registers (available on 586 and better only)
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* Note: the rd* operations modify the parameters directly (without using
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* pointer indirection), this allows gcc to optimize better
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*/
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#define rdmsr(msr, low, high) \
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do { \
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u64 __val = native_read_msr((msr)); \
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(void)((low) = (u32)__val); \
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(void)((high) = (u32)(__val >> 32)); \
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} while (0)
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static inline void wrmsr(unsigned msr, unsigned low, unsigned high)
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{
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native_write_msr(msr, low, high);
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}
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#define rdmsrl(msr, val) \
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((val) = native_read_msr((msr)))
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static inline void wrmsrl(unsigned msr, u64 val)
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{
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native_write_msr(msr, (u32)(val & 0xffffffffULL), (u32)(val >> 32));
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}
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/* wrmsr with exception handling */
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static inline int wrmsr_safe(unsigned msr, unsigned low, unsigned high)
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{
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return native_write_msr_safe(msr, low, high);
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}
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/* rdmsr with exception handling */
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#define rdmsr_safe(msr, low, high) \
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({ \
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int __err; \
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u64 __val = native_read_msr_safe((msr), &__err); \
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(*low) = (u32)__val; \
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(*high) = (u32)(__val >> 32); \
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__err; \
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})
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static inline int rdmsrl_safe(unsigned msr, unsigned long long *p)
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{
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int err;
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*p = native_read_msr_safe(msr, &err);
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return err;
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}
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#define rdpmc(counter, low, high) \
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do { \
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u64 _l = native_read_pmc((counter)); \
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(low) = (u32)_l; \
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(high) = (u32)(_l >> 32); \
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} while (0)
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#define rdpmcl(counter, val) ((val) = native_read_pmc(counter))
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#endif /* !CONFIG_PARAVIRT */
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/*
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* 64-bit version of wrmsr_safe():
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*/
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static inline int wrmsrl_safe(u32 msr, u64 val)
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{
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return wrmsr_safe(msr, (u32)val, (u32)(val >> 32));
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}
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#define write_tsc(low, high) wrmsr(MSR_IA32_TSC, (low), (high))
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#define write_rdtscp_aux(val) wrmsr(MSR_TSC_AUX, (val), 0)
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struct msr *msrs_alloc(void);
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void msrs_free(struct msr *msrs);
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int msr_set_bit(u32 msr, u8 bit);
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int msr_clear_bit(u32 msr, u8 bit);
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#ifdef CONFIG_SMP
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int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
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int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
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int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q);
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int wrmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 q);
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void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs);
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void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs);
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int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
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int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
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int rdmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q);
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int wrmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q);
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int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]);
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int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]);
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#else /* CONFIG_SMP */
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static inline int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
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{
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rdmsr(msr_no, *l, *h);
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return 0;
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}
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static inline int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
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{
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wrmsr(msr_no, l, h);
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return 0;
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}
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static inline int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q)
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{
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rdmsrl(msr_no, *q);
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return 0;
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}
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static inline int wrmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 q)
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{
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wrmsrl(msr_no, q);
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return 0;
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}
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static inline void rdmsr_on_cpus(const struct cpumask *m, u32 msr_no,
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struct msr *msrs)
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{
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rdmsr_on_cpu(0, msr_no, &(msrs[0].l), &(msrs[0].h));
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}
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static inline void wrmsr_on_cpus(const struct cpumask *m, u32 msr_no,
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struct msr *msrs)
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{
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wrmsr_on_cpu(0, msr_no, msrs[0].l, msrs[0].h);
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}
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static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no,
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u32 *l, u32 *h)
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{
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return rdmsr_safe(msr_no, l, h);
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}
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static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
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{
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return wrmsr_safe(msr_no, l, h);
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}
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static inline int rdmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q)
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{
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return rdmsrl_safe(msr_no, q);
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}
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static inline int wrmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q)
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{
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return wrmsrl_safe(msr_no, q);
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}
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static inline int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8])
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{
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return rdmsr_safe_regs(regs);
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}
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static inline int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8])
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{
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return wrmsr_safe_regs(regs);
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}
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#endif /* CONFIG_SMP */
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_X86_MSR_H */
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