570 lines
17 KiB
C
570 lines
17 KiB
C
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typedef void *pointer;
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typedef unsigned int memType;
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typedef struct { float hi, lo; } range;
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typedef enum
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{
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CHIP_FAMILY_UNKNOW,
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CHIP_FAMILY_LEGACY,
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CHIP_FAMILY_RADEON,
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CHIP_FAMILY_RV100,
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CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/
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CHIP_FAMILY_RV200,
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CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), RS250 (IGP 7000) */
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CHIP_FAMILY_R200,
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CHIP_FAMILY_RV250,
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CHIP_FAMILY_RS300, /* RS300/RS350 */
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CHIP_FAMILY_RV280,
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CHIP_FAMILY_R300,
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CHIP_FAMILY_R350,
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CHIP_FAMILY_RV350,
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CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */
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CHIP_FAMILY_R420, /* R420/R423/M18 */
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CHIP_FAMILY_RV410, /* RV410, M26 */
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CHIP_FAMILY_RS400, /* xpress 200, 200m (RS400) Intel */
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CHIP_FAMILY_RS480, /* xpress 200, 200m (RS410/480/482/485) AMD */
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CHIP_FAMILY_RV515, /* rv515 */
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CHIP_FAMILY_R520, /* r520 */
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CHIP_FAMILY_RV530, /* rv530 */
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CHIP_FAMILY_R580, /* r580 */
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CHIP_FAMILY_RV560, /* rv560 */
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CHIP_FAMILY_RV570, /* rv570 */
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CHIP_FAMILY_RS600,
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CHIP_FAMILY_RS690,
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CHIP_FAMILY_RS740,
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CHIP_FAMILY_R600, /* r600 */
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CHIP_FAMILY_R630,
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CHIP_FAMILY_RV610,
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CHIP_FAMILY_RV630,
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CHIP_FAMILY_RV670,
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CHIP_FAMILY_RV620,
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CHIP_FAMILY_RV635,
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CHIP_FAMILY_RS780,
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CHIP_FAMILY_RV770,
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CHIP_FAMILY_LAST
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} RADEONChipFamily;
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#define IS_RV100_VARIANT ((rhdPtr->ChipFamily == CHIP_FAMILY_RV100) || \
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(rhdPtr->ChipFamily == CHIP_FAMILY_RV200) || \
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(rhdPtr->ChipFamily == CHIP_FAMILY_RS100) || \
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(rhdPtr->ChipFamily == CHIP_FAMILY_RS200) || \
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(rhdPtr->ChipFamily == CHIP_FAMILY_RV250) || \
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(rhdPtr->ChipFamily == CHIP_FAMILY_RV280) || \
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(rhdPtr->ChipFamily == CHIP_FAMILY_RS300))
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#define IS_R300_VARIANT ((info->ChipFamily == CHIP_FAMILY_R300) || \
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(info->ChipFamily == CHIP_FAMILY_RV350) || \
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(info->ChipFamily == CHIP_FAMILY_R350) || \
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(info->ChipFamily == CHIP_FAMILY_RV380) || \
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(info->ChipFamily == CHIP_FAMILY_R420) || \
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(info->ChipFamily == CHIP_FAMILY_RV410) || \
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(info->ChipFamily == CHIP_FAMILY_RS400) || \
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(info->ChipFamily == CHIP_FAMILY_RS480))
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#define IS_AVIVO_VARIANT ((info->ChipFamily >= CHIP_FAMILY_RV515))
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#define IS_DCE3_VARIANT ((info->ChipFamily >= CHIP_FAMILY_RV620))
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#define IS_R500_3D ((info->ChipFamily == CHIP_FAMILY_RV515) || \
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(info->ChipFamily == CHIP_FAMILY_R520) || \
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(info->ChipFamily == CHIP_FAMILY_RV530) || \
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(info->ChipFamily == CHIP_FAMILY_R580) || \
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(info->ChipFamily == CHIP_FAMILY_RV560) || \
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(info->ChipFamily == CHIP_FAMILY_RV570))
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#define IS_R300_3D ((info->ChipFamily == CHIP_FAMILY_R300) || \
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(info->ChipFamily == CHIP_FAMILY_RV350) || \
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(info->ChipFamily == CHIP_FAMILY_R350) || \
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(info->ChipFamily == CHIP_FAMILY_RV380) || \
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(info->ChipFamily == CHIP_FAMILY_R420) || \
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(info->ChipFamily == CHIP_FAMILY_RV410) || \
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(info->ChipFamily == CHIP_FAMILY_RS690) || \
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(info->ChipFamily == CHIP_FAMILY_RS600) || \
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(info->ChipFamily == CHIP_FAMILY_RS740) || \
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(info->ChipFamily == CHIP_FAMILY_RS400) || \
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(info->ChipFamily == CHIP_FAMILY_RS480))
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typedef enum {
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CARD_PCI,
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CARD_AGP,
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CARD_PCIE
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} RADEONCardType;
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enum radeon_chip_flags {
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RADEON_FAMILY_MASK = 0x0000ffffUL,
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RADEON_FLAGS_MASK = 0xffff0000UL,
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RADEON_IS_MOBILITY = 0x00010000UL,
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RADEON_IS_IGP = 0x00020000UL,
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RADEON_SINGLE_CRTC = 0x00040000UL,
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RADEON_IS_AGP = 0x00080000UL,
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RADEON_HAS_HIERZ = 0x00100000UL,
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RADEON_IS_PCIE = 0x00200000UL,
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RADEON_NEW_MEMMAP = 0x00400000UL,
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RADEON_IS_PCI = 0x00800000UL,
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RADEON_IS_IGPGART = 0x01000000UL,
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};
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/*
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* Errata workarounds
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*/
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typedef enum {
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CHIP_ERRATA_R300_CG = 0x00000001,
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CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
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CHIP_ERRATA_PLL_DELAY = 0x00000004
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} RADEONErrata;
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typedef struct
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{
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u32_t pci_device_id;
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RADEONChipFamily chip_family;
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int mobility;
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int igp;
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int nocrtc2;
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int nointtvout;
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int singledac;
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} RADEONCardInfo;
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#define RHD_FB_BAR 0
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#define RHD_MMIO_BAR 2
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#define RHD_MEM_GART 1
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#define RHD_MEM_FB 2
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#define RADEON_DEFAULT_GART_SIZE 8 /* MB (must be 2^n and > 4MB) */
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#define R300_DEFAULT_GART_SIZE 32 /* MB (for R300 and above) */
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#define RADEON_DEFAULT_RING_SIZE 1 /* MB (must be page aligned) */
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#define RADEON_DEFAULT_BUFFER_SIZE 2 /* MB (must be page aligned) */
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#define RADEON_DEFAULT_GART_TEX_SIZE 1 /* MB (must be page aligned) */
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#define RADEON_DEFAULT_CP_TIMEOUT 100000 /* usecs */
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#define RADEON_DEFAULT_PCI_APER_SIZE 32 /* in MB */
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#define RADEON_PCIGART_TABLE_SIZE (32*1024)
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#define RADEON_IDLE_RETRY 16 /* Fall out of idle loops after this count */
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#define RADEON_TIMEOUT 4000000 /* Fall out of wait loops after this count */
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typedef struct RHDRec
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{
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addr_t MMIOBase;
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size_t MMIOMapSize;
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u32_t lock;
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addr_t FbFreeStart;
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addr_t FbFreeSize;
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/* visible part of the framebuffer */
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// unsigned int FbScanoutStart;
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// unsigned int FbScanoutSize;
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// u32_t LinearAddr; /* Frame buffer physical address */
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addr_t fbLocation; /* Frame buffer physical address */
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u32_t mc_fb_location;
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u32_t mc_agp_location;
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u32_t mc_agp_location_hi;
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size_t videoRam;
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u32_t MemCntl;
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u32_t BusCntl;
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unsigned long FbMapSize; /* Size of frame buffer, in bytes */
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unsigned long FbSecureSize; /* Size of secured fb area at end of
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framebuffer */
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RADEONChipFamily ChipFamily;
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RADEONErrata ChipErrata;
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char *chipset;
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Bool IsIGP;
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Bool IsMobility;
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Bool HasCRTC2;
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u32_t bus;
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u32_t devfn;
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PCITAG PciTag;
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u16_t PciDeviceID;
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u16_t subvendor_id;
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u16_t subdevice_id;
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RADEONCardType cardType; /* Current card is a PCI card */
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u32_t memBase[6];
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u32_t ioBase[6];
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u32_t memtype[6];
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u32_t memsize[6];
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struct mem_block *fb_heap;
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struct mem_block *gart_heap;
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u32_t displayWidth;
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u32_t displayHeight;
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u32_t gart_type;
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u32_t *gart_table;
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addr_t gart_table_dma;
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addr_t gart_vm_start;
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size_t gart_size;
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u32_t* ringBase;
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u32_t ring_rp;
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u32_t ring_wp;
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u32_t ringSize;
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u32_t ring_avail;
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u32_t bufSize;
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u32_t pciAperSize;
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u32_t CPusecTimeout;
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int __xmin;
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int __ymin;
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int __xmax;
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int __ymax;
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u32_t gui_control;
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u32_t dst_pitch_offset;
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u32_t surface_cntl;
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volatile u32_t host_rp __attribute__ ((aligned (128)));
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volatile u32_t scratch0 __attribute__ ((aligned (128)));
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volatile u32_t scratch1;
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volatile u32_t scratch2;
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volatile u32_t scratch3;
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volatile u32_t scratch4;
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volatile u32_t scratch5;
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volatile u32_t scratch6;
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volatile u32_t scratch7;
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int RamWidth __attribute__ ((aligned (128)));
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Bool IsDDR;
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int num_gb_pipes;
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int has_tcl;
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}RHD_t, *RHDPtr;
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extern RHD_t rhd;
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#define RADEON_CP_PACKET0 0x00000000
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#define RADEON_CP_PACKET1 0x40000000
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#define RADEON_CP_PACKET2 0x80000000
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#define RADEON_CP_PACKET3 0xC0000000
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# define RADEON_CNTL_PAINT 0x00009100
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# define RADEON_CNTL_BITBLT 0x00009200
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# define RADEON_CNTL_TRANBLT 0x00009C00
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# define RADEON_CNTL_PAINT_POLYLINE 0x00009500
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# define RADEON_CNTL_PAINT_MULTI 0x00009A00
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#if R300_PIO
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#define BEGIN_ACCEL(n) FIFOWait(n)
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#define FINISH_ACCEL()
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#define COMMIT_RING()
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#define OUT_ACCEL_REG(reg, val) OUTREG(reg, val)
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#else
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#define CP_PACKET0(reg, n) \
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(RADEON_CP_PACKET0 | ((n - 1 ) << 16) | ((reg) >> 2))
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#define CP_PACKET1(reg0, reg1) \
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(RADEON_CP_PACKET1 | (((reg1) >> 2) << 11) | ((reg0) >> 2))
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#define CP_PACKET2() \
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(RADEON_CP_PACKET2)
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#define CP_PACKET3( pkt, n ) \
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(RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
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#define BEGIN_RING( req ) do { \
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int avail = rhd.ring_rp-rhd.ring_wp; \
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if (avail <=0 ) avail+= 0x4000; \
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if( (req)+128 > avail) \
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{ \
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rhd.ring_rp = INREG(RADEON_CP_RB_RPTR); \
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avail = rhd.ring_rp-rhd.ring_wp; \
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if (avail <= 0) avail+= 0x4000; \
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if( (req)+128 > avail){ \
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unlock_device(); \
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return 0; \
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}; \
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} \
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ring = &rhd.ringBase[rhd.ring_wp]; \
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}while(0)
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#define ADVANCE_RING()
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#define OUT_RING( x ) *ring++ = (x)
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#define CP_REG(reg, val) \
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do { \
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ring[0] = CP_PACKET0((reg), 1); \
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ring[1] = (val); \
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ring+= 2; \
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} while (0)
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#define DRM_MEMORYBARRIER() __asm__ volatile("lock; addl $0,0(%%esp)" : : : "memory");
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#define COMMIT_RING() do { \
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rhd.ring_wp = (ring - rhd.ringBase) & 0x3FFF; \
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/* Flush writes to ring */ \
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DRM_MEMORYBARRIER(); \
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/*GET_RING_HEAD( dev_priv ); */ \
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OUTREG( RADEON_CP_RB_WPTR, rhd.ring_wp); \
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/* read from PCI bus to ensure correct posting */ \
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/* INREG( RADEON_CP_RB_RPTR ); */ \
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} while (0)
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#define BEGIN_ACCEL(n) BEGIN_RING(2*(n))
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#define FINISH_ACCEL() COMMIT_RING()
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#define OUT_ACCEL_REG(reg, val) CP_REG((reg), (val))
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#endif
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typedef struct {
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int token; /* id of the token */
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const char * name; /* token name */
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} SymTabRec, *SymTabPtr;
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extern inline void lock_device()
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{
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__asm__ __volatile__ (
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"call *__imp__WaitMutex"
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::"b" (&rhd.lock));
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};
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extern inline void unlock_device()
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{
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rhd.lock = 0;
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}
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extern inline void
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OUTREG8(u16_t offset, u8_t value)
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{
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*(volatile u8_t *)((u8_t *)(rhd.MMIOBase + offset)) = value;
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}
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extern inline u32_t INREG(u16_t offset)
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{
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return *(volatile u32_t *)((u8_t*)(rhd.MMIOBase + offset));
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}
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extern inline void OUTREG(u16_t offset, u32_t value)
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{
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*(volatile u32_t *)((u8_t *)(rhd.MMIOBase + offset)) = value;
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}
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//#define OUTREG( offset, value) \
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// *(volatile u32_t *)((u8_t *)(rhd.MMIOBase + (u32_t)(offset))) = (u32_t)value
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extern inline u32_t _RHDRegRead(RHDPtr rhdPtr, u16_t offset)
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{
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return *(volatile u32_t *)((u8_t*)(rhdPtr->MMIOBase + offset));
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}
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extern inline void
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MASKREG(u16_t offset, u32_t value, u32_t mask)
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{
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u32_t tmp;
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tmp = INREG(offset);
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tmp &= ~mask;
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tmp |= (value & mask);
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OUTREG(offset, tmp);
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};
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#define INPLL( addr) RADEONINPLL( addr)
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#define OUTPLL( addr, val) RADEONOUTPLL( addr, val)
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extern inline void
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_RHDRegWrite(RHDPtr rhdPtr, u16_t offset, u32_t value)
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{
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*(volatile u32_t *)((u8_t *)(rhdPtr->MMIOBase + offset)) = value;
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}
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extern inline void
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_RHDRegMask(RHDPtr rhdPtr, u16_t offset, u32_t value, u32_t mask)
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{
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u32_t tmp;
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tmp = _RHDRegRead(rhdPtr, offset);
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tmp &= ~mask;
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tmp |= (value & mask);
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_RHDRegWrite(rhdPtr, offset, tmp);
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};
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#define RHDRegRead(ptr, offset) _RHDRegRead((ptr)->rhdPtr, (offset))
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#define RHDRegWrite(ptr, offset, value) _RHDRegWrite((ptr)->rhdPtr, (offset), (value))
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#define RHDRegMask(ptr, offset, value, mask) _RHDRegMask((ptr)->rhdPtr, (offset), (value), (mask))
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#define RHDFUNC(ptr)
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#define DBG(x) x
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// #define DBG(x)
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#pragma pack (push,1)
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typedef struct s_cursor
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{
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u32_t magic; // 'CURS'
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void (*destroy)(struct s_cursor*); // destructor
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u32_t fd; // next object in list
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u32_t bk; // prev object in list
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u32_t pid; // owner id
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void *base; // allocated memory
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u32_t hot_x; // hotspot coords
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u32_t hot_y;
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}cursor_t;
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#pragma pack (pop)
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#define LOAD_FROM_FILE 0
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#define LOAD_FROM_MEM 1
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#define LOAD_INDIRECT 2
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cursor_t *create_cursor(u32_t pid, void *src, u32_t flags);
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void __stdcall copy_cursor(void *img, void *src);
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void destroy_cursor(cursor_t *cursor);
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void __destroy_cursor(cursor_t *cursor); // wrap
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void __stdcall r500_SelectCursor(cursor_t *cursor);
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void __stdcall r500_SetCursor(cursor_t *cursor, int x, int y);
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void __stdcall r500_CursorRestore(int x, int y);
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typedef struct {
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u32_t x ;
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u32_t y ;
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} xPointFixed;
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typedef u32_t xFixed_16_16;
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typedef xFixed_16_16 xFixed;
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#define XFIXED_BITS 16
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#define xFixedToInt(f) (int) ((f) >> XFIXED_BITS)
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#define IntToxFixed(i) ((xFixed) (i) << XFIXED_BITS)
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#define xFixedToFloat(f) (((float) (f)) / 65536)
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#define PICT_FORMAT(bpp,type,a,r,g,b) (((bpp) << 24) | \
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((type) << 16) | \
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((a) << 12) | \
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((r) << 8) | \
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((g) << 4) | \
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((b)))
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#define PICT_FORMAT_A(f) (((f) >> 12) & 0x0f)
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#define PICT_FORMAT_RGB(f) (((f) ) & 0xfff)
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#define PICT_TYPE_OTHER 0
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#define PICT_TYPE_A 1
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#define PICT_TYPE_ARGB 2
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#define PICT_TYPE_ABGR 3
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#define PICT_TYPE_COLOR 4
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#define PICT_TYPE_GRAY 5
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typedef enum _PictFormatShort {
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PICT_a8r8g8b8 = PICT_FORMAT(32,PICT_TYPE_ARGB,8,8,8,8),
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PICT_x8r8g8b8 = PICT_FORMAT(32,PICT_TYPE_ARGB,0,8,8,8),
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PICT_a8b8g8r8 = PICT_FORMAT(32,PICT_TYPE_ABGR,8,8,8,8),
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PICT_x8b8g8r8 = PICT_FORMAT(32,PICT_TYPE_ABGR,0,8,8,8),
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/* 24bpp formats */
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PICT_r8g8b8 = PICT_FORMAT(24,PICT_TYPE_ARGB,0,8,8,8),
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PICT_b8g8r8 = PICT_FORMAT(24,PICT_TYPE_ABGR,0,8,8,8),
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/* 16bpp formats */
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PICT_r5g6b5 = PICT_FORMAT(16,PICT_TYPE_ARGB,0,5,6,5),
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PICT_b5g6r5 = PICT_FORMAT(16,PICT_TYPE_ABGR,0,5,6,5),
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PICT_a1r5g5b5 = PICT_FORMAT(16,PICT_TYPE_ARGB,1,5,5,5),
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PICT_x1r5g5b5 = PICT_FORMAT(16,PICT_TYPE_ARGB,0,5,5,5),
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PICT_a1b5g5r5 = PICT_FORMAT(16,PICT_TYPE_ABGR,1,5,5,5),
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PICT_x1b5g5r5 = PICT_FORMAT(16,PICT_TYPE_ABGR,0,5,5,5),
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PICT_a4r4g4b4 = PICT_FORMAT(16,PICT_TYPE_ARGB,4,4,4,4),
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PICT_x4r4g4b4 = PICT_FORMAT(16,PICT_TYPE_ARGB,0,4,4,4),
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PICT_a4b4g4r4 = PICT_FORMAT(16,PICT_TYPE_ABGR,4,4,4,4),
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PICT_x4b4g4r4 = PICT_FORMAT(16,PICT_TYPE_ABGR,0,4,4,4),
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/* 8bpp formats */
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PICT_a8 = PICT_FORMAT(8,PICT_TYPE_A,8,0,0,0),
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PICT_r3g3b2 = PICT_FORMAT(8,PICT_TYPE_ARGB,0,3,3,2),
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PICT_b2g3r3 = PICT_FORMAT(8,PICT_TYPE_ABGR,0,3,3,2),
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PICT_a2r2g2b2 = PICT_FORMAT(8,PICT_TYPE_ARGB,2,2,2,2),
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PICT_a2b2g2r2 = PICT_FORMAT(8,PICT_TYPE_ABGR,2,2,2,2),
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PICT_c8 = PICT_FORMAT(8,PICT_TYPE_COLOR,0,0,0,0),
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PICT_g8 = PICT_FORMAT(8,PICT_TYPE_GRAY,0,0,0,0),
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PICT_x4a4 = PICT_FORMAT(8,PICT_TYPE_A,4,0,0,0),
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PICT_x4c4 = PICT_FORMAT(8,PICT_TYPE_COLOR,0,0,0,0),
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PICT_x4g4 = PICT_FORMAT(8,PICT_TYPE_GRAY,0,0,0,0),
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/* 4bpp formats */
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PICT_a4 = PICT_FORMAT(4,PICT_TYPE_A,4,0,0,0),
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PICT_r1g2b1 = PICT_FORMAT(4,PICT_TYPE_ARGB,0,1,2,1),
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PICT_b1g2r1 = PICT_FORMAT(4,PICT_TYPE_ABGR,0,1,2,1),
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PICT_a1r1g1b1 = PICT_FORMAT(4,PICT_TYPE_ARGB,1,1,1,1),
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PICT_a1b1g1r1 = PICT_FORMAT(4,PICT_TYPE_ABGR,1,1,1,1),
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PICT_c4 = PICT_FORMAT(4,PICT_TYPE_COLOR,0,0,0,0),
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PICT_g4 = PICT_FORMAT(4,PICT_TYPE_GRAY,0,0,0,0),
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/* 1bpp formats */
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PICT_a1 = PICT_FORMAT(1,PICT_TYPE_A,1,0,0,0),
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PICT_g1 = PICT_FORMAT(1,PICT_TYPE_GRAY,0,0,0,0),
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} PictFormatShort;
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void dump_mem();
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RHDPtr FindPciDevice();
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static __inline__ int drm_device_is_pcie(PCITAG pciTag);
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static void init_pipes(RHDPtr info);
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Bool init_cp(RHDPtr info);
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Bool RHDPreInit();
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void R5xx2DInit();
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int Init3DEngine(RHDPtr info);
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void init_gart(RHDPtr info);
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int rhdInitHeap(RHDPtr rhdPtr);
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