1131 lines
32 KiB
C
1131 lines
32 KiB
C
/*
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* Copyright © 2011 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Jesse Barnes <jbarnes@virtuousgeek.org>
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*
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* New plane/sprite handling.
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*
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* The older chips had a separate interface for programming plane related
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* registers; newer ones are much simpler and we can use the new DRM plane
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* support.
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*/
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#include <drm/drmP.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_fourcc.h>
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#include <drm/drm_rect.h>
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#include <drm/drm_atomic.h>
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#include <drm/drm_plane_helper.h>
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#include "intel_drv.h"
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#include <drm/i915_drm.h>
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#include "i915_drv.h"
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static bool
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format_is_yuv(uint32_t format)
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{
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switch (format) {
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case DRM_FORMAT_YUYV:
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case DRM_FORMAT_UYVY:
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case DRM_FORMAT_VYUY:
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case DRM_FORMAT_YVYU:
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return true;
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default:
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return false;
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}
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}
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static int usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
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int usecs)
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{
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/* paranoia */
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if (!adjusted_mode->crtc_htotal)
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return 1;
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return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
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1000 * adjusted_mode->crtc_htotal);
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}
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/**
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* intel_pipe_update_start() - start update of a set of display registers
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* @crtc: the crtc of which the registers are going to be updated
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* @start_vbl_count: vblank counter return pointer used for error checking
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*
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* Mark the start of an update to pipe registers that should be updated
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* atomically regarding vblank. If the next vblank will happens within
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* the next 100 us, this function waits until the vblank passes.
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*
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* After a successful call to this function, interrupts will be disabled
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* until a subsequent call to intel_pipe_update_end(). That is done to
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* avoid random delays. The value written to @start_vbl_count should be
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* supplied to intel_pipe_update_end() for error checking.
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*/
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void intel_pipe_update_start(struct intel_crtc *crtc)
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{
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struct drm_device *dev = crtc->base.dev;
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const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
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enum pipe pipe = crtc->pipe;
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long timeout = msecs_to_jiffies_timeout(1);
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int scanline, min, max, vblank_start;
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wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
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DEFINE_WAIT(wait);
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vblank_start = adjusted_mode->crtc_vblank_start;
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if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
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vblank_start = DIV_ROUND_UP(vblank_start, 2);
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/* FIXME needs to be calibrated sensibly */
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min = vblank_start - usecs_to_scanlines(adjusted_mode, 100);
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max = vblank_start - 1;
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local_irq_disable();
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if (min <= 0 || max <= 0)
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return;
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if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
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return;
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crtc->debug.min_vbl = min;
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crtc->debug.max_vbl = max;
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trace_i915_pipe_update_start(crtc);
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for (;;) {
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/*
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* prepare_to_wait() has a memory barrier, which guarantees
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* other CPUs can see the task state update by the time we
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* read the scanline.
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*/
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prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
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scanline = intel_get_crtc_scanline(crtc);
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if (scanline < min || scanline > max)
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break;
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if (timeout <= 0) {
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DRM_ERROR("Potential atomic update failure on pipe %c\n",
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pipe_name(crtc->pipe));
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break;
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}
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local_irq_enable();
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{
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unsigned long expire;
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expire = timeout + jiffies;
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WaitEventTimeout(wait.evnt, timeout);;
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timeout = expire - jiffies;
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timeout = timeout < 0 ? 0 : timeout;
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}
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local_irq_disable();
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}
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finish_wait(wq, &wait);
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drm_crtc_vblank_put(&crtc->base);
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crtc->debug.scanline_start = scanline;
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crtc->debug.start_vbl_time = ktime_get();
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crtc->debug.start_vbl_count =
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dev->driver->get_vblank_counter(dev, pipe);
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trace_i915_pipe_update_vblank_evaded(crtc);
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}
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/**
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* intel_pipe_update_end() - end update of a set of display registers
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* @crtc: the crtc of which the registers were updated
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* @start_vbl_count: start vblank counter (used for error checking)
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*
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* Mark the end of an update started with intel_pipe_update_start(). This
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* re-enables interrupts and verifies the update was actually completed
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* before a vblank using the value of @start_vbl_count.
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*/
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void intel_pipe_update_end(struct intel_crtc *crtc)
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{
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struct drm_device *dev = crtc->base.dev;
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enum pipe pipe = crtc->pipe;
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int scanline_end = intel_get_crtc_scanline(crtc);
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u32 end_vbl_count = dev->driver->get_vblank_counter(dev, pipe);
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ktime_t end_vbl_time = ktime_get();
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trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);
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local_irq_enable();
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if (crtc->debug.start_vbl_count &&
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crtc->debug.start_vbl_count != end_vbl_count) {
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DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
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pipe_name(pipe), crtc->debug.start_vbl_count,
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end_vbl_count,
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ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
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crtc->debug.min_vbl, crtc->debug.max_vbl,
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crtc->debug.scanline_start, scanline_end);
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}
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}
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static void
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skl_update_plane(struct drm_plane *drm_plane,
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const struct intel_crtc_state *crtc_state,
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const struct intel_plane_state *plane_state)
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{
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struct drm_device *dev = drm_plane->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_plane *intel_plane = to_intel_plane(drm_plane);
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struct drm_framebuffer *fb = plane_state->base.fb;
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struct drm_i915_gem_object *obj = intel_fb_obj(fb);
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const int pipe = intel_plane->pipe;
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const int plane = intel_plane->plane + 1;
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u32 plane_ctl, stride_div, stride;
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const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
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u32 surf_addr;
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u32 tile_height, plane_offset, plane_size;
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unsigned int rotation;
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int x_offset, y_offset;
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int crtc_x = plane_state->dst.x1;
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int crtc_y = plane_state->dst.y1;
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uint32_t crtc_w = drm_rect_width(&plane_state->dst);
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uint32_t crtc_h = drm_rect_height(&plane_state->dst);
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uint32_t x = plane_state->src.x1 >> 16;
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uint32_t y = plane_state->src.y1 >> 16;
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uint32_t src_w = drm_rect_width(&plane_state->src) >> 16;
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uint32_t src_h = drm_rect_height(&plane_state->src) >> 16;
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const struct intel_scaler *scaler =
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&crtc_state->scaler_state.scalers[plane_state->scaler_id];
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plane_ctl = PLANE_CTL_ENABLE |
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PLANE_CTL_PIPE_GAMMA_ENABLE |
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PLANE_CTL_PIPE_CSC_ENABLE;
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plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
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plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
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rotation = plane_state->base.rotation;
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plane_ctl |= skl_plane_ctl_rotation(rotation);
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stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
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fb->pixel_format);
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/* Sizes are 0 based */
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src_w--;
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src_h--;
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crtc_w--;
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crtc_h--;
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if (key->flags) {
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I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value);
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I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value);
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I915_WRITE(PLANE_KEYMSK(pipe, plane), key->channel_mask);
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}
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if (key->flags & I915_SET_COLORKEY_DESTINATION)
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plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
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else if (key->flags & I915_SET_COLORKEY_SOURCE)
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plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
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surf_addr = intel_plane_obj_offset(intel_plane, obj, 0);
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if (intel_rotation_90_or_270(rotation)) {
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int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
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/* stride: Surface height in tiles */
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tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
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stride = DIV_ROUND_UP(fb->height, tile_height);
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plane_size = (src_w << 16) | src_h;
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x_offset = stride * tile_height - y - (src_h + 1);
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y_offset = x;
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} else {
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stride = fb->pitches[0] / stride_div;
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plane_size = (src_h << 16) | src_w;
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x_offset = x;
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y_offset = y;
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}
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plane_offset = y_offset << 16 | x_offset;
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I915_WRITE(PLANE_OFFSET(pipe, plane), plane_offset);
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I915_WRITE(PLANE_STRIDE(pipe, plane), stride);
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I915_WRITE(PLANE_SIZE(pipe, plane), plane_size);
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/* program plane scaler */
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if (plane_state->scaler_id >= 0) {
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uint32_t ps_ctrl = 0;
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int scaler_id = plane_state->scaler_id;
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DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane,
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PS_PLANE_SEL(plane));
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ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane) | scaler->mode;
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I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
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I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
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I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
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I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id),
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((crtc_w + 1) << 16)|(crtc_h + 1));
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I915_WRITE(PLANE_POS(pipe, plane), 0);
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} else {
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I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x);
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}
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I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl);
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I915_WRITE(PLANE_SURF(pipe, plane), surf_addr);
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POSTING_READ(PLANE_SURF(pipe, plane));
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}
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static void
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skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
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{
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struct drm_device *dev = dplane->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_plane *intel_plane = to_intel_plane(dplane);
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const int pipe = intel_plane->pipe;
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const int plane = intel_plane->plane + 1;
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I915_WRITE(PLANE_CTL(pipe, plane), 0);
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I915_WRITE(PLANE_SURF(pipe, plane), 0);
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POSTING_READ(PLANE_SURF(pipe, plane));
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}
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static void
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chv_update_csc(struct intel_plane *intel_plane, uint32_t format)
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{
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struct drm_i915_private *dev_priv = intel_plane->base.dev->dev_private;
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int plane = intel_plane->plane;
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/* Seems RGB data bypasses the CSC always */
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if (!format_is_yuv(format))
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return;
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/*
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* BT.601 limited range YCbCr -> full range RGB
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*
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* |r| | 6537 4769 0| |cr |
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* |g| = |-3330 4769 -1605| x |y-64|
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* |b| | 0 4769 8263| |cb |
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*
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* Cb and Cr apparently come in as signed already, so no
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* need for any offset. For Y we need to remove the offset.
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*/
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I915_WRITE(SPCSCYGOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(-64));
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I915_WRITE(SPCSCCBOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
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I915_WRITE(SPCSCCROFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
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I915_WRITE(SPCSCC01(plane), SPCSC_C1(4769) | SPCSC_C0(6537));
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I915_WRITE(SPCSCC23(plane), SPCSC_C1(-3330) | SPCSC_C0(0));
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I915_WRITE(SPCSCC45(plane), SPCSC_C1(-1605) | SPCSC_C0(4769));
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I915_WRITE(SPCSCC67(plane), SPCSC_C1(4769) | SPCSC_C0(0));
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I915_WRITE(SPCSCC8(plane), SPCSC_C0(8263));
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I915_WRITE(SPCSCYGICLAMP(plane), SPCSC_IMAX(940) | SPCSC_IMIN(64));
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I915_WRITE(SPCSCCBICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
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I915_WRITE(SPCSCCRICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
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I915_WRITE(SPCSCYGOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
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I915_WRITE(SPCSCCBOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
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I915_WRITE(SPCSCCROCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
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}
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static void
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vlv_update_plane(struct drm_plane *dplane,
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const struct intel_crtc_state *crtc_state,
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const struct intel_plane_state *plane_state)
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{
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struct drm_device *dev = dplane->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_plane *intel_plane = to_intel_plane(dplane);
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struct drm_framebuffer *fb = plane_state->base.fb;
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struct drm_i915_gem_object *obj = intel_fb_obj(fb);
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int pipe = intel_plane->pipe;
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int plane = intel_plane->plane;
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u32 sprctl;
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u32 sprsurf_offset, linear_offset;
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int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
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const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
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int crtc_x = plane_state->dst.x1;
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int crtc_y = plane_state->dst.y1;
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uint32_t crtc_w = drm_rect_width(&plane_state->dst);
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uint32_t crtc_h = drm_rect_height(&plane_state->dst);
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uint32_t x = plane_state->src.x1 >> 16;
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uint32_t y = plane_state->src.y1 >> 16;
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uint32_t src_w = drm_rect_width(&plane_state->src) >> 16;
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uint32_t src_h = drm_rect_height(&plane_state->src) >> 16;
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sprctl = SP_ENABLE;
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switch (fb->pixel_format) {
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case DRM_FORMAT_YUYV:
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sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
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break;
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case DRM_FORMAT_YVYU:
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sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
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break;
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case DRM_FORMAT_UYVY:
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sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
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break;
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case DRM_FORMAT_VYUY:
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sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
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break;
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case DRM_FORMAT_RGB565:
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sprctl |= SP_FORMAT_BGR565;
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break;
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case DRM_FORMAT_XRGB8888:
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sprctl |= SP_FORMAT_BGRX8888;
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break;
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case DRM_FORMAT_ARGB8888:
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sprctl |= SP_FORMAT_BGRA8888;
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break;
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case DRM_FORMAT_XBGR2101010:
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sprctl |= SP_FORMAT_RGBX1010102;
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break;
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case DRM_FORMAT_ABGR2101010:
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sprctl |= SP_FORMAT_RGBA1010102;
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break;
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case DRM_FORMAT_XBGR8888:
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sprctl |= SP_FORMAT_RGBX8888;
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break;
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case DRM_FORMAT_ABGR8888:
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sprctl |= SP_FORMAT_RGBA8888;
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break;
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default:
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/*
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* If we get here one of the upper layers failed to filter
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* out the unsupported plane formats
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*/
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BUG();
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break;
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}
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/*
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* Enable gamma to match primary/cursor plane behaviour.
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* FIXME should be user controllable via propertiesa.
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*/
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sprctl |= SP_GAMMA_ENABLE;
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if (obj->tiling_mode != I915_TILING_NONE)
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sprctl |= SP_TILED;
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/* Sizes are 0 based */
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src_w--;
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src_h--;
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crtc_w--;
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crtc_h--;
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linear_offset = y * fb->pitches[0] + x * cpp;
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sprsurf_offset = intel_compute_tile_offset(dev_priv, &x, &y,
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fb->modifier[0], cpp,
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fb->pitches[0]);
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linear_offset -= sprsurf_offset;
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if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
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sprctl |= SP_ROTATE_180;
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x += src_w;
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y += src_h;
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linear_offset += src_h * fb->pitches[0] + src_w * cpp;
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}
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|
|
if (key->flags) {
|
|
I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
|
|
I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value);
|
|
I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask);
|
|
}
|
|
|
|
if (key->flags & I915_SET_COLORKEY_SOURCE)
|
|
sprctl |= SP_SOURCE_KEY;
|
|
|
|
if (IS_CHERRYVIEW(dev) && pipe == PIPE_B)
|
|
chv_update_csc(intel_plane, fb->pixel_format);
|
|
|
|
I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
|
|
I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
|
|
|
|
if (obj->tiling_mode != I915_TILING_NONE)
|
|
I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
|
|
else
|
|
I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
|
|
|
|
I915_WRITE(SPCONSTALPHA(pipe, plane), 0);
|
|
|
|
I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
|
|
I915_WRITE(SPCNTR(pipe, plane), sprctl);
|
|
I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) +
|
|
sprsurf_offset);
|
|
POSTING_READ(SPSURF(pipe, plane));
|
|
}
|
|
|
|
static void
|
|
vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
|
|
{
|
|
struct drm_device *dev = dplane->dev;
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct intel_plane *intel_plane = to_intel_plane(dplane);
|
|
int pipe = intel_plane->pipe;
|
|
int plane = intel_plane->plane;
|
|
|
|
I915_WRITE(SPCNTR(pipe, plane), 0);
|
|
|
|
I915_WRITE(SPSURF(pipe, plane), 0);
|
|
POSTING_READ(SPSURF(pipe, plane));
|
|
}
|
|
|
|
static void
|
|
ivb_update_plane(struct drm_plane *plane,
|
|
const struct intel_crtc_state *crtc_state,
|
|
const struct intel_plane_state *plane_state)
|
|
{
|
|
struct drm_device *dev = plane->dev;
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct intel_plane *intel_plane = to_intel_plane(plane);
|
|
struct drm_framebuffer *fb = plane_state->base.fb;
|
|
struct drm_i915_gem_object *obj = intel_fb_obj(fb);
|
|
enum pipe pipe = intel_plane->pipe;
|
|
u32 sprctl, sprscale = 0;
|
|
u32 sprsurf_offset, linear_offset;
|
|
int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
|
|
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
|
|
int crtc_x = plane_state->dst.x1;
|
|
int crtc_y = plane_state->dst.y1;
|
|
uint32_t crtc_w = drm_rect_width(&plane_state->dst);
|
|
uint32_t crtc_h = drm_rect_height(&plane_state->dst);
|
|
uint32_t x = plane_state->src.x1 >> 16;
|
|
uint32_t y = plane_state->src.y1 >> 16;
|
|
uint32_t src_w = drm_rect_width(&plane_state->src) >> 16;
|
|
uint32_t src_h = drm_rect_height(&plane_state->src) >> 16;
|
|
|
|
sprctl = SPRITE_ENABLE;
|
|
|
|
switch (fb->pixel_format) {
|
|
case DRM_FORMAT_XBGR8888:
|
|
sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
|
|
break;
|
|
case DRM_FORMAT_XRGB8888:
|
|
sprctl |= SPRITE_FORMAT_RGBX888;
|
|
break;
|
|
case DRM_FORMAT_YUYV:
|
|
sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
|
|
break;
|
|
case DRM_FORMAT_YVYU:
|
|
sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
|
|
break;
|
|
case DRM_FORMAT_UYVY:
|
|
sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
|
|
break;
|
|
case DRM_FORMAT_VYUY:
|
|
sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
|
|
break;
|
|
default:
|
|
BUG();
|
|
}
|
|
|
|
/*
|
|
* Enable gamma to match primary/cursor plane behaviour.
|
|
* FIXME should be user controllable via propertiesa.
|
|
*/
|
|
sprctl |= SPRITE_GAMMA_ENABLE;
|
|
|
|
if (obj->tiling_mode != I915_TILING_NONE)
|
|
sprctl |= SPRITE_TILED;
|
|
|
|
if (IS_HASWELL(dev) || IS_BROADWELL(dev))
|
|
sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE;
|
|
else
|
|
sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
|
|
|
|
if (IS_HASWELL(dev) || IS_BROADWELL(dev))
|
|
sprctl |= SPRITE_PIPE_CSC_ENABLE;
|
|
|
|
/* Sizes are 0 based */
|
|
src_w--;
|
|
src_h--;
|
|
crtc_w--;
|
|
crtc_h--;
|
|
|
|
if (crtc_w != src_w || crtc_h != src_h)
|
|
sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
|
|
|
|
linear_offset = y * fb->pitches[0] + x * cpp;
|
|
sprsurf_offset = intel_compute_tile_offset(dev_priv, &x, &y,
|
|
fb->modifier[0], cpp,
|
|
fb->pitches[0]);
|
|
linear_offset -= sprsurf_offset;
|
|
|
|
if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
|
|
sprctl |= SPRITE_ROTATE_180;
|
|
|
|
/* HSW and BDW does this automagically in hardware */
|
|
if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
|
|
x += src_w;
|
|
y += src_h;
|
|
linear_offset += src_h * fb->pitches[0] + src_w * cpp;
|
|
}
|
|
}
|
|
|
|
if (key->flags) {
|
|
I915_WRITE(SPRKEYVAL(pipe), key->min_value);
|
|
I915_WRITE(SPRKEYMAX(pipe), key->max_value);
|
|
I915_WRITE(SPRKEYMSK(pipe), key->channel_mask);
|
|
}
|
|
|
|
if (key->flags & I915_SET_COLORKEY_DESTINATION)
|
|
sprctl |= SPRITE_DEST_KEY;
|
|
else if (key->flags & I915_SET_COLORKEY_SOURCE)
|
|
sprctl |= SPRITE_SOURCE_KEY;
|
|
|
|
I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
|
|
I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
|
|
|
|
/* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
|
|
* register */
|
|
if (IS_HASWELL(dev) || IS_BROADWELL(dev))
|
|
I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
|
|
else if (obj->tiling_mode != I915_TILING_NONE)
|
|
I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
|
|
else
|
|
I915_WRITE(SPRLINOFF(pipe), linear_offset);
|
|
|
|
I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
|
|
if (intel_plane->can_scale)
|
|
I915_WRITE(SPRSCALE(pipe), sprscale);
|
|
I915_WRITE(SPRCTL(pipe), sprctl);
|
|
I915_WRITE(SPRSURF(pipe),
|
|
i915_gem_obj_ggtt_offset(obj) + sprsurf_offset);
|
|
POSTING_READ(SPRSURF(pipe));
|
|
}
|
|
|
|
static void
|
|
ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
|
|
{
|
|
struct drm_device *dev = plane->dev;
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct intel_plane *intel_plane = to_intel_plane(plane);
|
|
int pipe = intel_plane->pipe;
|
|
|
|
I915_WRITE(SPRCTL(pipe), 0);
|
|
/* Can't leave the scaler enabled... */
|
|
if (intel_plane->can_scale)
|
|
I915_WRITE(SPRSCALE(pipe), 0);
|
|
|
|
I915_WRITE(SPRSURF(pipe), 0);
|
|
POSTING_READ(SPRSURF(pipe));
|
|
}
|
|
|
|
static void
|
|
ilk_update_plane(struct drm_plane *plane,
|
|
const struct intel_crtc_state *crtc_state,
|
|
const struct intel_plane_state *plane_state)
|
|
{
|
|
struct drm_device *dev = plane->dev;
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct intel_plane *intel_plane = to_intel_plane(plane);
|
|
struct drm_framebuffer *fb = plane_state->base.fb;
|
|
struct drm_i915_gem_object *obj = intel_fb_obj(fb);
|
|
int pipe = intel_plane->pipe;
|
|
u32 dvscntr, dvsscale;
|
|
u32 dvssurf_offset, linear_offset;
|
|
int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
|
|
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
|
|
int crtc_x = plane_state->dst.x1;
|
|
int crtc_y = plane_state->dst.y1;
|
|
uint32_t crtc_w = drm_rect_width(&plane_state->dst);
|
|
uint32_t crtc_h = drm_rect_height(&plane_state->dst);
|
|
uint32_t x = plane_state->src.x1 >> 16;
|
|
uint32_t y = plane_state->src.y1 >> 16;
|
|
uint32_t src_w = drm_rect_width(&plane_state->src) >> 16;
|
|
uint32_t src_h = drm_rect_height(&plane_state->src) >> 16;
|
|
|
|
dvscntr = DVS_ENABLE;
|
|
|
|
switch (fb->pixel_format) {
|
|
case DRM_FORMAT_XBGR8888:
|
|
dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
|
|
break;
|
|
case DRM_FORMAT_XRGB8888:
|
|
dvscntr |= DVS_FORMAT_RGBX888;
|
|
break;
|
|
case DRM_FORMAT_YUYV:
|
|
dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
|
|
break;
|
|
case DRM_FORMAT_YVYU:
|
|
dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
|
|
break;
|
|
case DRM_FORMAT_UYVY:
|
|
dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
|
|
break;
|
|
case DRM_FORMAT_VYUY:
|
|
dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
|
|
break;
|
|
default:
|
|
BUG();
|
|
}
|
|
|
|
/*
|
|
* Enable gamma to match primary/cursor plane behaviour.
|
|
* FIXME should be user controllable via propertiesa.
|
|
*/
|
|
dvscntr |= DVS_GAMMA_ENABLE;
|
|
|
|
if (obj->tiling_mode != I915_TILING_NONE)
|
|
dvscntr |= DVS_TILED;
|
|
|
|
if (IS_GEN6(dev))
|
|
dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
|
|
|
|
/* Sizes are 0 based */
|
|
src_w--;
|
|
src_h--;
|
|
crtc_w--;
|
|
crtc_h--;
|
|
|
|
dvsscale = 0;
|
|
if (crtc_w != src_w || crtc_h != src_h)
|
|
dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
|
|
|
|
linear_offset = y * fb->pitches[0] + x * cpp;
|
|
dvssurf_offset = intel_compute_tile_offset(dev_priv, &x, &y,
|
|
fb->modifier[0], cpp,
|
|
fb->pitches[0]);
|
|
linear_offset -= dvssurf_offset;
|
|
|
|
if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
|
|
dvscntr |= DVS_ROTATE_180;
|
|
|
|
x += src_w;
|
|
y += src_h;
|
|
linear_offset += src_h * fb->pitches[0] + src_w * cpp;
|
|
}
|
|
|
|
if (key->flags) {
|
|
I915_WRITE(DVSKEYVAL(pipe), key->min_value);
|
|
I915_WRITE(DVSKEYMAX(pipe), key->max_value);
|
|
I915_WRITE(DVSKEYMSK(pipe), key->channel_mask);
|
|
}
|
|
|
|
if (key->flags & I915_SET_COLORKEY_DESTINATION)
|
|
dvscntr |= DVS_DEST_KEY;
|
|
else if (key->flags & I915_SET_COLORKEY_SOURCE)
|
|
dvscntr |= DVS_SOURCE_KEY;
|
|
|
|
I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
|
|
I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
|
|
|
|
if (obj->tiling_mode != I915_TILING_NONE)
|
|
I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
|
|
else
|
|
I915_WRITE(DVSLINOFF(pipe), linear_offset);
|
|
|
|
I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
|
|
I915_WRITE(DVSSCALE(pipe), dvsscale);
|
|
I915_WRITE(DVSCNTR(pipe), dvscntr);
|
|
I915_WRITE(DVSSURF(pipe),
|
|
i915_gem_obj_ggtt_offset(obj) + dvssurf_offset);
|
|
POSTING_READ(DVSSURF(pipe));
|
|
}
|
|
|
|
static void
|
|
ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
|
|
{
|
|
struct drm_device *dev = plane->dev;
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct intel_plane *intel_plane = to_intel_plane(plane);
|
|
int pipe = intel_plane->pipe;
|
|
|
|
I915_WRITE(DVSCNTR(pipe), 0);
|
|
/* Disable the scaler */
|
|
I915_WRITE(DVSSCALE(pipe), 0);
|
|
|
|
I915_WRITE(DVSSURF(pipe), 0);
|
|
POSTING_READ(DVSSURF(pipe));
|
|
}
|
|
|
|
static int
|
|
intel_check_sprite_plane(struct drm_plane *plane,
|
|
struct intel_crtc_state *crtc_state,
|
|
struct intel_plane_state *state)
|
|
{
|
|
struct drm_device *dev = plane->dev;
|
|
struct drm_crtc *crtc = state->base.crtc;
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
|
struct intel_plane *intel_plane = to_intel_plane(plane);
|
|
struct drm_framebuffer *fb = state->base.fb;
|
|
int crtc_x, crtc_y;
|
|
unsigned int crtc_w, crtc_h;
|
|
uint32_t src_x, src_y, src_w, src_h;
|
|
struct drm_rect *src = &state->src;
|
|
struct drm_rect *dst = &state->dst;
|
|
const struct drm_rect *clip = &state->clip;
|
|
int hscale, vscale;
|
|
int max_scale, min_scale;
|
|
bool can_scale;
|
|
|
|
if (!fb) {
|
|
state->visible = false;
|
|
return 0;
|
|
}
|
|
|
|
/* Don't modify another pipe's plane */
|
|
if (intel_plane->pipe != intel_crtc->pipe) {
|
|
DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* FIXME check all gen limits */
|
|
if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) {
|
|
DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* setup can_scale, min_scale, max_scale */
|
|
if (INTEL_INFO(dev)->gen >= 9) {
|
|
/* use scaler when colorkey is not required */
|
|
if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
|
|
can_scale = 1;
|
|
min_scale = 1;
|
|
max_scale = skl_max_scale(intel_crtc, crtc_state);
|
|
} else {
|
|
can_scale = 0;
|
|
min_scale = DRM_PLANE_HELPER_NO_SCALING;
|
|
max_scale = DRM_PLANE_HELPER_NO_SCALING;
|
|
}
|
|
} else {
|
|
can_scale = intel_plane->can_scale;
|
|
max_scale = intel_plane->max_downscale << 16;
|
|
min_scale = intel_plane->can_scale ? 1 : (1 << 16);
|
|
}
|
|
|
|
/*
|
|
* FIXME the following code does a bunch of fuzzy adjustments to the
|
|
* coordinates and sizes. We probably need some way to decide whether
|
|
* more strict checking should be done instead.
|
|
*/
|
|
drm_rect_rotate(src, fb->width << 16, fb->height << 16,
|
|
state->base.rotation);
|
|
|
|
hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale);
|
|
BUG_ON(hscale < 0);
|
|
|
|
vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale);
|
|
BUG_ON(vscale < 0);
|
|
|
|
state->visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale);
|
|
|
|
crtc_x = dst->x1;
|
|
crtc_y = dst->y1;
|
|
crtc_w = drm_rect_width(dst);
|
|
crtc_h = drm_rect_height(dst);
|
|
|
|
if (state->visible) {
|
|
/* check again in case clipping clamped the results */
|
|
hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
|
|
if (hscale < 0) {
|
|
DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
|
|
drm_rect_debug_print("src: ", src, true);
|
|
drm_rect_debug_print("dst: ", dst, false);
|
|
|
|
return hscale;
|
|
}
|
|
|
|
vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
|
|
if (vscale < 0) {
|
|
DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
|
|
drm_rect_debug_print("src: ", src, true);
|
|
drm_rect_debug_print("dst: ", dst, false);
|
|
|
|
return vscale;
|
|
}
|
|
|
|
/* Make the source viewport size an exact multiple of the scaling factors. */
|
|
drm_rect_adjust_size(src,
|
|
drm_rect_width(dst) * hscale - drm_rect_width(src),
|
|
drm_rect_height(dst) * vscale - drm_rect_height(src));
|
|
|
|
drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16,
|
|
state->base.rotation);
|
|
|
|
/* sanity check to make sure the src viewport wasn't enlarged */
|
|
WARN_ON(src->x1 < (int) state->base.src_x ||
|
|
src->y1 < (int) state->base.src_y ||
|
|
src->x2 > (int) state->base.src_x + state->base.src_w ||
|
|
src->y2 > (int) state->base.src_y + state->base.src_h);
|
|
|
|
/*
|
|
* Hardware doesn't handle subpixel coordinates.
|
|
* Adjust to (macro)pixel boundary, but be careful not to
|
|
* increase the source viewport size, because that could
|
|
* push the downscaling factor out of bounds.
|
|
*/
|
|
src_x = src->x1 >> 16;
|
|
src_w = drm_rect_width(src) >> 16;
|
|
src_y = src->y1 >> 16;
|
|
src_h = drm_rect_height(src) >> 16;
|
|
|
|
if (format_is_yuv(fb->pixel_format)) {
|
|
src_x &= ~1;
|
|
src_w &= ~1;
|
|
|
|
/*
|
|
* Must keep src and dst the
|
|
* same if we can't scale.
|
|
*/
|
|
if (!can_scale)
|
|
crtc_w &= ~1;
|
|
|
|
if (crtc_w == 0)
|
|
state->visible = false;
|
|
}
|
|
}
|
|
|
|
/* Check size restrictions when scaling */
|
|
if (state->visible && (src_w != crtc_w || src_h != crtc_h)) {
|
|
unsigned int width_bytes;
|
|
int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
|
|
|
|
WARN_ON(!can_scale);
|
|
|
|
/* FIXME interlacing min height is 6 */
|
|
|
|
if (crtc_w < 3 || crtc_h < 3)
|
|
state->visible = false;
|
|
|
|
if (src_w < 3 || src_h < 3)
|
|
state->visible = false;
|
|
|
|
width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
|
|
|
|
if (INTEL_INFO(dev)->gen < 9 && (src_w > 2048 || src_h > 2048 ||
|
|
width_bytes > 4096 || fb->pitches[0] > 4096)) {
|
|
DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
if (state->visible) {
|
|
src->x1 = src_x << 16;
|
|
src->x2 = (src_x + src_w) << 16;
|
|
src->y1 = src_y << 16;
|
|
src->y2 = (src_y + src_h) << 16;
|
|
}
|
|
|
|
dst->x1 = crtc_x;
|
|
dst->x2 = crtc_x + crtc_w;
|
|
dst->y1 = crtc_y;
|
|
dst->y2 = crtc_y + crtc_h;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv)
|
|
{
|
|
struct drm_intel_sprite_colorkey *set = data;
|
|
struct drm_plane *plane;
|
|
struct drm_plane_state *plane_state;
|
|
struct drm_atomic_state *state;
|
|
struct drm_modeset_acquire_ctx ctx;
|
|
int ret = 0;
|
|
|
|
/* Make sure we don't try to enable both src & dest simultaneously */
|
|
if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
|
|
return -EINVAL;
|
|
|
|
if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
|
|
set->flags & I915_SET_COLORKEY_DESTINATION)
|
|
return -EINVAL;
|
|
|
|
plane = drm_plane_find(dev, set->plane_id);
|
|
if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
|
|
return -ENOENT;
|
|
|
|
drm_modeset_acquire_init(&ctx, 0);
|
|
|
|
state = drm_atomic_state_alloc(plane->dev);
|
|
if (!state) {
|
|
ret = -ENOMEM;
|
|
goto out;
|
|
}
|
|
state->acquire_ctx = &ctx;
|
|
|
|
while (1) {
|
|
plane_state = drm_atomic_get_plane_state(state, plane);
|
|
ret = PTR_ERR_OR_ZERO(plane_state);
|
|
if (!ret) {
|
|
to_intel_plane_state(plane_state)->ckey = *set;
|
|
ret = drm_atomic_commit(state);
|
|
}
|
|
|
|
if (ret != -EDEADLK)
|
|
break;
|
|
|
|
drm_atomic_state_clear(state);
|
|
drm_modeset_backoff(&ctx);
|
|
}
|
|
|
|
if (ret)
|
|
drm_atomic_state_free(state);
|
|
|
|
out:
|
|
drm_modeset_drop_locks(&ctx);
|
|
drm_modeset_acquire_fini(&ctx);
|
|
return ret;
|
|
}
|
|
|
|
static const uint32_t ilk_plane_formats[] = {
|
|
DRM_FORMAT_XRGB8888,
|
|
DRM_FORMAT_YUYV,
|
|
DRM_FORMAT_YVYU,
|
|
DRM_FORMAT_UYVY,
|
|
DRM_FORMAT_VYUY,
|
|
};
|
|
|
|
static const uint32_t snb_plane_formats[] = {
|
|
DRM_FORMAT_XBGR8888,
|
|
DRM_FORMAT_XRGB8888,
|
|
DRM_FORMAT_YUYV,
|
|
DRM_FORMAT_YVYU,
|
|
DRM_FORMAT_UYVY,
|
|
DRM_FORMAT_VYUY,
|
|
};
|
|
|
|
static const uint32_t vlv_plane_formats[] = {
|
|
DRM_FORMAT_RGB565,
|
|
DRM_FORMAT_ABGR8888,
|
|
DRM_FORMAT_ARGB8888,
|
|
DRM_FORMAT_XBGR8888,
|
|
DRM_FORMAT_XRGB8888,
|
|
DRM_FORMAT_XBGR2101010,
|
|
DRM_FORMAT_ABGR2101010,
|
|
DRM_FORMAT_YUYV,
|
|
DRM_FORMAT_YVYU,
|
|
DRM_FORMAT_UYVY,
|
|
DRM_FORMAT_VYUY,
|
|
};
|
|
|
|
static uint32_t skl_plane_formats[] = {
|
|
DRM_FORMAT_RGB565,
|
|
DRM_FORMAT_ABGR8888,
|
|
DRM_FORMAT_ARGB8888,
|
|
DRM_FORMAT_XBGR8888,
|
|
DRM_FORMAT_XRGB8888,
|
|
DRM_FORMAT_YUYV,
|
|
DRM_FORMAT_YVYU,
|
|
DRM_FORMAT_UYVY,
|
|
DRM_FORMAT_VYUY,
|
|
};
|
|
|
|
int
|
|
intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
|
|
{
|
|
struct intel_plane *intel_plane;
|
|
struct intel_plane_state *state;
|
|
unsigned long possible_crtcs;
|
|
const uint32_t *plane_formats;
|
|
int num_plane_formats;
|
|
int ret;
|
|
|
|
if (INTEL_INFO(dev)->gen < 5)
|
|
return -ENODEV;
|
|
|
|
intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
|
|
if (!intel_plane)
|
|
return -ENOMEM;
|
|
|
|
state = intel_create_plane_state(&intel_plane->base);
|
|
if (!state) {
|
|
kfree(intel_plane);
|
|
return -ENOMEM;
|
|
}
|
|
intel_plane->base.state = &state->base;
|
|
|
|
switch (INTEL_INFO(dev)->gen) {
|
|
case 5:
|
|
case 6:
|
|
intel_plane->can_scale = true;
|
|
intel_plane->max_downscale = 16;
|
|
intel_plane->update_plane = ilk_update_plane;
|
|
intel_plane->disable_plane = ilk_disable_plane;
|
|
|
|
if (IS_GEN6(dev)) {
|
|
plane_formats = snb_plane_formats;
|
|
num_plane_formats = ARRAY_SIZE(snb_plane_formats);
|
|
} else {
|
|
plane_formats = ilk_plane_formats;
|
|
num_plane_formats = ARRAY_SIZE(ilk_plane_formats);
|
|
}
|
|
break;
|
|
|
|
case 7:
|
|
case 8:
|
|
if (IS_IVYBRIDGE(dev)) {
|
|
intel_plane->can_scale = true;
|
|
intel_plane->max_downscale = 2;
|
|
} else {
|
|
intel_plane->can_scale = false;
|
|
intel_plane->max_downscale = 1;
|
|
}
|
|
|
|
if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
|
|
intel_plane->update_plane = vlv_update_plane;
|
|
intel_plane->disable_plane = vlv_disable_plane;
|
|
|
|
plane_formats = vlv_plane_formats;
|
|
num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
|
|
} else {
|
|
intel_plane->update_plane = ivb_update_plane;
|
|
intel_plane->disable_plane = ivb_disable_plane;
|
|
|
|
plane_formats = snb_plane_formats;
|
|
num_plane_formats = ARRAY_SIZE(snb_plane_formats);
|
|
}
|
|
break;
|
|
case 9:
|
|
intel_plane->can_scale = true;
|
|
intel_plane->update_plane = skl_update_plane;
|
|
intel_plane->disable_plane = skl_disable_plane;
|
|
state->scaler_id = -1;
|
|
|
|
plane_formats = skl_plane_formats;
|
|
num_plane_formats = ARRAY_SIZE(skl_plane_formats);
|
|
break;
|
|
default:
|
|
kfree(intel_plane);
|
|
return -ENODEV;
|
|
}
|
|
|
|
intel_plane->pipe = pipe;
|
|
intel_plane->plane = plane;
|
|
intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane);
|
|
intel_plane->check_plane = intel_check_sprite_plane;
|
|
possible_crtcs = (1 << pipe);
|
|
ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs,
|
|
&intel_plane_funcs,
|
|
plane_formats, num_plane_formats,
|
|
DRM_PLANE_TYPE_OVERLAY, NULL);
|
|
if (ret) {
|
|
kfree(intel_plane);
|
|
goto out;
|
|
}
|
|
|
|
intel_create_rotation_property(dev, intel_plane);
|
|
|
|
drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);
|
|
|
|
out:
|
|
return ret;
|
|
}
|