485 lines
11 KiB
C
485 lines
11 KiB
C
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#include <linux/list.h>
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#include <drm/drmP.h>
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#include "radeon_drm.h"
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#include "radeon.h"
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static struct drm_mm mm_gtt;
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static struct drm_mm mm_vram;
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int drm_mm_alloc(struct drm_mm *mm, size_t num_pages,
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struct drm_mm_node **node)
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{
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struct drm_mm_node *vm_node;
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int r;
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retry_pre_get:
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r = drm_mm_pre_get(mm);
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if (unlikely(r != 0))
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return r;
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vm_node = drm_mm_search_free(mm, num_pages, 0, 0);
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if (unlikely(vm_node == NULL)) {
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r = -ENOMEM;
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return r;
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}
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*node = drm_mm_get_block_atomic(vm_node, num_pages, 0);
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if (unlikely(*node == NULL)) {
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goto retry_pre_get;
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}
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return 0;
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};
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void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
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{
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u32 c = 0;
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rbo->placement.fpfn = 0;
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rbo->placement.lpfn = 0;
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rbo->placement.placement = rbo->placements;
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rbo->placement.busy_placement = rbo->placements;
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if (domain & RADEON_GEM_DOMAIN_VRAM)
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rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
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TTM_PL_FLAG_VRAM;
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if (domain & RADEON_GEM_DOMAIN_GTT)
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rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
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if (domain & RADEON_GEM_DOMAIN_CPU)
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rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
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if (!c)
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rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
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rbo->placement.num_placement = c;
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rbo->placement.num_busy_placement = c;
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}
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int radeon_bo_init(struct radeon_device *rdev)
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{
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int r;
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DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
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rdev->mc.mc_vram_size >> 20,
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(unsigned long long)rdev->mc.aper_size >> 20);
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DRM_INFO("RAM width %dbits %cDR\n",
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rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
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r = drm_mm_init(&mm_vram, 0xC00000 >> PAGE_SHIFT,
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((rdev->mc.real_vram_size - 0xC00000) >> PAGE_SHIFT));
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if (r) {
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DRM_ERROR("Failed initializing VRAM heap.\n");
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return r;
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};
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r = drm_mm_init(&mm_gtt, 0, rdev->mc.gtt_size >> PAGE_SHIFT);
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if (r) {
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DRM_ERROR("Failed initializing GTT heap.\n");
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return r;
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}
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return 0;
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}
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int radeon_bo_reserve(struct radeon_bo *bo, bool no_wait)
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{
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int r;
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bo->tbo.reserved.counter = 1;
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return 0;
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}
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void ttm_bo_unreserve(struct ttm_buffer_object *bo)
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{
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bo->reserved.counter = 1;
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}
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struct sg_table;
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int radeon_bo_create(struct radeon_device *rdev,
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unsigned long size, int byte_align, bool kernel, u32 domain,
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struct sg_table *sg, struct radeon_bo **bo_ptr)
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{
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struct radeon_bo *bo;
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enum ttm_bo_type type;
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size_t num_pages;
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struct drm_mm *mman;
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u32 bo_domain;
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int r;
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num_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
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size = num_pages << PAGE_SHIFT;
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if (num_pages == 0) {
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dbgprintf("Illegal buffer object size.\n");
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return -EINVAL;
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}
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if(domain & RADEON_GEM_DOMAIN_VRAM)
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{
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mman = &mm_vram;
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bo_domain = RADEON_GEM_DOMAIN_VRAM;
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}
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else if(domain & RADEON_GEM_DOMAIN_GTT)
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{
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mman = &mm_gtt;
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bo_domain = RADEON_GEM_DOMAIN_GTT;
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}
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else return -EINVAL;
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if (kernel) {
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type = ttm_bo_type_kernel;
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} else {
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type = ttm_bo_type_device;
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}
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*bo_ptr = NULL;
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bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
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if (bo == NULL)
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return -ENOMEM;
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r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
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if (unlikely(r)) {
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kfree(bo);
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return r;
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}
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bo->rdev = rdev;
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bo->gem_base.driver_private = NULL;
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bo->surface_reg = -1;
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bo->tbo.num_pages = num_pages;
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bo->domain = domain;
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INIT_LIST_HEAD(&bo->list);
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// radeon_ttm_placement_from_domain(bo, domain);
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/* Kernel allocation are uninterruptible */
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r = drm_mm_alloc(mman, num_pages, &bo->tbo.vm_node);
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if (unlikely(r != 0))
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return r;
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*bo_ptr = bo;
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return 0;
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}
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#define page_tabs 0xFDC00000 /* just another hack */
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int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
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{
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int r=0, i;
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if (bo->pin_count) {
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bo->pin_count++;
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if (gpu_addr)
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*gpu_addr = radeon_bo_gpu_offset(bo);
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return 0;
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}
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bo->tbo.offset = bo->tbo.vm_node->start << PAGE_SHIFT;
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if(bo->domain & RADEON_GEM_DOMAIN_VRAM)
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{
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bo->tbo.offset += (u64)bo->rdev->mc.vram_start;
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}
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else if (bo->domain & RADEON_GEM_DOMAIN_GTT)
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{
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u32_t *pagelist;
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bo->kptr = KernelAlloc( bo->tbo.num_pages << PAGE_SHIFT );
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// dbgprintf("kernel alloc %x\n", bo->kptr );
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pagelist = &((u32_t*)page_tabs)[(u32_t)bo->kptr >> 12];
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// dbgprintf("pagelist %x\n", pagelist);
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radeon_gart_bind(bo->rdev, bo->tbo.offset,
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bo->tbo.vm_node->size, pagelist, NULL);
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bo->tbo.offset += (u64)bo->rdev->mc.gtt_start;
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}
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else
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{
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DRM_ERROR("Unknown placement %x\n", bo->domain);
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bo->tbo.offset = -1;
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r = -1;
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};
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if (unlikely(r != 0)) {
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DRM_ERROR("radeon: failed to pin object.\n");
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}
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if (likely(r == 0)) {
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bo->pin_count = 1;
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if (gpu_addr != NULL)
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*gpu_addr = radeon_bo_gpu_offset(bo);
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}
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if (unlikely(r != 0))
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dev_err(bo->rdev->dev, "%p pin failed\n", bo);
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return r;
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};
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int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
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u64 *gpu_addr)
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{
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int r, i;
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if (bo->pin_count) {
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bo->pin_count++;
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if (gpu_addr)
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*gpu_addr = radeon_bo_gpu_offset(bo);
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if (max_offset != 0) {
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u64 domain_start;
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if (domain == RADEON_GEM_DOMAIN_VRAM)
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domain_start = bo->rdev->mc.vram_start;
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else
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domain_start = bo->rdev->mc.gtt_start;
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WARN_ON_ONCE(max_offset <
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(radeon_bo_gpu_offset(bo) - domain_start));
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}
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return 0;
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}
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// radeon_ttm_placement_from_domain(bo, domain);
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if (domain == RADEON_GEM_DOMAIN_VRAM) {
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/* force to pin into visible video ram */
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// bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
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bo->tbo.offset += (u64)bo->rdev->mc.vram_start;
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}
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else if (bo->domain & RADEON_GEM_DOMAIN_GTT)
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{
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u32_t *pagelist;
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bo->kptr = KernelAlloc( bo->tbo.num_pages << PAGE_SHIFT );
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dbgprintf("kernel alloc %x\n", bo->kptr );
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pagelist = &((u32_t*)page_tabs)[(u32_t)bo->kptr >> 12];
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dbgprintf("pagelist %x\n", pagelist);
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radeon_gart_bind(bo->rdev, bo->tbo.offset,
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bo->tbo.vm_node->size, pagelist, NULL);
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bo->tbo.offset += (u64)bo->rdev->mc.gtt_start;
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}
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else
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{
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DRM_ERROR("Unknown placement %x\n", bo->domain);
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bo->tbo.offset = -1;
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r = -1;
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};
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if (likely(r == 0)) {
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bo->pin_count = 1;
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if (gpu_addr != NULL)
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*gpu_addr = radeon_bo_gpu_offset(bo);
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}
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if (unlikely(r != 0))
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dev_err(bo->rdev->dev, "%p pin failed\n", bo);
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return r;
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}
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int radeon_bo_unpin(struct radeon_bo *bo)
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{
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int r = 0;
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if (!bo->pin_count) {
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dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
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return 0;
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}
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bo->pin_count--;
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if (bo->pin_count)
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return 0;
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if( bo->tbo.vm_node )
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{
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drm_mm_put_block(bo->tbo.vm_node);
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bo->tbo.vm_node = NULL;
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};
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return r;
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}
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int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
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{
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bool is_iomem;
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if (bo->kptr) {
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if (ptr) {
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*ptr = bo->kptr;
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}
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return 0;
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}
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if(bo->domain & RADEON_GEM_DOMAIN_VRAM)
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{
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bo->cpu_addr = bo->rdev->mc.aper_base +
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(bo->tbo.vm_node->start << PAGE_SHIFT);
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bo->kptr = (void*)MapIoMem(bo->cpu_addr,
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bo->tbo.vm_node->size << 12, PG_SW);
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}
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else
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{
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return -1;
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}
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if (ptr) {
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*ptr = bo->kptr;
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}
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return 0;
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}
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int radeon_bo_user_map(struct radeon_bo *bo, void **ptr)
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{
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bool is_iomem;
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if (bo->uptr) {
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if (ptr) {
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*ptr = bo->uptr;
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}
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return 0;
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}
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if(bo->domain & RADEON_GEM_DOMAIN_VRAM)
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{
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return -1;
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}
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else
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{
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bo->uptr = UserAlloc(bo->tbo.num_pages << PAGE_SHIFT);
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if(bo->uptr)
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{
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u32_t *src, *dst;
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int count;
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src = &((u32_t*)page_tabs)[(u32_t)bo->kptr >> 12];
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dst = &((u32_t*)page_tabs)[(u32_t)bo->uptr >> 12];
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count = bo->tbo.num_pages;
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while(count--)
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{
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*dst++ = (0xFFFFF000 & *src++) | 0x207 ; // map as shared page
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};
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}
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else
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return -1;
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}
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if (ptr) {
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*ptr = bo->uptr;
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}
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return 0;
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}
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void radeon_bo_kunmap(struct radeon_bo *bo)
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{
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if (bo->kptr == NULL)
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return;
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if (bo->domain & RADEON_GEM_DOMAIN_VRAM)
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{
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FreeKernelSpace(bo->kptr);
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}
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bo->kptr = NULL;
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}
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void radeon_bo_unref(struct radeon_bo **bo)
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{
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struct ttm_buffer_object *tbo;
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if ((*bo) == NULL)
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return;
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*bo = NULL;
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}
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void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
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uint32_t *tiling_flags,
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uint32_t *pitch)
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{
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// BUG_ON(!atomic_read(&bo->tbo.reserved));
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if (tiling_flags)
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*tiling_flags = bo->tiling_flags;
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if (pitch)
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*pitch = bo->pitch;
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}
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int radeon_fb_bo_create(struct radeon_device *rdev, struct drm_gem_object *gobj,
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unsigned long size, bool kernel, u32 domain,
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struct radeon_bo **bo_ptr)
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{
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enum ttm_bo_type type;
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struct radeon_bo *bo;
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struct drm_mm *mman;
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struct drm_mm_node *vm_node;
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size_t num_pages;
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u32 bo_domain;
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int r;
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num_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
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if (num_pages == 0) {
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dbgprintf("Illegal buffer object size.\n");
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return -EINVAL;
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}
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if( (domain & RADEON_GEM_DOMAIN_VRAM) !=
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RADEON_GEM_DOMAIN_VRAM )
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{
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return -EINVAL;
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};
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if (kernel) {
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type = ttm_bo_type_kernel;
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} else {
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type = ttm_bo_type_device;
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}
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*bo_ptr = NULL;
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bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
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if (bo == NULL)
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return -ENOMEM;
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bo->rdev = rdev;
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// bo->gobj = gobj;
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bo->surface_reg = -1;
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bo->tbo.num_pages = num_pages;
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bo->domain = domain;
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INIT_LIST_HEAD(&bo->list);
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// radeon_ttm_placement_from_domain(bo, domain);
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/* Kernel allocation are uninterruptible */
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vm_node = kzalloc(sizeof(*vm_node),0);
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vm_node->size = 0xC00000 >> 12;
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vm_node->start = 0;
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vm_node->mm = NULL;
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bo->tbo.vm_node = vm_node;
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bo->tbo.offset = bo->tbo.vm_node->start << PAGE_SHIFT;
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bo->tbo.offset += (u64)bo->rdev->mc.vram_start;
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bo->kptr = (void*)0xFE000000;
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bo->pin_count = 1;
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*bo_ptr = bo;
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return 0;
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}
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