99 lines
2.3 KiB
C++
99 lines
2.3 KiB
C++
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u32_t pciGetBaseSize(int bus, int devfn, int index,
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Bool destructive, Bool *min)
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{
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int offset;
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u32_t addr1;
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u32_t addr2;
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u32_t mask1;
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u32_t mask2;
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int bits = 0;
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/*
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* silently ignore bogus index values. Valid values are 0-6. 0-5 are
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* the 6 base address registers, and 6 is the ROM base address register.
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*/
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if (index < 0 || index > 6)
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return 0;
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if (min)
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*min = destructive;
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/* Get the PCI offset */
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if (index == 6)
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offset = PCI_MAP_ROM_REG;
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else
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offset = PCI_MAP_REG_START + (index << 2);
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addr1 = PciRead32(bus, devfn, offset);
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/*
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* Check if this is the second part of a 64 bit address.
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* XXX need to check how endianness affects 64 bit addresses.
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*/
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if (index > 0 && index < 6) {
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addr2 = PciRead32(bus, devfn, offset - 4);
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if (PCI_MAP_IS_MEM(addr2) && PCI_MAP_IS64BITMEM(addr2))
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return 0;
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}
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if (destructive) {
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PciWrite32(bus, devfn, offset, 0xffffffff);
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mask1 = PciRead32(bus, devfn, offset);
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PciWrite32(bus, devfn, offset, addr1);
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} else {
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mask1 = addr1;
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}
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/* Check if this is the first part of a 64 bit address. */
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if (index < 5 && PCI_MAP_IS_MEM(mask1) && PCI_MAP_IS64BITMEM(mask1))
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{
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if (PCIGETMEMORY(mask1) == 0)
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{
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addr2 = PciRead32(bus, devfn, offset + 4);
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if (destructive)
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{
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PciWrite32(bus, devfn, offset + 4, 0xffffffff);
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mask2 = PciRead32(bus, devfn, offset + 4);
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PciWrite32(bus, devfn, offset + 4, addr2);
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}
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else
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{
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mask2 = addr2;
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}
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if (mask2 == 0)
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return 0;
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bits = 32;
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while ((mask2 & 1) == 0)
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{
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bits++;
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mask2 >>= 1;
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}
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if (bits > 32)
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return bits;
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}
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}
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if (index < 6)
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if (PCI_MAP_IS_MEM(mask1))
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mask1 = PCIGETMEMORY(mask1);
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else
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mask1 = PCIGETIO(mask1);
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else
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mask1 = PCIGETROM(mask1);
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if (mask1 == 0)
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return 0;
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bits = 0;
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while ((mask1 & 1) == 0) {
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bits++;
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mask1 >>= 1;
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}
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/* I/O maps can be no larger than 8 bits */
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if ((index < 6) && PCI_MAP_IS_IO(addr1) && bits > 8)
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bits = 8;
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/* ROM maps can be no larger than 24 bits */
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if (index == 6 && bits > 24)
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bits = 24;
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return bits;
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}
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