1068 lines
32 KiB
C
1068 lines
32 KiB
C
/*
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* Copyright 2007-8 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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*/
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#include "drmP.h"
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#include "radeon_drm.h"
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#include "radeon.h"
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#include "atom.h"
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//#include <asm/div64.h>
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#include "drm_crtc_helper.h"
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#include "drm_edid.h"
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static int radeon_ddc_dump(struct drm_connector *connector);
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static void avivo_crtc_load_lut(struct drm_crtc *crtc)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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struct drm_device *dev = crtc->dev;
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struct radeon_device *rdev = dev->dev_private;
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int i;
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DRM_DEBUG("%d\n", radeon_crtc->crtc_id);
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WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
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WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
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WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
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WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
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WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
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WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
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WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
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WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
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WREG32(AVIVO_DC_LUT_RW_MODE, 0);
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WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
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WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
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for (i = 0; i < 256; i++) {
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WREG32(AVIVO_DC_LUT_30_COLOR,
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(radeon_crtc->lut_r[i] << 20) |
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(radeon_crtc->lut_g[i] << 10) |
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(radeon_crtc->lut_b[i] << 0));
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}
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WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
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}
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static void evergreen_crtc_load_lut(struct drm_crtc *crtc)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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struct drm_device *dev = crtc->dev;
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struct radeon_device *rdev = dev->dev_private;
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int i;
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DRM_DEBUG("%d\n", radeon_crtc->crtc_id);
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WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
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WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
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WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
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WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
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WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
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WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
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WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
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WREG32(EVERGREEN_DC_LUT_RW_MODE, radeon_crtc->crtc_id);
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WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK, 0x00000007);
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WREG32(EVERGREEN_DC_LUT_RW_INDEX, 0);
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for (i = 0; i < 256; i++) {
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WREG32(EVERGREEN_DC_LUT_30_COLOR,
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(radeon_crtc->lut_r[i] << 20) |
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(radeon_crtc->lut_g[i] << 10) |
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(radeon_crtc->lut_b[i] << 0));
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}
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}
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static void legacy_crtc_load_lut(struct drm_crtc *crtc)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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struct drm_device *dev = crtc->dev;
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struct radeon_device *rdev = dev->dev_private;
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int i;
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uint32_t dac2_cntl;
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dac2_cntl = RREG32(RADEON_DAC_CNTL2);
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if (radeon_crtc->crtc_id == 0)
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dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
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else
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dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
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WREG32(RADEON_DAC_CNTL2, dac2_cntl);
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WREG8(RADEON_PALETTE_INDEX, 0);
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for (i = 0; i < 256; i++) {
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WREG32(RADEON_PALETTE_30_DATA,
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(radeon_crtc->lut_r[i] << 20) |
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(radeon_crtc->lut_g[i] << 10) |
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(radeon_crtc->lut_b[i] << 0));
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}
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}
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void radeon_crtc_load_lut(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct radeon_device *rdev = dev->dev_private;
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if (!crtc->enabled)
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return;
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if (ASIC_IS_DCE4(rdev))
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evergreen_crtc_load_lut(crtc);
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else if (ASIC_IS_AVIVO(rdev))
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avivo_crtc_load_lut(crtc);
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else
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legacy_crtc_load_lut(crtc);
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}
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/** Sets the color ramps on behalf of fbcon */
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void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
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u16 blue, int regno)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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radeon_crtc->lut_r[regno] = red >> 6;
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radeon_crtc->lut_g[regno] = green >> 6;
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radeon_crtc->lut_b[regno] = blue >> 6;
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}
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/** Gets the color ramps on behalf of fbcon */
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void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
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u16 *blue, int regno)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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*red = radeon_crtc->lut_r[regno] << 6;
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*green = radeon_crtc->lut_g[regno] << 6;
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*blue = radeon_crtc->lut_b[regno] << 6;
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}
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static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
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u16 *blue, uint32_t size)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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int i;
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if (size != 256) {
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return;
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}
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/* userspace palettes are always correct as is */
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for (i = 0; i < 256; i++) {
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radeon_crtc->lut_r[i] = red[i] >> 6;
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radeon_crtc->lut_g[i] = green[i] >> 6;
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radeon_crtc->lut_b[i] = blue[i] >> 6;
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}
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radeon_crtc_load_lut(crtc);
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}
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static void radeon_crtc_destroy(struct drm_crtc *crtc)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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drm_crtc_cleanup(crtc);
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kfree(radeon_crtc);
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}
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static const struct drm_crtc_funcs radeon_crtc_funcs = {
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.cursor_set = NULL,
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.cursor_move = NULL,
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.gamma_set = radeon_crtc_gamma_set,
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.set_config = drm_crtc_helper_set_config,
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.destroy = radeon_crtc_destroy,
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};
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static void radeon_crtc_init(struct drm_device *dev, int index)
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{
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struct radeon_device *rdev = dev->dev_private;
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struct radeon_crtc *radeon_crtc;
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int i;
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radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
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if (radeon_crtc == NULL)
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return;
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drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
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drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
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radeon_crtc->crtc_id = index;
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rdev->mode_info.crtcs[index] = radeon_crtc;
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#if 0
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radeon_crtc->mode_set.crtc = &radeon_crtc->base;
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radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
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radeon_crtc->mode_set.num_connectors = 0;
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#endif
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for (i = 0; i < 256; i++) {
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radeon_crtc->lut_r[i] = i << 2;
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radeon_crtc->lut_g[i] = i << 2;
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radeon_crtc->lut_b[i] = i << 2;
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}
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if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
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radeon_atombios_init_crtc(dev, radeon_crtc);
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else
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radeon_legacy_init_crtc(dev, radeon_crtc);
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}
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static const char *encoder_names[34] = {
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"NONE",
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"INTERNAL_LVDS",
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"INTERNAL_TMDS1",
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"INTERNAL_TMDS2",
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"INTERNAL_DAC1",
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"INTERNAL_DAC2",
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"INTERNAL_SDVOA",
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"INTERNAL_SDVOB",
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"SI170B",
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"CH7303",
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"CH7301",
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"INTERNAL_DVO1",
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"EXTERNAL_SDVOA",
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"EXTERNAL_SDVOB",
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"TITFP513",
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"INTERNAL_LVTM1",
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"VT1623",
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"HDMI_SI1930",
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"HDMI_INTERNAL",
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"INTERNAL_KLDSCP_TMDS1",
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"INTERNAL_KLDSCP_DVO1",
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"INTERNAL_KLDSCP_DAC1",
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"INTERNAL_KLDSCP_DAC2",
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"SI178",
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"MVPU_FPGA",
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"INTERNAL_DDI",
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"VT1625",
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"HDMI_SI1932",
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"DP_AN9801",
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"DP_DP501",
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"INTERNAL_UNIPHY",
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"INTERNAL_KLDSCP_LVTMA",
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"INTERNAL_UNIPHY1",
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"INTERNAL_UNIPHY2",
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};
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static const char *connector_names[15] = {
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"Unknown",
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"VGA",
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"DVI-I",
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"DVI-D",
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"DVI-A",
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"Composite",
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"S-video",
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"LVDS",
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"Component",
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"DIN",
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"DisplayPort",
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"HDMI-A",
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"HDMI-B",
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"TV",
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"eDP",
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};
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static const char *hpd_names[7] = {
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"NONE",
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"HPD1",
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"HPD2",
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"HPD3",
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"HPD4",
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"HPD5",
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"HPD6",
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};
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static void radeon_print_display_setup(struct drm_device *dev)
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{
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struct drm_connector *connector;
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struct radeon_connector *radeon_connector;
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struct drm_encoder *encoder;
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struct radeon_encoder *radeon_encoder;
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uint32_t devices;
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int i = 0;
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DRM_INFO("Radeon Display Connectors\n");
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list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
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radeon_connector = to_radeon_connector(connector);
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DRM_INFO("Connector %d:\n", i);
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DRM_INFO(" %s\n", connector_names[connector->connector_type]);
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if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
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DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
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if (radeon_connector->ddc_bus) {
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DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
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radeon_connector->ddc_bus->rec.mask_clk_reg,
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radeon_connector->ddc_bus->rec.mask_data_reg,
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radeon_connector->ddc_bus->rec.a_clk_reg,
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radeon_connector->ddc_bus->rec.a_data_reg,
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radeon_connector->ddc_bus->rec.en_clk_reg,
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radeon_connector->ddc_bus->rec.en_data_reg,
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radeon_connector->ddc_bus->rec.y_clk_reg,
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radeon_connector->ddc_bus->rec.y_data_reg);
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} else {
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if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
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connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
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connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
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connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
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connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
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connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
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DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
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}
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DRM_INFO(" Encoders:\n");
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list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
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radeon_encoder = to_radeon_encoder(encoder);
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devices = radeon_encoder->devices & radeon_connector->devices;
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if (devices) {
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if (devices & ATOM_DEVICE_CRT1_SUPPORT)
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DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
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if (devices & ATOM_DEVICE_CRT2_SUPPORT)
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DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
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if (devices & ATOM_DEVICE_LCD1_SUPPORT)
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DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
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if (devices & ATOM_DEVICE_DFP1_SUPPORT)
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DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
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if (devices & ATOM_DEVICE_DFP2_SUPPORT)
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DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
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if (devices & ATOM_DEVICE_DFP3_SUPPORT)
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DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
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if (devices & ATOM_DEVICE_DFP4_SUPPORT)
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DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
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if (devices & ATOM_DEVICE_DFP5_SUPPORT)
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DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
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if (devices & ATOM_DEVICE_TV1_SUPPORT)
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DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
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if (devices & ATOM_DEVICE_CV_SUPPORT)
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DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
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}
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}
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i++;
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}
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}
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static bool radeon_setup_enc_conn(struct drm_device *dev)
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{
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struct radeon_device *rdev = dev->dev_private;
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struct drm_connector *drm_connector;
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bool ret = false;
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if (rdev->bios) {
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if (rdev->is_atom_bios) {
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if (rdev->family >= CHIP_R600)
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ret = radeon_get_atom_connector_info_from_object_table(dev);
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else
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ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
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} else {
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ret = radeon_get_legacy_connector_info_from_bios(dev);
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if (ret == false)
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ret = radeon_get_legacy_connector_info_from_table(dev);
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}
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} else {
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if (!ASIC_IS_AVIVO(rdev))
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ret = radeon_get_legacy_connector_info_from_table(dev);
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}
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if (ret) {
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radeon_setup_encoder_clones(dev);
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radeon_print_display_setup(dev);
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list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head)
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radeon_ddc_dump(drm_connector);
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}
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return ret;
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}
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int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
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{
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struct drm_device *dev = radeon_connector->base.dev;
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struct radeon_device *rdev = dev->dev_private;
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int ret = 0;
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if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
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(radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
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struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
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if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
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dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
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radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter);
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}
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if (!radeon_connector->ddc_bus)
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return -1;
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if (!radeon_connector->edid) {
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radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter);
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}
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/* some servers provide a hardcoded edid in rom for KVMs */
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if (!radeon_connector->edid)
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radeon_connector->edid = radeon_combios_get_hardcoded_edid(rdev);
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if (radeon_connector->edid) {
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drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
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ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
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return ret;
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}
|
|
drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
|
|
return 0;
|
|
}
|
|
|
|
static int radeon_ddc_dump(struct drm_connector *connector)
|
|
{
|
|
struct edid *edid;
|
|
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
|
|
int ret = 0;
|
|
|
|
if (!radeon_connector->ddc_bus)
|
|
return -1;
|
|
edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter);
|
|
if (edid) {
|
|
kfree(edid);
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static inline uint32_t radeon_div(uint64_t n, uint32_t d)
|
|
{
|
|
uint64_t mod;
|
|
|
|
n += d / 2;
|
|
|
|
mod = do_div(n, d);
|
|
return n;
|
|
}
|
|
|
|
static void radeon_compute_pll_legacy(struct radeon_pll *pll,
|
|
uint64_t freq,
|
|
uint32_t *dot_clock_p,
|
|
uint32_t *fb_div_p,
|
|
uint32_t *frac_fb_div_p,
|
|
uint32_t *ref_div_p,
|
|
uint32_t *post_div_p)
|
|
{
|
|
uint32_t min_ref_div = pll->min_ref_div;
|
|
uint32_t max_ref_div = pll->max_ref_div;
|
|
uint32_t min_post_div = pll->min_post_div;
|
|
uint32_t max_post_div = pll->max_post_div;
|
|
uint32_t min_fractional_feed_div = 0;
|
|
uint32_t max_fractional_feed_div = 0;
|
|
uint32_t best_vco = pll->best_vco;
|
|
uint32_t best_post_div = 1;
|
|
uint32_t best_ref_div = 1;
|
|
uint32_t best_feedback_div = 1;
|
|
uint32_t best_frac_feedback_div = 0;
|
|
uint32_t best_freq = -1;
|
|
uint32_t best_error = 0xffffffff;
|
|
uint32_t best_vco_diff = 1;
|
|
uint32_t post_div;
|
|
|
|
DRM_DEBUG("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
|
|
freq = freq * 1000;
|
|
|
|
if (pll->flags & RADEON_PLL_USE_REF_DIV)
|
|
min_ref_div = max_ref_div = pll->reference_div;
|
|
else {
|
|
while (min_ref_div < max_ref_div-1) {
|
|
uint32_t mid = (min_ref_div + max_ref_div) / 2;
|
|
uint32_t pll_in = pll->reference_freq / mid;
|
|
if (pll_in < pll->pll_in_min)
|
|
max_ref_div = mid;
|
|
else if (pll_in > pll->pll_in_max)
|
|
min_ref_div = mid;
|
|
else
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (pll->flags & RADEON_PLL_USE_POST_DIV)
|
|
min_post_div = max_post_div = pll->post_div;
|
|
|
|
if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
|
|
min_fractional_feed_div = pll->min_frac_feedback_div;
|
|
max_fractional_feed_div = pll->max_frac_feedback_div;
|
|
}
|
|
|
|
for (post_div = min_post_div; post_div <= max_post_div; ++post_div) {
|
|
uint32_t ref_div;
|
|
|
|
if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
|
|
continue;
|
|
|
|
/* legacy radeons only have a few post_divs */
|
|
if (pll->flags & RADEON_PLL_LEGACY) {
|
|
if ((post_div == 5) ||
|
|
(post_div == 7) ||
|
|
(post_div == 9) ||
|
|
(post_div == 10) ||
|
|
(post_div == 11) ||
|
|
(post_div == 13) ||
|
|
(post_div == 14) ||
|
|
(post_div == 15))
|
|
continue;
|
|
}
|
|
|
|
for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
|
|
uint32_t feedback_div, current_freq = 0, error, vco_diff;
|
|
uint32_t pll_in = pll->reference_freq / ref_div;
|
|
uint32_t min_feed_div = pll->min_feedback_div;
|
|
uint32_t max_feed_div = pll->max_feedback_div + 1;
|
|
|
|
if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
|
|
continue;
|
|
|
|
while (min_feed_div < max_feed_div) {
|
|
uint32_t vco;
|
|
uint32_t min_frac_feed_div = min_fractional_feed_div;
|
|
uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
|
|
uint32_t frac_feedback_div;
|
|
uint64_t tmp;
|
|
|
|
feedback_div = (min_feed_div + max_feed_div) / 2;
|
|
|
|
tmp = (uint64_t)pll->reference_freq * feedback_div;
|
|
vco = radeon_div(tmp, ref_div);
|
|
|
|
if (vco < pll->pll_out_min) {
|
|
min_feed_div = feedback_div + 1;
|
|
continue;
|
|
} else if (vco > pll->pll_out_max) {
|
|
max_feed_div = feedback_div;
|
|
continue;
|
|
}
|
|
|
|
while (min_frac_feed_div < max_frac_feed_div) {
|
|
frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
|
|
tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
|
|
tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
|
|
current_freq = radeon_div(tmp, ref_div * post_div);
|
|
|
|
if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
|
|
error = freq - current_freq;
|
|
error = error < 0 ? 0xffffffff : error;
|
|
} else
|
|
error = abs(current_freq - freq);
|
|
vco_diff = abs(vco - best_vco);
|
|
|
|
if ((best_vco == 0 && error < best_error) ||
|
|
(best_vco != 0 &&
|
|
(error < best_error - 100 ||
|
|
(abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
|
|
best_post_div = post_div;
|
|
best_ref_div = ref_div;
|
|
best_feedback_div = feedback_div;
|
|
best_frac_feedback_div = frac_feedback_div;
|
|
best_freq = current_freq;
|
|
best_error = error;
|
|
best_vco_diff = vco_diff;
|
|
} else if (current_freq == freq) {
|
|
if (best_freq == -1) {
|
|
best_post_div = post_div;
|
|
best_ref_div = ref_div;
|
|
best_feedback_div = feedback_div;
|
|
best_frac_feedback_div = frac_feedback_div;
|
|
best_freq = current_freq;
|
|
best_error = error;
|
|
best_vco_diff = vco_diff;
|
|
} else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
|
|
((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
|
|
((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
|
|
((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
|
|
((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
|
|
((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
|
|
best_post_div = post_div;
|
|
best_ref_div = ref_div;
|
|
best_feedback_div = feedback_div;
|
|
best_frac_feedback_div = frac_feedback_div;
|
|
best_freq = current_freq;
|
|
best_error = error;
|
|
best_vco_diff = vco_diff;
|
|
}
|
|
}
|
|
if (current_freq < freq)
|
|
min_frac_feed_div = frac_feedback_div + 1;
|
|
else
|
|
max_frac_feed_div = frac_feedback_div;
|
|
}
|
|
if (current_freq < freq)
|
|
min_feed_div = feedback_div + 1;
|
|
else
|
|
max_feed_div = feedback_div;
|
|
}
|
|
}
|
|
}
|
|
|
|
*dot_clock_p = best_freq / 10000;
|
|
*fb_div_p = best_feedback_div;
|
|
*frac_fb_div_p = best_frac_feedback_div;
|
|
*ref_div_p = best_ref_div;
|
|
*post_div_p = best_post_div;
|
|
}
|
|
|
|
static bool
|
|
calc_fb_div(struct radeon_pll *pll,
|
|
uint32_t freq,
|
|
uint32_t post_div,
|
|
uint32_t ref_div,
|
|
uint32_t *fb_div,
|
|
uint32_t *fb_div_frac)
|
|
{
|
|
fixed20_12 feedback_divider, a, b;
|
|
u32 vco_freq;
|
|
|
|
vco_freq = freq * post_div;
|
|
/* feedback_divider = vco_freq * ref_div / pll->reference_freq; */
|
|
a.full = rfixed_const(pll->reference_freq);
|
|
feedback_divider.full = rfixed_const(vco_freq);
|
|
feedback_divider.full = rfixed_div(feedback_divider, a);
|
|
a.full = rfixed_const(ref_div);
|
|
feedback_divider.full = rfixed_mul(feedback_divider, a);
|
|
|
|
if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
|
|
/* feedback_divider = floor((feedback_divider * 10.0) + 0.5) * 0.1; */
|
|
a.full = rfixed_const(10);
|
|
feedback_divider.full = rfixed_mul(feedback_divider, a);
|
|
feedback_divider.full += rfixed_const_half(0);
|
|
feedback_divider.full = rfixed_floor(feedback_divider);
|
|
feedback_divider.full = rfixed_div(feedback_divider, a);
|
|
|
|
/* *fb_div = floor(feedback_divider); */
|
|
a.full = rfixed_floor(feedback_divider);
|
|
*fb_div = rfixed_trunc(a);
|
|
/* *fb_div_frac = fmod(feedback_divider, 1.0) * 10.0; */
|
|
a.full = rfixed_const(10);
|
|
b.full = rfixed_mul(feedback_divider, a);
|
|
|
|
feedback_divider.full = rfixed_floor(feedback_divider);
|
|
feedback_divider.full = rfixed_mul(feedback_divider, a);
|
|
feedback_divider.full = b.full - feedback_divider.full;
|
|
*fb_div_frac = rfixed_trunc(feedback_divider);
|
|
} else {
|
|
/* *fb_div = floor(feedback_divider + 0.5); */
|
|
feedback_divider.full += rfixed_const_half(0);
|
|
feedback_divider.full = rfixed_floor(feedback_divider);
|
|
|
|
*fb_div = rfixed_trunc(feedback_divider);
|
|
*fb_div_frac = 0;
|
|
}
|
|
|
|
if (((*fb_div) < pll->min_feedback_div) || ((*fb_div) > pll->max_feedback_div))
|
|
return false;
|
|
else
|
|
return true;
|
|
}
|
|
|
|
static bool
|
|
calc_fb_ref_div(struct radeon_pll *pll,
|
|
uint32_t freq,
|
|
uint32_t post_div,
|
|
uint32_t *fb_div,
|
|
uint32_t *fb_div_frac,
|
|
uint32_t *ref_div)
|
|
{
|
|
fixed20_12 ffreq, max_error, error, pll_out, a;
|
|
u32 vco;
|
|
|
|
ffreq.full = rfixed_const(freq);
|
|
/* max_error = ffreq * 0.0025; */
|
|
a.full = rfixed_const(400);
|
|
max_error.full = rfixed_div(ffreq, a);
|
|
|
|
for ((*ref_div) = pll->min_ref_div; (*ref_div) < pll->max_ref_div; ++(*ref_div)) {
|
|
if (calc_fb_div(pll, freq, post_div, (*ref_div), fb_div, fb_div_frac)) {
|
|
vco = pll->reference_freq * (((*fb_div) * 10) + (*fb_div_frac));
|
|
vco = vco / ((*ref_div) * 10);
|
|
|
|
if ((vco < pll->pll_out_min) || (vco > pll->pll_out_max))
|
|
continue;
|
|
|
|
/* pll_out = vco / post_div; */
|
|
a.full = rfixed_const(post_div);
|
|
pll_out.full = rfixed_const(vco);
|
|
pll_out.full = rfixed_div(pll_out, a);
|
|
|
|
if (pll_out.full >= ffreq.full) {
|
|
error.full = pll_out.full - ffreq.full;
|
|
if (error.full <= max_error.full)
|
|
return true;
|
|
}
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
static void radeon_compute_pll_new(struct radeon_pll *pll,
|
|
uint64_t freq,
|
|
uint32_t *dot_clock_p,
|
|
uint32_t *fb_div_p,
|
|
uint32_t *frac_fb_div_p,
|
|
uint32_t *ref_div_p,
|
|
uint32_t *post_div_p)
|
|
{
|
|
u32 fb_div = 0, fb_div_frac = 0, post_div = 0, ref_div = 0;
|
|
u32 best_freq = 0, vco_frequency;
|
|
|
|
/* freq = freq / 10; */
|
|
do_div(freq, 10);
|
|
|
|
if (pll->flags & RADEON_PLL_USE_POST_DIV) {
|
|
post_div = pll->post_div;
|
|
if ((post_div < pll->min_post_div) || (post_div > pll->max_post_div))
|
|
goto done;
|
|
|
|
vco_frequency = freq * post_div;
|
|
if ((vco_frequency < pll->pll_out_min) || (vco_frequency > pll->pll_out_max))
|
|
goto done;
|
|
|
|
if (pll->flags & RADEON_PLL_USE_REF_DIV) {
|
|
ref_div = pll->reference_div;
|
|
if ((ref_div < pll->min_ref_div) || (ref_div > pll->max_ref_div))
|
|
goto done;
|
|
if (!calc_fb_div(pll, freq, post_div, ref_div, &fb_div, &fb_div_frac))
|
|
goto done;
|
|
}
|
|
} else {
|
|
for (post_div = pll->max_post_div; post_div >= pll->min_post_div; --post_div) {
|
|
if (pll->flags & RADEON_PLL_LEGACY) {
|
|
if ((post_div == 5) ||
|
|
(post_div == 7) ||
|
|
(post_div == 9) ||
|
|
(post_div == 10) ||
|
|
(post_div == 11))
|
|
continue;
|
|
}
|
|
|
|
if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
|
|
continue;
|
|
|
|
vco_frequency = freq * post_div;
|
|
if ((vco_frequency < pll->pll_out_min) || (vco_frequency > pll->pll_out_max))
|
|
continue;
|
|
if (pll->flags & RADEON_PLL_USE_REF_DIV) {
|
|
ref_div = pll->reference_div;
|
|
if ((ref_div < pll->min_ref_div) || (ref_div > pll->max_ref_div))
|
|
goto done;
|
|
if (calc_fb_div(pll, freq, post_div, ref_div, &fb_div, &fb_div_frac))
|
|
break;
|
|
} else {
|
|
if (calc_fb_ref_div(pll, freq, post_div, &fb_div, &fb_div_frac, &ref_div))
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
best_freq = pll->reference_freq * 10 * fb_div;
|
|
best_freq += pll->reference_freq * fb_div_frac;
|
|
best_freq = best_freq / (ref_div * post_div);
|
|
|
|
done:
|
|
if (best_freq == 0)
|
|
DRM_ERROR("Couldn't find valid PLL dividers\n");
|
|
|
|
*dot_clock_p = best_freq / 10;
|
|
*fb_div_p = fb_div;
|
|
*frac_fb_div_p = fb_div_frac;
|
|
*ref_div_p = ref_div;
|
|
*post_div_p = post_div;
|
|
|
|
DRM_DEBUG("%u %d.%d, %d, %d\n", *dot_clock_p, *fb_div_p, *frac_fb_div_p, *ref_div_p, *post_div_p);
|
|
}
|
|
|
|
void radeon_compute_pll(struct radeon_pll *pll,
|
|
uint64_t freq,
|
|
uint32_t *dot_clock_p,
|
|
uint32_t *fb_div_p,
|
|
uint32_t *frac_fb_div_p,
|
|
uint32_t *ref_div_p,
|
|
uint32_t *post_div_p)
|
|
{
|
|
switch (pll->algo) {
|
|
case PLL_ALGO_NEW:
|
|
radeon_compute_pll_new(pll, freq, dot_clock_p, fb_div_p,
|
|
frac_fb_div_p, ref_div_p, post_div_p);
|
|
break;
|
|
case PLL_ALGO_LEGACY:
|
|
default:
|
|
radeon_compute_pll_legacy(pll, freq, dot_clock_p, fb_div_p,
|
|
frac_fb_div_p, ref_div_p, post_div_p);
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
|
|
{
|
|
struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
|
|
struct drm_device *dev = fb->dev;
|
|
|
|
if (fb->fbdev)
|
|
radeonfb_remove(dev, fb);
|
|
|
|
|
|
drm_framebuffer_cleanup(fb);
|
|
kfree(radeon_fb);
|
|
}
|
|
|
|
static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
|
|
struct drm_file *file_priv,
|
|
unsigned int *handle)
|
|
{
|
|
struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
|
|
|
|
return NULL;
|
|
// return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
|
|
}
|
|
|
|
static const struct drm_framebuffer_funcs radeon_fb_funcs = {
|
|
.destroy = radeon_user_framebuffer_destroy,
|
|
.create_handle = radeon_user_framebuffer_create_handle,
|
|
};
|
|
|
|
struct drm_framebuffer *
|
|
radeon_framebuffer_create(struct drm_device *dev,
|
|
struct drm_mode_fb_cmd *mode_cmd,
|
|
struct drm_gem_object *obj)
|
|
{
|
|
struct radeon_framebuffer *radeon_fb;
|
|
|
|
radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
|
|
if (radeon_fb == NULL) {
|
|
return NULL;
|
|
}
|
|
drm_framebuffer_init(dev, &radeon_fb->base, &radeon_fb_funcs);
|
|
drm_helper_mode_fill_fb_struct(&radeon_fb->base, mode_cmd);
|
|
radeon_fb->obj = obj;
|
|
return &radeon_fb->base;
|
|
}
|
|
|
|
static struct drm_framebuffer *
|
|
radeon_user_framebuffer_create(struct drm_device *dev,
|
|
struct drm_file *file_priv,
|
|
struct drm_mode_fb_cmd *mode_cmd)
|
|
{
|
|
struct drm_gem_object *obj;
|
|
|
|
return NULL;
|
|
|
|
// obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle);
|
|
//
|
|
// return radeon_framebuffer_create(dev, mode_cmd, obj);
|
|
}
|
|
|
|
static const struct drm_mode_config_funcs radeon_mode_funcs = {
|
|
// .fb_create = radeon_user_framebuffer_create,
|
|
.fb_changed = radeonfb_probe,
|
|
};
|
|
|
|
struct drm_prop_enum_list {
|
|
int type;
|
|
char *name;
|
|
};
|
|
|
|
static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
|
|
{ { 0, "driver" },
|
|
{ 1, "bios" },
|
|
};
|
|
|
|
static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
|
|
{ { TV_STD_NTSC, "ntsc" },
|
|
{ TV_STD_PAL, "pal" },
|
|
{ TV_STD_PAL_M, "pal-m" },
|
|
{ TV_STD_PAL_60, "pal-60" },
|
|
{ TV_STD_NTSC_J, "ntsc-j" },
|
|
{ TV_STD_SCART_PAL, "scart-pal" },
|
|
{ TV_STD_PAL_CN, "pal-cn" },
|
|
{ TV_STD_SECAM, "secam" },
|
|
};
|
|
|
|
static int radeon_modeset_create_props(struct radeon_device *rdev)
|
|
{
|
|
int i, sz;
|
|
|
|
if (rdev->is_atom_bios) {
|
|
rdev->mode_info.coherent_mode_property =
|
|
drm_property_create(rdev->ddev,
|
|
DRM_MODE_PROP_RANGE,
|
|
"coherent", 2);
|
|
if (!rdev->mode_info.coherent_mode_property)
|
|
return -ENOMEM;
|
|
|
|
rdev->mode_info.coherent_mode_property->values[0] = 0;
|
|
rdev->mode_info.coherent_mode_property->values[1] = 1;
|
|
}
|
|
|
|
if (!ASIC_IS_AVIVO(rdev)) {
|
|
sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
|
|
rdev->mode_info.tmds_pll_property =
|
|
drm_property_create(rdev->ddev,
|
|
DRM_MODE_PROP_ENUM,
|
|
"tmds_pll", sz);
|
|
for (i = 0; i < sz; i++) {
|
|
drm_property_add_enum(rdev->mode_info.tmds_pll_property,
|
|
i,
|
|
radeon_tmds_pll_enum_list[i].type,
|
|
radeon_tmds_pll_enum_list[i].name);
|
|
}
|
|
}
|
|
|
|
rdev->mode_info.load_detect_property =
|
|
drm_property_create(rdev->ddev,
|
|
DRM_MODE_PROP_RANGE,
|
|
"load detection", 2);
|
|
if (!rdev->mode_info.load_detect_property)
|
|
return -ENOMEM;
|
|
rdev->mode_info.load_detect_property->values[0] = 0;
|
|
rdev->mode_info.load_detect_property->values[1] = 1;
|
|
|
|
drm_mode_create_scaling_mode_property(rdev->ddev);
|
|
|
|
sz = ARRAY_SIZE(radeon_tv_std_enum_list);
|
|
rdev->mode_info.tv_std_property =
|
|
drm_property_create(rdev->ddev,
|
|
DRM_MODE_PROP_ENUM,
|
|
"tv standard", sz);
|
|
for (i = 0; i < sz; i++) {
|
|
drm_property_add_enum(rdev->mode_info.tv_std_property,
|
|
i,
|
|
radeon_tv_std_enum_list[i].type,
|
|
radeon_tv_std_enum_list[i].name);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int radeon_modeset_init(struct radeon_device *rdev)
|
|
{
|
|
int i;
|
|
int ret;
|
|
|
|
drm_mode_config_init(rdev->ddev);
|
|
rdev->mode_info.mode_config_initialized = true;
|
|
|
|
rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs;
|
|
|
|
if (ASIC_IS_AVIVO(rdev)) {
|
|
rdev->ddev->mode_config.max_width = 8192;
|
|
rdev->ddev->mode_config.max_height = 8192;
|
|
} else {
|
|
rdev->ddev->mode_config.max_width = 4096;
|
|
rdev->ddev->mode_config.max_height = 4096;
|
|
}
|
|
|
|
rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
|
|
|
|
ret = radeon_modeset_create_props(rdev);
|
|
if (ret) {
|
|
return ret;
|
|
}
|
|
|
|
/* check combios for a valid hardcoded EDID - Sun servers */
|
|
if (!rdev->is_atom_bios) {
|
|
/* check for hardcoded EDID in BIOS */
|
|
radeon_combios_check_hardcoded_edid(rdev);
|
|
}
|
|
|
|
if (rdev->flags & RADEON_SINGLE_CRTC)
|
|
rdev->num_crtc = 1;
|
|
else {
|
|
if (ASIC_IS_DCE4(rdev))
|
|
rdev->num_crtc = 6;
|
|
else
|
|
rdev->num_crtc = 2;
|
|
}
|
|
|
|
/* allocate crtcs */
|
|
for (i = 0; i < rdev->num_crtc; i++) {
|
|
radeon_crtc_init(rdev->ddev, i);
|
|
}
|
|
|
|
/* okay we should have all the bios connectors */
|
|
ret = radeon_setup_enc_conn(rdev->ddev);
|
|
if (!ret) {
|
|
return ret;
|
|
}
|
|
/* initialize hpd */
|
|
radeon_hpd_init(rdev);
|
|
drm_helper_initial_config(rdev->ddev);
|
|
return 0;
|
|
}
|
|
|
|
void radeon_modeset_fini(struct radeon_device *rdev)
|
|
{
|
|
kfree(rdev->mode_info.bios_hardcoded_edid);
|
|
|
|
if (rdev->mode_info.mode_config_initialized) {
|
|
radeon_hpd_fini(rdev);
|
|
drm_mode_config_cleanup(rdev->ddev);
|
|
rdev->mode_info.mode_config_initialized = false;
|
|
}
|
|
}
|
|
|
|
bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
|
|
struct drm_display_mode *mode,
|
|
struct drm_display_mode *adjusted_mode)
|
|
{
|
|
struct drm_device *dev = crtc->dev;
|
|
struct drm_encoder *encoder;
|
|
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
|
|
struct radeon_encoder *radeon_encoder;
|
|
bool first = true;
|
|
|
|
list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
|
|
radeon_encoder = to_radeon_encoder(encoder);
|
|
if (encoder->crtc != crtc)
|
|
continue;
|
|
if (first) {
|
|
/* set scaling */
|
|
if (radeon_encoder->rmx_type == RMX_OFF)
|
|
radeon_crtc->rmx_type = RMX_OFF;
|
|
else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
|
|
mode->vdisplay < radeon_encoder->native_mode.vdisplay)
|
|
radeon_crtc->rmx_type = radeon_encoder->rmx_type;
|
|
else
|
|
radeon_crtc->rmx_type = RMX_OFF;
|
|
/* copy native mode */
|
|
memcpy(&radeon_crtc->native_mode,
|
|
&radeon_encoder->native_mode,
|
|
sizeof(struct drm_display_mode));
|
|
first = false;
|
|
} else {
|
|
if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
|
|
/* WARNING: Right now this can't happen but
|
|
* in the future we need to check that scaling
|
|
* are consistent accross different encoder
|
|
* (ie all encoder can work with the same
|
|
* scaling).
|
|
*/
|
|
DRM_ERROR("Scaling not consistent accross encoder.\n");
|
|
return false;
|
|
}
|
|
}
|
|
}
|
|
if (radeon_crtc->rmx_type != RMX_OFF) {
|
|
fixed20_12 a, b;
|
|
a.full = rfixed_const(crtc->mode.vdisplay);
|
|
b.full = rfixed_const(radeon_crtc->native_mode.hdisplay);
|
|
radeon_crtc->vsc.full = rfixed_div(a, b);
|
|
a.full = rfixed_const(crtc->mode.hdisplay);
|
|
b.full = rfixed_const(radeon_crtc->native_mode.vdisplay);
|
|
radeon_crtc->hsc.full = rfixed_div(a, b);
|
|
} else {
|
|
radeon_crtc->vsc.full = rfixed_const(1);
|
|
radeon_crtc->hsc.full = rfixed_const(1);
|
|
}
|
|
return true;
|
|
}
|