132 lines
3.2 KiB
C
132 lines
3.2 KiB
C
/*
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* Copyright (c) 2006 Jakub Jermar
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* - Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* - Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* - The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef KERN_ATOMIC_H_
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#define KERN_ATOMIC_H_
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typedef struct atomic {
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volatile long count;
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} atomic_t;
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static inline void atomic_inc(atomic_t *val) {
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#ifdef USE_SMP
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asm volatile ("lock inc %0\n" : "+m" (val->count));
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#else
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asm volatile ("inc %0\n" : "+m" (val->count));
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#endif /* USE_SMP */
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}
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static inline void atomic_dec(atomic_t *val) {
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#ifdef USE_SMP
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asm volatile ("lock dec %0\n" : "+m" (val->count));
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#else
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asm volatile ("dec %0\n" : "+m" (val->count));
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#endif /* USE_SMP */
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}
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/*
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static inline long atomic_postinc(atomic_t *val)
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{
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long r = 1;
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asm volatile (
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"lock xadd %1, %0\n"
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: "+m" (val->count), "+r" (r)
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);
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return r;
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}
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static inline long atomic_postdec(atomic_t *val)
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{
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long r = -1;
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asm volatile (
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"lock xadd %1, %0\n"
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: "+m" (val->count), "+r"(r)
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);
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return r;
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}
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#define atomic_preinc(val) (atomic_postinc(val) + 1)
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#define atomic_predec(val) (atomic_postdec(val) - 1)
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static inline u32_t test_and_set(atomic_t *val) {
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uint32_t v;
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asm volatile (
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"movl $1, %0\n"
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"xchgl %0, %1\n"
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: "=r" (v),"+m" (val->count)
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);
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return v;
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}
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*/
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/* ia32 specific fast spinlock */
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static inline void atomic_lock_arch(atomic_t *val)
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{
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u32_t tmp;
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// preemption_disable();
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asm volatile (
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"0:\n"
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"pause\n\t" /* Pentium 4's HT love this instruction */
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"mov %1, [%0]\n\t"
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"test %1, %1\n\t"
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"jnz 0b\n\t" /* lightweight looping on locked spinlock */
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"inc %1\n\t" /* now use the atomic operation */
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"xchg [%0], %1\n\t"
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"test %1, %1\n\t"
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"jnz 0b\n\t"
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: "+m" (val->count), "=r"(tmp)
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);
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/*
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* Prevent critical section code from bleeding out this way up.
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*/
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// CS_ENTER_BARRIER();
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}
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static inline void atomic_set(atomic_t *val, long i)
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{
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val->count = i;
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}
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static inline long atomic_get(atomic_t *val)
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{
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return val->count;
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}
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#endif /* KERN_ATOMIC_H_ */
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