448 lines
17 KiB
C
448 lines
17 KiB
C
/*=====================================================================
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Macros.c -> Macros used on the opcode execution.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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Copyright (c) 2000 Santiago Romero Iglesias.
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Email: sromero@escomposlinux.org
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======================================================================*/
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/* defines for the registers: faster access to them when coding... */
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#define r_PC regs->PC.W
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#define r_PCl regs->PC.B.l
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#define r_PCh regs->PC.B.h
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#define r_SP regs->SP.W
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#define r_IFF1 regs->IFF1
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#define r_IFF2 regs->IFF2
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#define r_R regs->R.W
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#define r_AF regs->AF.W
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#define r_A regs->AF.B.h
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#define r_F regs->AF.B.l
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#define r_BC regs->BC.W
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#define r_B regs->BC.B.h
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#define r_C regs->BC.B.l
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#define r_DE regs->DE.W
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#define r_D regs->DE.B.h
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#define r_E regs->DE.B.l
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#define r_HL regs->HL.W
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#define r_H regs->HL.B.h
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#define r_L regs->HL.B.l
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#define r_IX regs->IX.W
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#define r_IXh regs->IX.B.h
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#define r_IXl regs->IX.B.l
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#define r_IY regs->IY.W
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#define r_IYh regs->IY.B.h
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#define r_IYl regs->IY.B.l
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#define r_AFs regs->AFs.W
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#define r_As regs->AFs.B.h
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#define r_Fs regs->AFs.B.l
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#define r_BCs regs->BCs.W
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#define r_Bs regs->BCs.B.h
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#define r_Cs regs->BCs.B.l
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#define r_DEs regs->DEs.W
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#define r_Ds regs->DEs.B.h
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#define r_Es regs->DEs.B.l
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#define r_HLs regs->HLs.W
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#define r_Hs regs->HLs.B.h
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#define r_Ls regs->HLs.B.l
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#define r_IXs regs->IX.W
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#define r_IXhs regs->IX.B.h
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#define r_IXls regs->IX.B.l
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#define r_IYs regs->IY.W
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#define r_IYhs regs->IY.B.h
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#define r_IYls regs->IY.B.l
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#define r_op ops.W
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#define r_oph ops.B.h
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#define r_opl ops.B.l
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#define r_tmp tmpreg2.W
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#define r_tmph tmpreg2.B.h
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#define r_tmpl tmpreg2.B.l
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#define r_mem mread.W
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#define r_memh mread.B.h
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#define r_meml mread.B.l
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#ifndef _DISASM_
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/*--- Flag tables by Philip Kendall, taken from it's fuse emulator -*/
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/*--- I was having headache trying to emulate correctly the FLAGS,
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so I finished using the FLAG tables used by P. Kendall. ------*/
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#define FLAG_C 0x01
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#define FLAG_N 0x02
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#define FLAG_P 0x04
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#define FLAG_V FLAG_P
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#define FLAG_3 0x08
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#define FLAG_H 0x10
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#define FLAG_5 0x20
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#define FLAG_Z 0x40
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#define FLAG_S 0x80
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/* Whether a half carry occured or not can be determined by looking at
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the 3rd bit of the two arguments and the result; these are hashed
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into this table in the form r12, where r is the 3rd bit of the
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result, 1 is the 3rd bit of the 1st argument and 2 is the
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third bit of the 2nd argument; the tables differ for add and subtract
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operations */
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/* Whether a half carry occured or not can be determined by looking at
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the 3rd bit of the two arguments and the result; these are hashed
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into this table in the form r12, where r is the 3rd bit of the
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result, 1 is the 3rd bit of the 1st argument and 2 is the
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third bit of the 2nd argument; the tables differ for add and subtract
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operations */
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byte halfcarry_add_table[] = { 0, FLAG_H, FLAG_H, FLAG_H, 0, 0, 0, FLAG_H };
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byte halfcarry_sub_table[] = { 0, 0, FLAG_H, 0, FLAG_H, 0, FLAG_H, FLAG_H };
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/* Similarly, overflow can be determined by looking at the 7th bits; again
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the hash into this table is r12 */
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byte overflow_add_table[] = { 0, 0, 0, FLAG_V, FLAG_V, 0, 0, 0 };
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byte overflow_sub_table[] = { 0, FLAG_V, 0, 0, 0, 0, FLAG_V, 0 };
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/* Some more tables; initialised in z80_init_tables() */
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byte sz53_table[0x100]; /* The S, Z, 5 and 3 bits of the temp value */
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byte parity_table[0x100]; /* The parity of the temp value */
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byte sz53p_table[0x100]; /* OR the above two tables together */
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/*------------------------------------------------------------------*/
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// Contributed by Metalbrain to implement OUTI, etc.
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byte ioblock_inc1_table[64];
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byte ioblock_dec1_table[64];
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byte ioblock_2_table[0x100];
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/*--- Memory Write on the A address on no bank machines -------------*/
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void Z80WriteMem( word where, word A, Z80Regs *regs)
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{
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if( where >= 16384 )
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regs->RAM[where] = A;
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}
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#endif
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/*--- Memory Read from the A address on no bank machines -------------*/
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#define Z80ReadMem(A) ((regs->RAM[(A)]))
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// return( regs->RAM[A] );
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/* macros to change the ICount register */
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#define AddCycles(n) regs->ICount-=(n)
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#define SubCycles(n) regs->ICount+=(n)
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//#define AddR(n) r_R = (r_R+(n))
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#define AddR(n) r_R = ((r_R & 0x80) | ((r_R+(n)) & 0x7f ))
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#define SubR(n) r_R = ((r_R & 0x80) | ((r_R-(n)) & 0x7f ))
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/* setting and resetting the flag bits: */
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#define SET_FLAG(flag) (r_F |= (flag))
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#define RESET_FLAG(flag) (r_F &= ~(flag))
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#define TEST_FLAG(flag) (r_F & (flag))
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/* store a given register in the stack (hi and lo bytes) */
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#define PUSH(rreg) \
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Z80WriteMem( --(r_SP), regs->rreg.B.h, regs); \
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Z80WriteMem( --(r_SP), regs->rreg.B.l, regs)
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#define POP(rreg)\
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regs->rreg.B.l = Z80ReadMem(r_SP); r_SP++;\
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regs->rreg.B.h = Z80ReadMem(r_SP); r_SP++
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#define PUSH_IXYr() \
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Z80WriteMem( --(r_SP), REGH, regs); \
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Z80WriteMem( --(r_SP), REGL, regs)
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#define POP_IXYr()\
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REGL = Z80ReadMem(r_SP); r_SP++; \
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REGH = Z80ReadMem(r_SP); r_SP++
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#define RST(rstval) PUSH(PC); r_PC=(rstval)
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/*--- Move data to mem or regs --------------------------------------*/
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#define LD_r_r(dreg, sreg) (dreg) = (sreg)
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#define STORE_r(daddreg, sreg) Z80WriteMem((daddreg), (sreg), regs)
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#define STORE_nn_rr(dreg) \
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r_opl = Z80ReadMem(r_PC); r_PC++;\
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r_oph = Z80ReadMem(r_PC); r_PC++; \
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r_tmp = dreg; \
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Z80WriteMem((r_op),r_tmpl, regs); \
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Z80WriteMem((r_op+1),r_tmph, regs)
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#define STORE_nn_r(sreg) \
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r_opl = Z80ReadMem(r_PC); r_PC++; \
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r_oph = Z80ReadMem(r_PC); r_PC++; \
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Z80WriteMem((r_op),(sreg), regs)
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#define LOAD_r(dreg, saddreg) (dreg)=Z80ReadMem((saddreg))
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#define LOAD_rr_nn(dreg) r_opl = Z80ReadMem(r_PC); r_PC++; \
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r_oph = Z80ReadMem(r_PC); r_PC++; \
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r_tmpl = Z80ReadMem(r_op); \
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r_tmph = Z80ReadMem((r_op)+1); \
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dreg=r_tmp
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#define LOAD_r_nn(dreg) r_opl = Z80ReadMem(r_PC); r_PC++; \
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r_oph = Z80ReadMem(r_PC); r_PC++; \
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dreg = Z80ReadMem(r_op)
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#define LD_r_n(reg) (reg) = Z80ReadMem(r_PC++)
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#define LD_rr_nn(reg) r_opl = Z80ReadMem(r_PC); r_PC++; \
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r_oph = Z80ReadMem(r_PC); r_PC++; \
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reg = r_op
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#define EX(reg1,reg2) r_opl=(reg1); (reg1)=(reg2); (reg2)=r_opl
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#define EX_WORD(reg1,reg2) r_op=(reg1); (reg1)=(reg2); (reg2)=r_op
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/*--- Increments/Decrements -----------------------------------------*/
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#define INC(reg) (reg)++; \
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r_F = ( r_F & FLAG_C ) | ( (reg)==0x80 ? FLAG_V : 0 ) | \
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( (reg)&0x0f ? 0 : FLAG_H ) | ( (reg) ? 0 : FLAG_Z ) | \
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sz53_table[(reg)]
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#define DEC(reg) \
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r_F = ( r_F & FLAG_C ) | ( (reg)&0x0f ? 0 : FLAG_H ) | FLAG_N; \
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(reg)--; \
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r_F |= ( (reg)==0x7f ? FLAG_V : 0 ) | sz53_table[(reg)]
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// it was:
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// r_F |= ( (reg)==0x79 ? FLAG_V : 0 ) | sz53_table[(reg)]
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// But Kak pointed my was not 0x79 -> 0x7F, changed 7-3-2001
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/*--- Bit operations ------------------------------------------------*/
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#define BIT_RES(b,reg) reg &= ~(0x1<<b)
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#define BIT_SET(b,reg) reg |= (0x1<<b)
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#define BIT_mem_RES(b,addr) r_opl = Z80ReadMem(addr); \
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r_opl &= ~(0x1<<b); \
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Z80WriteMem(addr, r_opl, regs)
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#define BIT_mem_SET(b,addr) r_opl = Z80ReadMem(addr); \
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r_opl |= (0x1<<b); \
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Z80WriteMem(addr, r_opl, regs)
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#define BIT_RES_mem(b,addr,reg) reg &= ~(0x1<<b); \
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Z80WriteMem((addr), (reg), regs)
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#define BIT_SET_mem(b,addr,reg) reg |= (0x1<<b); \
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Z80WriteMem((addr), (reg), regs)
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#define BIT_BIT(b,reg) r_F = ( r_F & FLAG_C ) | \
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( (reg) & ( FLAG_3 | FLAG_5 ) ) |\
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(((reg) & ( 0x01 << b ) ) ? FLAG_H : \
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(FLAG_P|FLAG_H|FLAG_Z ) )
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#define BIT_mem_BIT(b,reg) r_opl = Z80ReadMem(reg); \
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r_F = ( r_F & FLAG_C ) | \
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( (r_opl) & ( FLAG_3 | FLAG_5 ) ) |\
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(((r_opl) & ( 0x01 << b ) ) ? FLAG_H : \
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(FLAG_P|FLAG_H|FLAG_Z ) )
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#define BIT_BIT7(reg) r_F = ( r_F & FLAG_C ) | ( (reg) & \
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( FLAG_3 | FLAG_5 ) ) |\
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(((reg) & 0x80 ) ? ( FLAG_H | FLAG_S ) :\
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( FLAG_P | FLAG_H | FLAG_Z ) )
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#define BIT_mem_BIT7(reg) r_opl = Z80ReadMem(reg); \
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r_F = ( r_F & FLAG_C ) | ( (r_opl) & \
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( FLAG_3 | FLAG_5 ) ) |\
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(((r_opl) & 0x80 ) ? ( FLAG_H | FLAG_S ) :\
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( FLAG_P | FLAG_H | FLAG_Z ) )
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#define RLC(reg) (reg) = ( (reg)<<1 ) | ( (reg)>>7 ); \
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r_F = ( (reg) & FLAG_C ) | sz53p_table[(reg)]
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#define RRC(reg) r_F = (reg) & FLAG_C; \
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(reg) = ( (reg)>>1 ) | ( (reg)<<7 );\
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r_F |= sz53p_table[(reg)]
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#define RL(reg) r_opl = (reg); \
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(reg) = ( (reg)<<1 ) | ( r_F & FLAG_C ); \
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r_F = ( r_opl >> 7 ) | sz53p_table[(reg)]
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#define RR(reg) r_opl = (reg); \
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(reg) = ( (reg)>>1 ) | ( r_F << 7 );\
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r_F = ( r_opl & FLAG_C ) | sz53p_table[(reg)]
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#define SLA(reg) r_F = (reg) >> 7;\
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(reg) <<= 1;\
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r_F |= sz53p_table[(reg)]
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#define SRA(reg) r_F = (reg) & FLAG_C; \
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(reg) = ( (reg) & 0x80 ) | ( (reg) >> 1 );\
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r_F |= sz53p_table[(reg)]
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#define SLL(reg) r_F = (reg) >> 7;\
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(reg) = ( (reg) << 1 ) | 0x01;\
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r_F |= sz53p_table[(reg)]
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#define SRL(reg) r_F = (reg) & FLAG_C;\
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(reg) >>= 1;\
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r_F |= sz53p_table[(reg)]
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/*--- JP operations -------------------------------------------------*/
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#define JP_nn() r_opl = Z80ReadMem(r_PC); \
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r_PC++; \
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r_oph = Z80ReadMem(r_PC); \
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r_PC = r_op
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#define JR_n() r_PC += (offset) (Z80ReadMem(r_PC)); r_PC++
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#define RET_nn() r_PCl = Z80ReadMem (r_SP); r_SP++; \
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r_PCh = Z80ReadMem (r_SP); r_SP++;
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#define CALL_nn() r_opl = Z80ReadMem (r_PC); r_PC++; \
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r_oph = Z80ReadMem (r_PC); r_PC++; \
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Z80WriteMem( --(r_SP), r_PCh, regs ); \
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Z80WriteMem( --(r_SP), r_PCl, regs ); \
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r_PC = r_op
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/*--- ALU operations ------------------------------------------------*/
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#define AND(reg) r_A &= (reg); \
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r_F = FLAG_H | sz53p_table[r_A]
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#define OR(reg) r_A |= (reg); \
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r_F = sz53p_table[r_A]
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#define XOR(reg) r_A ^= (reg); \
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r_F = sz53p_table[r_A]
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#define AND_mem(raddress) r_opl = Z80ReadMem(raddress); \
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r_A &= (r_opl); \
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r_F = FLAG_H | sz53p_table[r_A]
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#define OR_mem(raddress) r_opl = Z80ReadMem(raddress); \
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r_A |= (r_opl); \
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r_F = sz53p_table[r_A]
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#define XOR_mem(raddress) r_opl = Z80ReadMem(raddress); \
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r_A ^= (r_opl); \
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r_F = sz53p_table[r_A]
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#define ADD(val) tempword = r_A + (val); \
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r_oph = ((r_A&0x88)>>3)|(((val)&0x88)>>2) | \
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( (tempword & 0x88) >> 1 ); \
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r_A = tempword; \
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r_F = ( tempword & 0x100 ? FLAG_C : 0 ) | \
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halfcarry_add_table[ r_oph & 0x07] | \
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overflow_add_table[ r_oph >> 4] | \
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sz53_table[r_A]
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#define ADD_WORD(value1,value2) \
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tempdword = (value1) + (value2); \
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r_oph = ( ( (value1) & 0x0800 ) >> 11 ) | \
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( ( (value2) & 0x0800 ) >> 10 ) | \
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( ( tempdword & 0x0800 ) >> 9 ); \
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(value1) = tempdword; \
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r_F = ( r_F & ( FLAG_V | FLAG_Z | FLAG_S ) ) | \
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( tempdword & 0x10000 ? FLAG_C : 0 ) | \
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(( tempdword >> 8 ) & ( FLAG_3 | FLAG_5 ) ) | \
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halfcarry_add_table[r_oph]
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#define ADC(value) \
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tempword = r_A + (value) + ( r_F & FLAG_C ); \
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r_oph = ( (r_A & 0x88) >> 3 ) | ( ( (value) & 0x88 ) >> 2 ) |\
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( (tempword & 0x88) >> 1 ); \
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r_A = tempword; \
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r_F = ( tempword & 0x100 ? FLAG_C : 0 ) | \
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halfcarry_add_table[r_oph & 0x07] | \
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overflow_add_table[r_oph >> 4] | \
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sz53_table[r_A]
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#define ADC_WORD(value) \
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tempdword= r_HL + (value) + ( r_F & FLAG_C ); \
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r_oph = ( ( r_HL & 0x8800 ) >> 11 ) | \
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( ( (value) & 0x8800 ) >> 10 ) | \
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( ( tempdword & 0x8800 ) >> 9 ); \
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r_HL = tempdword; \
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r_F = ( tempdword & 0x10000 ? FLAG_C : 0 )| \
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overflow_add_table[r_oph >> 4] | \
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( r_H & ( FLAG_3 | FLAG_5 | FLAG_S ) ) | \
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halfcarry_add_table[ r_oph & 0x0f ]| \
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( r_HL ? 0 : FLAG_Z )
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#define SUB(value) \
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tempword = r_A - (value);\
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r_opl = ( (r_A & 0x88) >> 3 ) | \
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( ( (value) & 0x88 ) >> 2 ) | \
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( (tempword & 0x88) >> 1 ); \
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r_A = tempword; \
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r_F = ( tempword & 0x100 ? FLAG_C : 0 ) | FLAG_N | \
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halfcarry_sub_table[r_opl & 0x07] | \
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overflow_sub_table[r_opl >> 4] | \
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sz53_table[r_A]
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#define SBC(value) \
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tempword = r_A - (value) - ( r_F & FLAG_C ); \
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r_opl = ( (r_A & 0x88) >> 3 ) | \
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( ( (value) & 0x88 ) >> 2 ) | \
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( (tempword & 0x88) >> 1 ); \
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r_A = tempword; \
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r_F = ( tempword & 0x100 ? FLAG_C : 0 ) | FLAG_N | \
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halfcarry_sub_table[r_opl & 0x07] | \
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overflow_sub_table[r_opl >> 4] | \
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sz53_table[r_A]
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#define SBC_WORD(Rg) \
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tempword=r_F & C_FLAG; r_op=(r_HL-Rg-tempword)&0xFFFF; \
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r_F= \
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N_FLAG| \
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(((long)r_HL-(long)Rg-(long)tempword)&0x10000? C_FLAG:0)| \
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((r_HL^Rg)&(r_HL^r_op)&0x8000? O_FLAG:0)| \
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((r_HL^Rg^r_op)&0x1000? H_FLAG:0)| \
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(r_op? 0:Z_FLAG)|(r_oph&S_FLAG); \
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r_HL=r_op
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#define CP(value) \
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tempword = r_A - (value);\
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r_opl = ( (r_A & 0x88) >> 3 ) | ( ( (value) & 0x88 ) >> 2 ) | \
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( (tempword & 0x88) >> 1 ); \
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r_F = ( tempword & 0x100 ? FLAG_C : ( tempword ? 0 : FLAG_Z ) ) | FLAG_N |\
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halfcarry_sub_table[r_opl & 0x07] | \
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overflow_sub_table[r_opl >> 4] | \
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( value & ( FLAG_3 | FLAG_5 ) ) | \
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( tempword & FLAG_S )
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#define NEG_A() r_opl = r_A; r_A=0; SUB(r_opl)
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/*--- MISC operations -----------------------------------------------*/
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#define IN(reg,port) (reg)=Z80InPort((port)); \
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r_F = ( r_F & FLAG_C) | sz53p_table[(reg)]
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