873 lines
28 KiB
C
873 lines
28 KiB
C
/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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//#include <linux/console.h>
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#include <drm/drmP.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/radeon_drm.h>
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//#include <linux/vgaarb.h>
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//#include <linux/vga_switcheroo.h>
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#include "radeon_reg.h"
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#include "radeon.h"
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#include "radeon_asic.h"
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#include "atom.h"
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/*
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* Registers accessors functions.
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*/
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static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
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{
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DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
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BUG_ON(1);
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return 0;
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}
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static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
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{
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DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
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reg, v);
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BUG_ON(1);
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}
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static void radeon_register_accessor_init(struct radeon_device *rdev)
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{
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rdev->mc_rreg = &radeon_invalid_rreg;
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rdev->mc_wreg = &radeon_invalid_wreg;
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rdev->pll_rreg = &radeon_invalid_rreg;
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rdev->pll_wreg = &radeon_invalid_wreg;
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rdev->pciep_rreg = &radeon_invalid_rreg;
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rdev->pciep_wreg = &radeon_invalid_wreg;
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/* Don't change order as we are overridding accessor. */
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if (rdev->family < CHIP_RV515) {
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rdev->pcie_reg_mask = 0xff;
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} else {
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rdev->pcie_reg_mask = 0x7ff;
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}
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/* FIXME: not sure here */
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if (rdev->family <= CHIP_R580) {
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rdev->pll_rreg = &r100_pll_rreg;
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rdev->pll_wreg = &r100_pll_wreg;
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}
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if (rdev->family >= CHIP_R420) {
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rdev->mc_rreg = &r420_mc_rreg;
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rdev->mc_wreg = &r420_mc_wreg;
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}
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if (rdev->family >= CHIP_RV515) {
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rdev->mc_rreg = &rv515_mc_rreg;
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rdev->mc_wreg = &rv515_mc_wreg;
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}
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if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
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rdev->mc_rreg = &rs400_mc_rreg;
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rdev->mc_wreg = &rs400_mc_wreg;
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}
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if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
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rdev->mc_rreg = &rs690_mc_rreg;
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rdev->mc_wreg = &rs690_mc_wreg;
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}
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if (rdev->family == CHIP_RS600) {
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rdev->mc_rreg = &rs600_mc_rreg;
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rdev->mc_wreg = &rs600_mc_wreg;
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}
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if (rdev->family >= CHIP_R600) {
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rdev->pciep_rreg = &r600_pciep_rreg;
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rdev->pciep_wreg = &r600_pciep_wreg;
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}
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}
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/* helper to disable agp */
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void radeon_agp_disable(struct radeon_device *rdev)
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{
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rdev->flags &= ~RADEON_IS_AGP;
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if (rdev->family >= CHIP_R600) {
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DRM_INFO("Forcing AGP to PCIE mode\n");
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rdev->flags |= RADEON_IS_PCIE;
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} else if (rdev->family >= CHIP_RV515 ||
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rdev->family == CHIP_RV380 ||
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rdev->family == CHIP_RV410 ||
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rdev->family == CHIP_R423) {
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DRM_INFO("Forcing AGP to PCIE mode\n");
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rdev->flags |= RADEON_IS_PCIE;
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rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
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rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
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} else {
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DRM_INFO("Forcing AGP to PCI mode\n");
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rdev->flags |= RADEON_IS_PCI;
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rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
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rdev->asic->gart_set_page = &r100_pci_gart_set_page;
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}
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rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
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}
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/*
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* ASIC
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*/
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static struct radeon_asic r100_asic = {
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.init = &r100_init,
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// .fini = &r100_fini,
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// .suspend = &r100_suspend,
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// .resume = &r100_resume,
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// .vga_set_state = &r100_vga_set_state,
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.asic_reset = &r100_asic_reset,
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.gart_tlb_flush = &r100_pci_gart_tlb_flush,
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.gart_set_page = &r100_pci_gart_set_page,
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.cp_commit = &r100_cp_commit,
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.ring_start = &r100_ring_start,
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.ring_test = &r100_ring_test,
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// .ring_ib_execute = &r100_ring_ib_execute,
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// .irq_set = &r100_irq_set,
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// .irq_process = &r100_irq_process,
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// .get_vblank_counter = &r100_get_vblank_counter,
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.fence_ring_emit = &r100_fence_ring_emit,
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// .cs_parse = &r100_cs_parse,
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// .copy_blit = &r100_copy_blit,
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// .copy_dma = NULL,
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// .copy = &r100_copy_blit,
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.get_engine_clock = &radeon_legacy_get_engine_clock,
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.set_engine_clock = &radeon_legacy_set_engine_clock,
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.get_memory_clock = &radeon_legacy_get_memory_clock,
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.set_memory_clock = NULL,
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.get_pcie_lanes = NULL,
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.set_pcie_lanes = NULL,
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.set_clock_gating = &radeon_legacy_set_clock_gating,
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.set_surface_reg = r100_set_surface_reg,
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.clear_surface_reg = r100_clear_surface_reg,
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.bandwidth_update = &r100_bandwidth_update,
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.hpd_init = &r100_hpd_init,
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.hpd_fini = &r100_hpd_fini,
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.hpd_sense = &r100_hpd_sense,
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.hpd_set_polarity = &r100_hpd_set_polarity,
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.ioctl_wait_idle = NULL,
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};
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static struct radeon_asic r200_asic = {
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.init = &r100_init,
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// .fini = &r100_fini,
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// .suspend = &r100_suspend,
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// .resume = &r100_resume,
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// .vga_set_state = &r100_vga_set_state,
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.asic_reset = &r100_asic_reset,
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.gart_tlb_flush = &r100_pci_gart_tlb_flush,
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.gart_set_page = &r100_pci_gart_set_page,
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.cp_commit = &r100_cp_commit,
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.ring_start = &r100_ring_start,
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.ring_test = &r100_ring_test,
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// .ring_ib_execute = &r100_ring_ib_execute,
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// .irq_set = &r100_irq_set,
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// .irq_process = &r100_irq_process,
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// .get_vblank_counter = &r100_get_vblank_counter,
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.fence_ring_emit = &r100_fence_ring_emit,
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// .cs_parse = &r100_cs_parse,
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// .copy_blit = &r100_copy_blit,
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// .copy_dma = NULL,
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// .copy = &r100_copy_blit,
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.get_engine_clock = &radeon_legacy_get_engine_clock,
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.set_engine_clock = &radeon_legacy_set_engine_clock,
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.get_memory_clock = &radeon_legacy_get_memory_clock,
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.set_memory_clock = NULL,
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.set_pcie_lanes = NULL,
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.set_clock_gating = &radeon_legacy_set_clock_gating,
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.set_surface_reg = r100_set_surface_reg,
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.clear_surface_reg = r100_clear_surface_reg,
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.bandwidth_update = &r100_bandwidth_update,
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.hpd_init = &r100_hpd_init,
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.hpd_fini = &r100_hpd_fini,
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.hpd_sense = &r100_hpd_sense,
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.hpd_set_polarity = &r100_hpd_set_polarity,
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.ioctl_wait_idle = NULL,
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};
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static struct radeon_asic r300_asic = {
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.init = &r300_init,
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// .fini = &r300_fini,
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// .suspend = &r300_suspend,
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// .resume = &r300_resume,
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// .vga_set_state = &r100_vga_set_state,
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.asic_reset = &r300_asic_reset,
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.gart_tlb_flush = &r100_pci_gart_tlb_flush,
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.gart_set_page = &r100_pci_gart_set_page,
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.cp_commit = &r100_cp_commit,
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.ring_start = &r300_ring_start,
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.ring_test = &r100_ring_test,
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// .ring_ib_execute = &r100_ring_ib_execute,
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// .irq_set = &r100_irq_set,
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// .irq_process = &r100_irq_process,
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// .get_vblank_counter = &r100_get_vblank_counter,
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.fence_ring_emit = &r300_fence_ring_emit,
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// .cs_parse = &r300_cs_parse,
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// .copy_blit = &r100_copy_blit,
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// .copy_dma = &r300_copy_dma,
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// .copy = &r100_copy_blit,
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.get_engine_clock = &radeon_legacy_get_engine_clock,
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.set_engine_clock = &radeon_legacy_set_engine_clock,
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.get_memory_clock = &radeon_legacy_get_memory_clock,
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.set_memory_clock = NULL,
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.get_pcie_lanes = &rv370_get_pcie_lanes,
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.set_pcie_lanes = &rv370_set_pcie_lanes,
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.set_clock_gating = &radeon_legacy_set_clock_gating,
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.set_surface_reg = r100_set_surface_reg,
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.clear_surface_reg = r100_clear_surface_reg,
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.bandwidth_update = &r100_bandwidth_update,
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.hpd_init = &r100_hpd_init,
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.hpd_fini = &r100_hpd_fini,
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.hpd_sense = &r100_hpd_sense,
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.hpd_set_polarity = &r100_hpd_set_polarity,
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.ioctl_wait_idle = NULL,
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};
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static struct radeon_asic r300_asic_pcie = {
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.init = &r300_init,
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// .fini = &r300_fini,
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// .suspend = &r300_suspend,
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// .resume = &r300_resume,
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// .vga_set_state = &r100_vga_set_state,
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.asic_reset = &r300_asic_reset,
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.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
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.gart_set_page = &rv370_pcie_gart_set_page,
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.cp_commit = &r100_cp_commit,
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.ring_start = &r300_ring_start,
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.ring_test = &r100_ring_test,
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// .ring_ib_execute = &r100_ring_ib_execute,
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// .irq_set = &r100_irq_set,
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// .irq_process = &r100_irq_process,
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// .get_vblank_counter = &r100_get_vblank_counter,
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.fence_ring_emit = &r300_fence_ring_emit,
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// .cs_parse = &r300_cs_parse,
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// .copy_blit = &r100_copy_blit,
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// .copy_dma = &r300_copy_dma,
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// .copy = &r100_copy_blit,
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.get_engine_clock = &radeon_legacy_get_engine_clock,
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.set_engine_clock = &radeon_legacy_set_engine_clock,
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.get_memory_clock = &radeon_legacy_get_memory_clock,
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.set_memory_clock = NULL,
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.set_pcie_lanes = &rv370_set_pcie_lanes,
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.set_clock_gating = &radeon_legacy_set_clock_gating,
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.set_surface_reg = r100_set_surface_reg,
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.clear_surface_reg = r100_clear_surface_reg,
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.bandwidth_update = &r100_bandwidth_update,
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.hpd_init = &r100_hpd_init,
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.hpd_fini = &r100_hpd_fini,
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.hpd_sense = &r100_hpd_sense,
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.hpd_set_polarity = &r100_hpd_set_polarity,
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.ioctl_wait_idle = NULL,
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};
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static struct radeon_asic r420_asic = {
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.init = &r420_init,
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// .fini = &r420_fini,
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// .suspend = &r420_suspend,
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// .resume = &r420_resume,
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// .vga_set_state = &r100_vga_set_state,
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.asic_reset = &r300_asic_reset,
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.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
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.gart_set_page = &rv370_pcie_gart_set_page,
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.cp_commit = &r100_cp_commit,
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.ring_start = &r300_ring_start,
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.ring_test = &r100_ring_test,
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// .ring_ib_execute = &r100_ring_ib_execute,
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// .irq_set = &r100_irq_set,
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// .irq_process = &r100_irq_process,
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// .get_vblank_counter = &r100_get_vblank_counter,
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.fence_ring_emit = &r300_fence_ring_emit,
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// .cs_parse = &r300_cs_parse,
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// .copy_blit = &r100_copy_blit,
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// .copy_dma = &r300_copy_dma,
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// .copy = &r100_copy_blit,
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.get_engine_clock = &radeon_atom_get_engine_clock,
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.set_engine_clock = &radeon_atom_set_engine_clock,
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.get_memory_clock = &radeon_atom_get_memory_clock,
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.set_memory_clock = &radeon_atom_set_memory_clock,
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.get_pcie_lanes = &rv370_get_pcie_lanes,
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.set_pcie_lanes = &rv370_set_pcie_lanes,
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.set_clock_gating = &radeon_atom_set_clock_gating,
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.set_surface_reg = r100_set_surface_reg,
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.clear_surface_reg = r100_clear_surface_reg,
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.bandwidth_update = &r100_bandwidth_update,
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.hpd_init = &r100_hpd_init,
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.hpd_fini = &r100_hpd_fini,
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.hpd_sense = &r100_hpd_sense,
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.hpd_set_polarity = &r100_hpd_set_polarity,
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.ioctl_wait_idle = NULL,
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};
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static struct radeon_asic rs400_asic = {
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.init = &rs400_init,
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// .fini = &rs400_fini,
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// .suspend = &rs400_suspend,
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// .resume = &rs400_resume,
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// .vga_set_state = &r100_vga_set_state,
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.asic_reset = &r300_asic_reset,
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.gart_tlb_flush = &rs400_gart_tlb_flush,
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.gart_set_page = &rs400_gart_set_page,
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.cp_commit = &r100_cp_commit,
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.ring_start = &r300_ring_start,
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.ring_test = &r100_ring_test,
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// .ring_ib_execute = &r100_ring_ib_execute,
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// .irq_set = &r100_irq_set,
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// .irq_process = &r100_irq_process,
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// .get_vblank_counter = &r100_get_vblank_counter,
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.fence_ring_emit = &r300_fence_ring_emit,
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// .cs_parse = &r300_cs_parse,
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// .copy_blit = &r100_copy_blit,
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// .copy_dma = &r300_copy_dma,
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// .copy = &r100_copy_blit,
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.get_engine_clock = &radeon_legacy_get_engine_clock,
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.set_engine_clock = &radeon_legacy_set_engine_clock,
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.get_memory_clock = &radeon_legacy_get_memory_clock,
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.set_memory_clock = NULL,
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.get_pcie_lanes = NULL,
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.set_pcie_lanes = NULL,
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.set_clock_gating = &radeon_legacy_set_clock_gating,
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.set_surface_reg = r100_set_surface_reg,
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.clear_surface_reg = r100_clear_surface_reg,
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.bandwidth_update = &r100_bandwidth_update,
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.hpd_init = &r100_hpd_init,
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.hpd_fini = &r100_hpd_fini,
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.hpd_sense = &r100_hpd_sense,
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.hpd_set_polarity = &r100_hpd_set_polarity,
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.ioctl_wait_idle = NULL,
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};
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static struct radeon_asic rs600_asic = {
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.init = &rs600_init,
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// .fini = &rs600_fini,
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// .suspend = &rs600_suspend,
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// .resume = &rs600_resume,
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// .vga_set_state = &r100_vga_set_state,
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.asic_reset = &rs600_asic_reset,
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.gart_tlb_flush = &rs600_gart_tlb_flush,
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.gart_set_page = &rs600_gart_set_page,
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.cp_commit = &r100_cp_commit,
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.ring_start = &r300_ring_start,
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.ring_test = &r100_ring_test,
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// .ring_ib_execute = &r100_ring_ib_execute,
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// .irq_set = &rs600_irq_set,
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// .irq_process = &rs600_irq_process,
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// .get_vblank_counter = &rs600_get_vblank_counter,
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.fence_ring_emit = &r300_fence_ring_emit,
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// .cs_parse = &r300_cs_parse,
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// .copy_blit = &r100_copy_blit,
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// .copy_dma = &r300_copy_dma,
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// .copy = &r100_copy_blit,
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.get_engine_clock = &radeon_atom_get_engine_clock,
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.set_engine_clock = &radeon_atom_set_engine_clock,
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.get_memory_clock = &radeon_atom_get_memory_clock,
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.set_memory_clock = &radeon_atom_set_memory_clock,
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.get_pcie_lanes = NULL,
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.set_pcie_lanes = NULL,
|
|
.set_clock_gating = &radeon_atom_set_clock_gating,
|
|
.set_surface_reg = r100_set_surface_reg,
|
|
.clear_surface_reg = r100_clear_surface_reg,
|
|
.bandwidth_update = &rs600_bandwidth_update,
|
|
.hpd_init = &rs600_hpd_init,
|
|
.hpd_fini = &rs600_hpd_fini,
|
|
.hpd_sense = &rs600_hpd_sense,
|
|
.hpd_set_polarity = &rs600_hpd_set_polarity,
|
|
.ioctl_wait_idle = NULL,
|
|
};
|
|
|
|
static struct radeon_asic rs690_asic = {
|
|
.init = &rs690_init,
|
|
// .fini = &rs690_fini,
|
|
// .suspend = &rs690_suspend,
|
|
// .resume = &rs690_resume,
|
|
// .vga_set_state = &r100_vga_set_state,
|
|
.asic_reset = &rs600_asic_reset,
|
|
.gart_tlb_flush = &rs400_gart_tlb_flush,
|
|
.gart_set_page = &rs400_gart_set_page,
|
|
.cp_commit = &r100_cp_commit,
|
|
.ring_start = &r300_ring_start,
|
|
.ring_test = &r100_ring_test,
|
|
// .ring_ib_execute = &r100_ring_ib_execute,
|
|
// .irq_set = &rs600_irq_set,
|
|
// .irq_process = &rs600_irq_process,
|
|
// .get_vblank_counter = &rs600_get_vblank_counter,
|
|
.fence_ring_emit = &r300_fence_ring_emit,
|
|
// .cs_parse = &r300_cs_parse,
|
|
// .copy_blit = &r100_copy_blit,
|
|
// .copy_dma = &r300_copy_dma,
|
|
// .copy = &r300_copy_dma,
|
|
.get_engine_clock = &radeon_atom_get_engine_clock,
|
|
.set_engine_clock = &radeon_atom_set_engine_clock,
|
|
.get_memory_clock = &radeon_atom_get_memory_clock,
|
|
.set_memory_clock = &radeon_atom_set_memory_clock,
|
|
.get_pcie_lanes = NULL,
|
|
.set_pcie_lanes = NULL,
|
|
.set_clock_gating = &radeon_atom_set_clock_gating,
|
|
.set_surface_reg = r100_set_surface_reg,
|
|
.clear_surface_reg = r100_clear_surface_reg,
|
|
.bandwidth_update = &rs690_bandwidth_update,
|
|
.hpd_init = &rs600_hpd_init,
|
|
.hpd_fini = &rs600_hpd_fini,
|
|
.hpd_sense = &rs600_hpd_sense,
|
|
.hpd_set_polarity = &rs600_hpd_set_polarity,
|
|
.ioctl_wait_idle = NULL,
|
|
};
|
|
|
|
static struct radeon_asic rv515_asic = {
|
|
.init = &rv515_init,
|
|
// .fini = &rv515_fini,
|
|
// .suspend = &rv515_suspend,
|
|
// .resume = &rv515_resume,
|
|
// .vga_set_state = &r100_vga_set_state,
|
|
.asic_reset = &rs600_asic_reset,
|
|
.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
|
|
.gart_set_page = &rv370_pcie_gart_set_page,
|
|
.cp_commit = &r100_cp_commit,
|
|
.ring_start = &rv515_ring_start,
|
|
.ring_test = &r100_ring_test,
|
|
// .ring_ib_execute = &r100_ring_ib_execute,
|
|
// .irq_set = &rs600_irq_set,
|
|
// .irq_process = &rs600_irq_process,
|
|
// .get_vblank_counter = &rs600_get_vblank_counter,
|
|
.fence_ring_emit = &r300_fence_ring_emit,
|
|
// .cs_parse = &r300_cs_parse,
|
|
// .copy_blit = &r100_copy_blit,
|
|
// .copy_dma = &r300_copy_dma,
|
|
// .copy = &r100_copy_blit,
|
|
.get_engine_clock = &radeon_atom_get_engine_clock,
|
|
.set_engine_clock = &radeon_atom_set_engine_clock,
|
|
.get_memory_clock = &radeon_atom_get_memory_clock,
|
|
.set_memory_clock = &radeon_atom_set_memory_clock,
|
|
.get_pcie_lanes = &rv370_get_pcie_lanes,
|
|
.set_pcie_lanes = &rv370_set_pcie_lanes,
|
|
.set_clock_gating = &radeon_atom_set_clock_gating,
|
|
.set_surface_reg = r100_set_surface_reg,
|
|
.clear_surface_reg = r100_clear_surface_reg,
|
|
.bandwidth_update = &rv515_bandwidth_update,
|
|
.hpd_init = &rs600_hpd_init,
|
|
.hpd_fini = &rs600_hpd_fini,
|
|
.hpd_sense = &rs600_hpd_sense,
|
|
.hpd_set_polarity = &rs600_hpd_set_polarity,
|
|
.ioctl_wait_idle = NULL,
|
|
};
|
|
|
|
static struct radeon_asic r520_asic = {
|
|
.init = &r520_init,
|
|
// .fini = &rv515_fini,
|
|
// .suspend = &rv515_suspend,
|
|
// .resume = &r520_resume,
|
|
// .vga_set_state = &r100_vga_set_state,
|
|
.asic_reset = &rs600_asic_reset,
|
|
.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
|
|
.gart_set_page = &rv370_pcie_gart_set_page,
|
|
.cp_commit = &r100_cp_commit,
|
|
.ring_start = &rv515_ring_start,
|
|
.ring_test = &r100_ring_test,
|
|
// .ring_ib_execute = &r100_ring_ib_execute,
|
|
// .irq_set = &rs600_irq_set,
|
|
// .irq_process = &rs600_irq_process,
|
|
// .get_vblank_counter = &rs600_get_vblank_counter,
|
|
.fence_ring_emit = &r300_fence_ring_emit,
|
|
// .cs_parse = &r300_cs_parse,
|
|
// .copy_blit = &r100_copy_blit,
|
|
// .copy_dma = &r300_copy_dma,
|
|
// .copy = &r100_copy_blit,
|
|
.get_engine_clock = &radeon_atom_get_engine_clock,
|
|
.set_engine_clock = &radeon_atom_set_engine_clock,
|
|
.get_memory_clock = &radeon_atom_get_memory_clock,
|
|
.set_memory_clock = &radeon_atom_set_memory_clock,
|
|
.get_pcie_lanes = &rv370_get_pcie_lanes,
|
|
.set_pcie_lanes = &rv370_set_pcie_lanes,
|
|
.set_clock_gating = &radeon_atom_set_clock_gating,
|
|
.set_surface_reg = r100_set_surface_reg,
|
|
.clear_surface_reg = r100_clear_surface_reg,
|
|
.bandwidth_update = &rv515_bandwidth_update,
|
|
.hpd_init = &rs600_hpd_init,
|
|
.hpd_fini = &rs600_hpd_fini,
|
|
.hpd_sense = &rs600_hpd_sense,
|
|
.hpd_set_polarity = &rs600_hpd_set_polarity,
|
|
.ioctl_wait_idle = NULL,
|
|
};
|
|
|
|
static struct radeon_asic r600_asic = {
|
|
.init = &r600_init,
|
|
// .fini = &r600_fini,
|
|
// .suspend = &r600_suspend,
|
|
// .resume = &r600_resume,
|
|
.cp_commit = &r600_cp_commit,
|
|
.vga_set_state = &r600_vga_set_state,
|
|
.asic_reset = &r600_asic_reset,
|
|
.gart_tlb_flush = &r600_pcie_gart_tlb_flush,
|
|
.gart_set_page = &rs600_gart_set_page,
|
|
.ring_test = &r600_ring_test,
|
|
// .ring_ib_execute = &r600_ring_ib_execute,
|
|
.irq_set = &r600_irq_set,
|
|
.irq_process = &r600_irq_process,
|
|
.fence_ring_emit = &r600_fence_ring_emit,
|
|
// .cs_parse = &r600_cs_parse,
|
|
// .copy_blit = &r600_copy_blit,
|
|
// .copy_dma = &r600_copy_blit,
|
|
// .copy = &r600_copy_blit,
|
|
.get_engine_clock = &radeon_atom_get_engine_clock,
|
|
.set_engine_clock = &radeon_atom_set_engine_clock,
|
|
.get_memory_clock = &radeon_atom_get_memory_clock,
|
|
.set_memory_clock = &radeon_atom_set_memory_clock,
|
|
.get_pcie_lanes = &rv370_get_pcie_lanes,
|
|
.set_pcie_lanes = NULL,
|
|
.set_clock_gating = NULL,
|
|
.set_surface_reg = r600_set_surface_reg,
|
|
.clear_surface_reg = r600_clear_surface_reg,
|
|
.bandwidth_update = &rv515_bandwidth_update,
|
|
.hpd_init = &r600_hpd_init,
|
|
.hpd_fini = &r600_hpd_fini,
|
|
.hpd_sense = &r600_hpd_sense,
|
|
.hpd_set_polarity = &r600_hpd_set_polarity,
|
|
// .ioctl_wait_idle = r600_ioctl_wait_idle,
|
|
};
|
|
|
|
static struct radeon_asic rs780_asic = {
|
|
.init = &r600_init,
|
|
// .fini = &r600_fini,
|
|
// .suspend = &r600_suspend,
|
|
// .resume = &r600_resume,
|
|
.cp_commit = &r600_cp_commit,
|
|
.gpu_is_lockup = &r600_gpu_is_lockup,
|
|
.vga_set_state = &r600_vga_set_state,
|
|
.asic_reset = &r600_asic_reset,
|
|
.gart_tlb_flush = &r600_pcie_gart_tlb_flush,
|
|
.gart_set_page = &rs600_gart_set_page,
|
|
.ring_test = &r600_ring_test,
|
|
// .ring_ib_execute = &r600_ring_ib_execute,
|
|
.irq_set = &r600_irq_set,
|
|
.irq_process = &r600_irq_process,
|
|
.fence_ring_emit = &r600_fence_ring_emit,
|
|
// .cs_parse = &r600_cs_parse,
|
|
// .copy_blit = &r600_copy_blit,
|
|
// .copy_dma = &r600_copy_blit,
|
|
// .copy = &r600_copy_blit,
|
|
.get_engine_clock = &radeon_atom_get_engine_clock,
|
|
.set_engine_clock = &radeon_atom_set_engine_clock,
|
|
.get_memory_clock = NULL,
|
|
.set_memory_clock = NULL,
|
|
.get_pcie_lanes = NULL,
|
|
.set_pcie_lanes = NULL,
|
|
.set_clock_gating = NULL,
|
|
.set_surface_reg = r600_set_surface_reg,
|
|
.clear_surface_reg = r600_clear_surface_reg,
|
|
.bandwidth_update = &rs690_bandwidth_update,
|
|
.hpd_init = &r600_hpd_init,
|
|
.hpd_fini = &r600_hpd_fini,
|
|
.hpd_sense = &r600_hpd_sense,
|
|
.hpd_set_polarity = &r600_hpd_set_polarity,
|
|
};
|
|
|
|
static struct radeon_asic rv770_asic = {
|
|
.init = &rv770_init,
|
|
// .fini = &rv770_fini,
|
|
// .suspend = &rv770_suspend,
|
|
// .resume = &rv770_resume,
|
|
.cp_commit = &r600_cp_commit,
|
|
.asic_reset = &r600_asic_reset,
|
|
.vga_set_state = &r600_vga_set_state,
|
|
.gart_tlb_flush = &r600_pcie_gart_tlb_flush,
|
|
.gart_set_page = &rs600_gart_set_page,
|
|
.ring_test = &r600_ring_test,
|
|
.ring_ib_execute = &r600_ring_ib_execute,
|
|
.irq_set = &r600_irq_set,
|
|
.irq_process = &r600_irq_process,
|
|
.fence_ring_emit = &r600_fence_ring_emit,
|
|
// .cs_parse = &r600_cs_parse,
|
|
// .copy_blit = &r600_copy_blit,
|
|
// .copy_dma = &r600_copy_blit,
|
|
// .copy = &r600_copy_blit,
|
|
.get_engine_clock = &radeon_atom_get_engine_clock,
|
|
.set_engine_clock = &radeon_atom_set_engine_clock,
|
|
.get_memory_clock = &radeon_atom_get_memory_clock,
|
|
.set_memory_clock = &radeon_atom_set_memory_clock,
|
|
.get_pcie_lanes = &rv370_get_pcie_lanes,
|
|
.set_pcie_lanes = NULL,
|
|
.set_clock_gating = &radeon_atom_set_clock_gating,
|
|
.set_surface_reg = r600_set_surface_reg,
|
|
.clear_surface_reg = r600_clear_surface_reg,
|
|
.bandwidth_update = &rv515_bandwidth_update,
|
|
.hpd_init = &r600_hpd_init,
|
|
.hpd_fini = &r600_hpd_fini,
|
|
.hpd_sense = &r600_hpd_sense,
|
|
.hpd_set_polarity = &r600_hpd_set_polarity,
|
|
};
|
|
|
|
static struct radeon_asic evergreen_asic = {
|
|
.init = &evergreen_init,
|
|
// .fini = &evergreen_fini,
|
|
// .suspend = &evergreen_suspend,
|
|
// .resume = &evergreen_resume,
|
|
.cp_commit = &r600_cp_commit,
|
|
.asic_reset = &evergreen_asic_reset,
|
|
.vga_set_state = &r600_vga_set_state,
|
|
.gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
|
|
.gart_set_page = &rs600_gart_set_page,
|
|
.ring_test = &r600_ring_test,
|
|
// .ring_ib_execute = &r600_ring_ib_execute,
|
|
// .irq_set = &r600_irq_set,
|
|
// .irq_process = &r600_irq_process,
|
|
.fence_ring_emit = &r600_fence_ring_emit,
|
|
// .cs_parse = &r600_cs_parse,
|
|
// .copy_blit = &r600_copy_blit,
|
|
// .copy_dma = &r600_copy_blit,
|
|
// .copy = &r600_copy_blit,
|
|
.get_engine_clock = &radeon_atom_get_engine_clock,
|
|
.set_engine_clock = &radeon_atom_set_engine_clock,
|
|
.get_memory_clock = &radeon_atom_get_memory_clock,
|
|
.set_memory_clock = &radeon_atom_set_memory_clock,
|
|
.get_pcie_lanes = &r600_get_pcie_lanes,
|
|
.set_pcie_lanes = &r600_set_pcie_lanes,
|
|
.set_clock_gating = NULL,
|
|
.set_surface_reg = r600_set_surface_reg,
|
|
.clear_surface_reg = r600_clear_surface_reg,
|
|
.bandwidth_update = &evergreen_bandwidth_update,
|
|
|
|
};
|
|
|
|
static struct radeon_asic sumo_asic = {
|
|
.init = &evergreen_init,
|
|
// .fini = &evergreen_fini,
|
|
// .suspend = &evergreen_suspend,
|
|
// .resume = &evergreen_resume,
|
|
.cp_commit = &r600_cp_commit,
|
|
.asic_reset = &evergreen_asic_reset,
|
|
.vga_set_state = &r600_vga_set_state,
|
|
.gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
|
|
.gart_set_page = &rs600_gart_set_page,
|
|
.ring_test = &r600_ring_test,
|
|
// .ring_ib_execute = &r600_ring_ib_execute,
|
|
// .irq_set = &r600_irq_set,
|
|
// .irq_process = &r600_irq_process,
|
|
.fence_ring_emit = &r600_fence_ring_emit,
|
|
// .cs_parse = &r600_cs_parse,
|
|
// .copy_blit = &r600_copy_blit,
|
|
// .copy_dma = &r600_copy_blit,
|
|
// .copy = &r600_copy_blit,
|
|
.get_engine_clock = &radeon_atom_get_engine_clock,
|
|
.set_engine_clock = &radeon_atom_set_engine_clock,
|
|
.get_memory_clock = NULL,
|
|
.set_memory_clock = NULL,
|
|
.get_pcie_lanes = NULL,
|
|
.set_pcie_lanes = NULL,
|
|
.set_clock_gating = NULL,
|
|
.set_surface_reg = r600_set_surface_reg,
|
|
.clear_surface_reg = r600_clear_surface_reg,
|
|
.bandwidth_update = &evergreen_bandwidth_update,
|
|
};
|
|
|
|
|
|
static struct radeon_asic btc_asic = {
|
|
.init = &evergreen_init,
|
|
// .fini = &evergreen_fini,
|
|
// .suspend = &evergreen_suspend,
|
|
// .resume = &evergreen_resume,
|
|
.cp_commit = &r600_cp_commit,
|
|
.asic_reset = &evergreen_asic_reset,
|
|
.vga_set_state = &r600_vga_set_state,
|
|
.gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
|
|
.gart_set_page = &rs600_gart_set_page,
|
|
.ring_test = &r600_ring_test,
|
|
// .ring_ib_execute = &r600_ring_ib_execute,
|
|
// .irq_set = &r600_irq_set,
|
|
// .irq_process = &r600_irq_process,
|
|
.fence_ring_emit = &r600_fence_ring_emit,
|
|
// .cs_parse = &r600_cs_parse,
|
|
// .copy_blit = &r600_copy_blit,
|
|
// .copy_dma = &r600_copy_blit,
|
|
// .copy = &r600_copy_blit,
|
|
.get_engine_clock = &radeon_atom_get_engine_clock,
|
|
.set_engine_clock = &radeon_atom_set_engine_clock,
|
|
.get_memory_clock = &radeon_atom_get_memory_clock,
|
|
.set_memory_clock = &radeon_atom_set_memory_clock,
|
|
.get_pcie_lanes = NULL,
|
|
.set_pcie_lanes = NULL,
|
|
.set_clock_gating = NULL,
|
|
.set_surface_reg = r600_set_surface_reg,
|
|
.clear_surface_reg = r600_clear_surface_reg,
|
|
.bandwidth_update = &evergreen_bandwidth_update,
|
|
.hpd_init = &evergreen_hpd_init,
|
|
.hpd_sense = &evergreen_hpd_sense,
|
|
};
|
|
|
|
static struct radeon_asic cayman_asic = {
|
|
.init = &cayman_init,
|
|
// .fini = &evergreen_fini,
|
|
// .suspend = &evergreen_suspend,
|
|
// .resume = &evergreen_resume,
|
|
.cp_commit = &r600_cp_commit,
|
|
.asic_reset = &cayman_asic_reset,
|
|
.vga_set_state = &r600_vga_set_state,
|
|
.gart_tlb_flush = &cayman_pcie_gart_tlb_flush,
|
|
.gart_set_page = &rs600_gart_set_page,
|
|
.ring_test = &r600_ring_test,
|
|
// .ring_ib_execute = &r600_ring_ib_execute,
|
|
// .irq_set = &r600_irq_set,
|
|
// .irq_process = &r600_irq_process,
|
|
.fence_ring_emit = &r600_fence_ring_emit,
|
|
// .cs_parse = &r600_cs_parse,
|
|
// .copy_blit = &r600_copy_blit,
|
|
// .copy_dma = &r600_copy_blit,
|
|
// .copy = &r600_copy_blit,
|
|
.get_engine_clock = &radeon_atom_get_engine_clock,
|
|
.set_engine_clock = &radeon_atom_set_engine_clock,
|
|
.get_memory_clock = &radeon_atom_get_memory_clock,
|
|
.set_memory_clock = &radeon_atom_set_memory_clock,
|
|
.get_pcie_lanes = NULL,
|
|
.set_pcie_lanes = NULL,
|
|
.set_clock_gating = NULL,
|
|
.set_surface_reg = r600_set_surface_reg,
|
|
.clear_surface_reg = r600_clear_surface_reg,
|
|
.bandwidth_update = &evergreen_bandwidth_update,
|
|
};
|
|
|
|
int radeon_asic_init(struct radeon_device *rdev)
|
|
{
|
|
radeon_register_accessor_init(rdev);
|
|
|
|
/* set the number of crtcs */
|
|
if (rdev->flags & RADEON_SINGLE_CRTC)
|
|
rdev->num_crtc = 1;
|
|
else
|
|
rdev->num_crtc = 2;
|
|
|
|
switch (rdev->family) {
|
|
case CHIP_R100:
|
|
case CHIP_RV100:
|
|
case CHIP_RS100:
|
|
case CHIP_RV200:
|
|
case CHIP_RS200:
|
|
rdev->asic = &r100_asic;
|
|
break;
|
|
case CHIP_R200:
|
|
case CHIP_RV250:
|
|
case CHIP_RS300:
|
|
case CHIP_RV280:
|
|
rdev->asic = &r200_asic;
|
|
break;
|
|
case CHIP_R300:
|
|
case CHIP_R350:
|
|
case CHIP_RV350:
|
|
case CHIP_RV380:
|
|
if (rdev->flags & RADEON_IS_PCIE)
|
|
rdev->asic = &r300_asic_pcie;
|
|
else
|
|
rdev->asic = &r300_asic;
|
|
break;
|
|
case CHIP_R420:
|
|
case CHIP_R423:
|
|
case CHIP_RV410:
|
|
rdev->asic = &r420_asic;
|
|
/* handle macs */
|
|
if (rdev->bios == NULL) {
|
|
rdev->asic->get_engine_clock = &radeon_legacy_get_engine_clock;
|
|
rdev->asic->set_engine_clock = &radeon_legacy_set_engine_clock;
|
|
rdev->asic->get_memory_clock = &radeon_legacy_get_memory_clock;
|
|
rdev->asic->set_memory_clock = NULL;
|
|
}
|
|
break;
|
|
case CHIP_RS400:
|
|
case CHIP_RS480:
|
|
rdev->asic = &rs400_asic;
|
|
break;
|
|
case CHIP_RS600:
|
|
rdev->asic = &rs600_asic;
|
|
break;
|
|
case CHIP_RS690:
|
|
case CHIP_RS740:
|
|
rdev->asic = &rs690_asic;
|
|
break;
|
|
case CHIP_RV515:
|
|
rdev->asic = &rv515_asic;
|
|
break;
|
|
case CHIP_R520:
|
|
case CHIP_RV530:
|
|
case CHIP_RV560:
|
|
case CHIP_RV570:
|
|
case CHIP_R580:
|
|
rdev->asic = &r520_asic;
|
|
break;
|
|
case CHIP_R600:
|
|
case CHIP_RV610:
|
|
case CHIP_RV630:
|
|
case CHIP_RV620:
|
|
case CHIP_RV635:
|
|
case CHIP_RV670:
|
|
rdev->asic = &r600_asic;
|
|
break;
|
|
case CHIP_RS780:
|
|
case CHIP_RS880:
|
|
rdev->asic = &rs780_asic;
|
|
break;
|
|
case CHIP_RV770:
|
|
case CHIP_RV730:
|
|
case CHIP_RV710:
|
|
case CHIP_RV740:
|
|
rdev->asic = &rv770_asic;
|
|
break;
|
|
case CHIP_CEDAR:
|
|
case CHIP_REDWOOD:
|
|
case CHIP_JUNIPER:
|
|
case CHIP_CYPRESS:
|
|
case CHIP_HEMLOCK:
|
|
/* set num crtcs */
|
|
if (rdev->family == CHIP_CEDAR)
|
|
rdev->num_crtc = 4;
|
|
else
|
|
rdev->num_crtc = 6;
|
|
rdev->asic = &evergreen_asic;
|
|
break;
|
|
case CHIP_PALM:
|
|
case CHIP_SUMO:
|
|
case CHIP_SUMO2:
|
|
rdev->asic = &sumo_asic;
|
|
break;
|
|
case CHIP_BARTS:
|
|
case CHIP_TURKS:
|
|
case CHIP_CAICOS:
|
|
/* set num crtcs */
|
|
if (rdev->family == CHIP_CAICOS)
|
|
rdev->num_crtc = 4;
|
|
else
|
|
rdev->num_crtc = 6;
|
|
rdev->asic = &btc_asic;
|
|
break;
|
|
case CHIP_CAYMAN:
|
|
rdev->asic = &cayman_asic;
|
|
/* set num crtcs */
|
|
rdev->num_crtc = 6;
|
|
break;
|
|
default:
|
|
/* FIXME: not supported yet */
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (rdev->flags & RADEON_IS_IGP) {
|
|
rdev->asic->get_memory_clock = NULL;
|
|
rdev->asic->set_memory_clock = NULL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|