149 lines
4.8 KiB
C
149 lines
4.8 KiB
C
/*
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* Copyright © 2008 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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*
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*/
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#include "drmP.h"
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#include "drm.h"
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//#include "i915_drm.h"
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#include "i915_drv.h"
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//#include "i915_trace.h"
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#include "intel_drv.h"
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//#include <linux/shmem_fs.h>
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//#include <linux/slab.h>
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//#include <linux/swap.h>
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#include <linux/pci.h>
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#define I915_EXEC_CONSTANTS_MASK (3<<6)
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#define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */
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#define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6)
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#define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */
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/**
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* i915_gem_clear_fence_reg - clear out fence register info
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* @obj: object to clear
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*
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* Zeroes out the fence register itself and clears out the associated
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* data structures in dev_priv and obj.
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*/
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static void
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i915_gem_clear_fence_reg(struct drm_device *dev,
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struct drm_i915_fence_reg *reg)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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uint32_t fence_reg = reg - dev_priv->fence_regs;
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switch (INTEL_INFO(dev)->gen) {
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case 7:
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case 6:
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I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0);
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break;
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case 5:
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case 4:
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I915_WRITE64(FENCE_REG_965_0 + fence_reg*8, 0);
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break;
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case 3:
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if (fence_reg >= 8)
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fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
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else
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case 2:
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fence_reg = FENCE_REG_830_0 + fence_reg * 4;
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I915_WRITE(fence_reg, 0);
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break;
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}
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list_del_init(®->lru_list);
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reg->obj = NULL;
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reg->setup_seqno = 0;
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}
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static void
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init_ring_lists(struct intel_ring_buffer *ring)
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{
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INIT_LIST_HEAD(&ring->active_list);
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INIT_LIST_HEAD(&ring->request_list);
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INIT_LIST_HEAD(&ring->gpu_write_list);
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}
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void
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i915_gem_load(struct drm_device *dev)
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{
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int i;
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drm_i915_private_t *dev_priv = dev->dev_private;
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INIT_LIST_HEAD(&dev_priv->mm.active_list);
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INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
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INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
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INIT_LIST_HEAD(&dev_priv->mm.pinned_list);
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INIT_LIST_HEAD(&dev_priv->mm.fence_list);
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INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
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INIT_LIST_HEAD(&dev_priv->mm.gtt_list);
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for (i = 0; i < I915_NUM_RINGS; i++)
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init_ring_lists(&dev_priv->ring[i]);
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for (i = 0; i < 16; i++)
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INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
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// INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
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// i915_gem_retire_work_handler);
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// init_completion(&dev_priv->error_completion);
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/* On GEN3 we really need to make sure the ARB C3 LP bit is set */
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if (IS_GEN3(dev)) {
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u32 tmp = I915_READ(MI_ARB_STATE);
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if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
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/* arb state is a masked write, so set bit + bit in mask */
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tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
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I915_WRITE(MI_ARB_STATE, tmp);
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}
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}
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dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
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if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
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dev_priv->num_fence_regs = 16;
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else
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dev_priv->num_fence_regs = 8;
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/* Initialize fence registers to zero */
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for (i = 0; i < dev_priv->num_fence_regs; i++) {
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i915_gem_clear_fence_reg(dev, &dev_priv->fence_regs[i]);
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}
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i915_gem_detect_bit_6_swizzle(dev);
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// init_waitqueue_head(&dev_priv->pending_flip_queue);
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dev_priv->mm.interruptible = true;
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// dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
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// dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
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// register_shrinker(&dev_priv->mm.inactive_shrinker);
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}
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