785 lines
24 KiB
C
785 lines
24 KiB
C
#include "drmP.h"
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#include "drm.h"
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#include "radeon_drm.h"
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#include "radeon.h"
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#include "r600d.h"
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#define DI_PT_RECTLIST 0x11
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#define DI_INDEX_SIZE_16_BIT 0x0
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#define DI_SRC_SEL_AUTO_INDEX 0x2
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#define FMT_8 0x1
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#define FMT_5_6_5 0x8
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#define FMT_8_8_8_8 0x1a
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#define COLOR_8 0x1
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#define COLOR_5_6_5 0x8
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#define COLOR_8_8_8_8 0x1a
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//#define CP_PACKET2 0x80000000
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//#define PACKET2_PAD_SHIFT 0
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//#define PACKET2_PAD_MASK (0x3fffffff << 0)
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//#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
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extern const u32 r7xx_default_state[];
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extern const u32 r6xx_default_state[];
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extern const u32 r6xx_default_size, r7xx_default_size;
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extern const u32 R600_video_ps[];
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extern const u32 R600_video_vs[];
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extern const u32 r600_video_ps_size;
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extern const u32 r600_video_vs_size;
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extern struct radeon_device *main_device;
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int r600_video_init(struct radeon_device *rdev)
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{
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u32 obj_size;
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int i, r, dwords;
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void *ptr;
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u32 packet2s[16];
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int num_packet2s = 0;
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/* pin copy shader into vram if already initialized */
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if (rdev->r600_video.shader_obj)
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goto done;
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mutex_init(&rdev->r600_video.mutex);
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rdev->r600_video.state_offset = 0;
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if (rdev->family >= CHIP_RV770)
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rdev->r600_video.state_len = r7xx_default_size;
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else
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rdev->r600_video.state_len = r6xx_default_size;
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dwords = rdev->r600_video.state_len;
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while (dwords & 0xf) {
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packet2s[num_packet2s++] = cpu_to_le32(PACKET2(0));
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dwords++;
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}
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obj_size = dwords * 4;
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obj_size = ALIGN(obj_size, 256);
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rdev->r600_video.vs_offset = obj_size;
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obj_size += r600_video_vs_size * 4;
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obj_size = ALIGN(obj_size, 256);
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rdev->r600_video.ps_offset = obj_size;
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obj_size += r600_video_ps_size * 4;
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obj_size = ALIGN(obj_size, 256);
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r = radeon_bo_create(rdev, obj_size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
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&rdev->r600_video.shader_obj);
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if (r) {
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DRM_ERROR("r600 failed to allocate video shader\n");
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return r;
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}
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DRM_DEBUG("r6xx video blit allocated bo %08x vs %08x ps %08x\n",
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obj_size,
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rdev->r600_video.vs_offset, rdev->r600_video.ps_offset);
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r = radeon_bo_reserve(rdev->r600_video.shader_obj, false);
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if (unlikely(r != 0))
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return r;
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r = radeon_bo_kmap(rdev->r600_video.shader_obj, &ptr);
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if (r) {
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DRM_ERROR("failed to map blit object %d\n", r);
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return r;
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}
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if (rdev->family >= CHIP_RV770)
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memcpy(ptr + rdev->r600_video.state_offset,
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r7xx_default_state, rdev->r600_video.state_len * 4);
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else
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memcpy(ptr + rdev->r600_video.state_offset,
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r6xx_default_state, rdev->r600_video.state_len * 4);
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if (num_packet2s)
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memcpy(ptr + rdev->r600_video.state_offset + (rdev->r600_video.state_len * 4),
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packet2s, num_packet2s * 4);
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for (i = 0; i < r600_video_vs_size; i++)
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*(u32 *)((unsigned long)ptr + rdev->r600_video.vs_offset + i * 4) = cpu_to_le32(R600_video_vs[i]);
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for (i = 0; i < r600_video_ps_size; i++)
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*(u32 *)((unsigned long)ptr + rdev->r600_video.ps_offset + i * 4) = cpu_to_le32(R600_video_ps[i]);
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radeon_bo_kunmap(rdev->r600_video.shader_obj);
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radeon_bo_unreserve(rdev->r600_video.shader_obj);
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done:
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r = radeon_bo_reserve(rdev->r600_video.shader_obj, false);
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if (unlikely(r != 0))
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return r;
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r = radeon_bo_pin(rdev->r600_video.shader_obj, RADEON_GEM_DOMAIN_VRAM,
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&rdev->r600_video.shader_gpu_addr);
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radeon_bo_unreserve(rdev->r600_video.shader_obj);
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if (r) {
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dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
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return r;
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}
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return 0;
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}
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/* emits 21 on rv770+, 23 on r600 */
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static void
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set_render_target(struct radeon_device *rdev, int format,
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int w, int h, u64 gpu_addr)
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{
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u32 cb_color_info;
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int pitch, slice;
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h = ALIGN(h, 8);
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if (h < 8)
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h = 8;
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cb_color_info = ((format << 2) | (1 << 27) | (1 << 8));
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pitch = (w / 8) - 1;
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slice = ((w * h) / 64) - 1;
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radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
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radeon_ring_write(rdev, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
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radeon_ring_write(rdev, gpu_addr >> 8);
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if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) {
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radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0));
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radeon_ring_write(rdev, 2 << 0);
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}
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radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
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radeon_ring_write(rdev, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
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radeon_ring_write(rdev, (pitch << 0) | (slice << 10));
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radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
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radeon_ring_write(rdev, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
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radeon_ring_write(rdev, 0);
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radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
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radeon_ring_write(rdev, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
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radeon_ring_write(rdev, cb_color_info);
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radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
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radeon_ring_write(rdev, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
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radeon_ring_write(rdev, 0);
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radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
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radeon_ring_write(rdev, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
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radeon_ring_write(rdev, 0);
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radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
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radeon_ring_write(rdev, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
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radeon_ring_write(rdev, 0);
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}
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/* emits 5dw */
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static void
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cp_set_surface_sync(struct radeon_device *rdev,
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u32 sync_type, u32 size,
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u64 mc_addr)
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{
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u32 cp_coher_size;
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if (size == 0xffffffff)
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cp_coher_size = 0xffffffff;
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else
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cp_coher_size = ((size + 255) >> 8);
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radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3));
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radeon_ring_write(rdev, sync_type);
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radeon_ring_write(rdev, cp_coher_size);
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radeon_ring_write(rdev, mc_addr >> 8);
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radeon_ring_write(rdev, 10); /* poll interval */
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}
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/* emits 21dw + 1 surface sync = 26dw */
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static void
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set_shaders(struct radeon_device *rdev)
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{
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u64 gpu_addr;
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u32 sq_pgm_resources;
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/* setup shader regs */
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sq_pgm_resources = (1 << 0);
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/* VS */
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gpu_addr = rdev->r600_video.shader_gpu_addr + rdev->r600_video.vs_offset;
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radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
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radeon_ring_write(rdev, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
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radeon_ring_write(rdev, gpu_addr >> 8);
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radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
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radeon_ring_write(rdev, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
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radeon_ring_write(rdev, sq_pgm_resources);
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radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
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radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
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radeon_ring_write(rdev, 0);
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/* PS */
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gpu_addr = rdev->r600_video.shader_gpu_addr + rdev->r600_video.ps_offset;
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radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
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radeon_ring_write(rdev, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
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radeon_ring_write(rdev, gpu_addr >> 8);
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radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
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radeon_ring_write(rdev, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
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radeon_ring_write(rdev, sq_pgm_resources | (1 << 28));
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radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
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radeon_ring_write(rdev, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
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radeon_ring_write(rdev, 2);
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radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
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radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
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radeon_ring_write(rdev, 0);
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gpu_addr = rdev->r600_video.shader_gpu_addr + rdev->r600_video.vs_offset;
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cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);
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}
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/* emits 9 + 1 sync (5) = 14*/
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static void
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set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
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{
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u32 sq_vtx_constant_word2;
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sq_vtx_constant_word2 = ((upper_32_bits(gpu_addr) & 0xff) | (16 << 8));
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#ifdef __BIG_ENDIAN
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sq_vtx_constant_word2 |= (2 << 30);
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#endif
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radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7));
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radeon_ring_write(rdev, 0x460);
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radeon_ring_write(rdev, gpu_addr & 0xffffffff);
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radeon_ring_write(rdev, 48 - 1);
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radeon_ring_write(rdev, sq_vtx_constant_word2);
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radeon_ring_write(rdev, 1 << 0);
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radeon_ring_write(rdev, 0);
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radeon_ring_write(rdev, 0);
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radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30);
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if ((rdev->family == CHIP_RV610) ||
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(rdev->family == CHIP_RV620) ||
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(rdev->family == CHIP_RS780) ||
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(rdev->family == CHIP_RS880) ||
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(rdev->family == CHIP_RV710))
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cp_set_surface_sync(rdev,
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PACKET3_TC_ACTION_ENA, 48, gpu_addr);
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else
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cp_set_surface_sync(rdev,
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PACKET3_VC_ACTION_ENA, 48, gpu_addr);
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}
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/* emits 9 */
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static void
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set_tex_resource(struct radeon_device *rdev,
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int format, int w, int h, int pitch,
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u64 gpu_addr)
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{
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uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4;
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if (h < 1)
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h = 1;
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sq_tex_resource_word0 = (1 << 0) | (1 << 3);
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sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 8) |
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((w - 1) << 19));
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sq_tex_resource_word1 = (format << 26);
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sq_tex_resource_word1 |= ((h - 1) << 0);
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sq_tex_resource_word4 = ((1 << 14) |
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(0 << 16) |
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(1 << 19) |
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(2 << 22) |
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(3 << 25));
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radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7));
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radeon_ring_write(rdev, 0);
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radeon_ring_write(rdev, sq_tex_resource_word0);
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radeon_ring_write(rdev, sq_tex_resource_word1);
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radeon_ring_write(rdev, gpu_addr >> 8);
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radeon_ring_write(rdev, gpu_addr >> 8);
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radeon_ring_write(rdev, sq_tex_resource_word4);
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radeon_ring_write(rdev, 0);
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radeon_ring_write(rdev, SQ_TEX_VTX_VALID_TEXTURE << 30);
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}
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/* emits 12 */
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static void
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set_scissors(struct radeon_device *rdev, int x1, int y1,
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int x2, int y2)
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{
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radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
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radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
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radeon_ring_write(rdev, (x1 << 0) | (y1 << 16));
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radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
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radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
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radeon_ring_write(rdev, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
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radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31));
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radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
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radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
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radeon_ring_write(rdev, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
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radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31));
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radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
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}
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/* emits 10 */
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static void
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draw_auto(struct radeon_device *rdev)
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{
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radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
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radeon_ring_write(rdev, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
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radeon_ring_write(rdev, DI_PT_RECTLIST);
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radeon_ring_write(rdev, PACKET3(PACKET3_INDEX_TYPE, 0));
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radeon_ring_write(rdev, DI_INDEX_SIZE_16_BIT);
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radeon_ring_write(rdev, PACKET3(PACKET3_NUM_INSTANCES, 0));
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radeon_ring_write(rdev, 1);
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radeon_ring_write(rdev, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));
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radeon_ring_write(rdev, 3);
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radeon_ring_write(rdev, DI_SRC_SEL_AUTO_INDEX);
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}
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/* emits 14 */
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static void
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set_default_state(struct radeon_device *rdev)
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{
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u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2;
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u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2;
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int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs;
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int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;
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int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
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u64 gpu_addr;
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int dwords;
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switch (rdev->family) {
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case CHIP_R600:
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num_ps_gprs = 192;
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num_vs_gprs = 56;
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num_temp_gprs = 4;
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num_gs_gprs = 0;
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num_es_gprs = 0;
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num_ps_threads = 136;
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num_vs_threads = 48;
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num_gs_threads = 4;
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num_es_threads = 4;
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num_ps_stack_entries = 128;
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num_vs_stack_entries = 128;
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num_gs_stack_entries = 0;
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num_es_stack_entries = 0;
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break;
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case CHIP_RV630:
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case CHIP_RV635:
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num_ps_gprs = 84;
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num_vs_gprs = 36;
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num_temp_gprs = 4;
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num_gs_gprs = 0;
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num_es_gprs = 0;
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num_ps_threads = 144;
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num_vs_threads = 40;
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num_gs_threads = 4;
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num_es_threads = 4;
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num_ps_stack_entries = 40;
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num_vs_stack_entries = 40;
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num_gs_stack_entries = 32;
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num_es_stack_entries = 16;
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break;
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case CHIP_RV610:
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case CHIP_RV620:
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case CHIP_RS780:
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case CHIP_RS880:
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default:
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num_ps_gprs = 84;
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num_vs_gprs = 36;
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num_temp_gprs = 4;
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num_gs_gprs = 0;
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num_es_gprs = 0;
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num_ps_threads = 136;
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num_vs_threads = 48;
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num_gs_threads = 4;
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num_es_threads = 4;
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num_ps_stack_entries = 40;
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num_vs_stack_entries = 40;
|
|
num_gs_stack_entries = 32;
|
|
num_es_stack_entries = 16;
|
|
break;
|
|
case CHIP_RV670:
|
|
num_ps_gprs = 144;
|
|
num_vs_gprs = 40;
|
|
num_temp_gprs = 4;
|
|
num_gs_gprs = 0;
|
|
num_es_gprs = 0;
|
|
num_ps_threads = 136;
|
|
num_vs_threads = 48;
|
|
num_gs_threads = 4;
|
|
num_es_threads = 4;
|
|
num_ps_stack_entries = 40;
|
|
num_vs_stack_entries = 40;
|
|
num_gs_stack_entries = 32;
|
|
num_es_stack_entries = 16;
|
|
break;
|
|
case CHIP_RV770:
|
|
num_ps_gprs = 192;
|
|
num_vs_gprs = 56;
|
|
num_temp_gprs = 4;
|
|
num_gs_gprs = 0;
|
|
num_es_gprs = 0;
|
|
num_ps_threads = 188;
|
|
num_vs_threads = 60;
|
|
num_gs_threads = 0;
|
|
num_es_threads = 0;
|
|
num_ps_stack_entries = 256;
|
|
num_vs_stack_entries = 256;
|
|
num_gs_stack_entries = 0;
|
|
num_es_stack_entries = 0;
|
|
break;
|
|
case CHIP_RV730:
|
|
case CHIP_RV740:
|
|
num_ps_gprs = 84;
|
|
num_vs_gprs = 36;
|
|
num_temp_gprs = 4;
|
|
num_gs_gprs = 0;
|
|
num_es_gprs = 0;
|
|
num_ps_threads = 188;
|
|
num_vs_threads = 60;
|
|
num_gs_threads = 0;
|
|
num_es_threads = 0;
|
|
num_ps_stack_entries = 128;
|
|
num_vs_stack_entries = 128;
|
|
num_gs_stack_entries = 0;
|
|
num_es_stack_entries = 0;
|
|
break;
|
|
case CHIP_RV710:
|
|
num_ps_gprs = 192;
|
|
num_vs_gprs = 56;
|
|
num_temp_gprs = 4;
|
|
num_gs_gprs = 0;
|
|
num_es_gprs = 0;
|
|
num_ps_threads = 144;
|
|
num_vs_threads = 48;
|
|
num_gs_threads = 0;
|
|
num_es_threads = 0;
|
|
num_ps_stack_entries = 128;
|
|
num_vs_stack_entries = 128;
|
|
num_gs_stack_entries = 0;
|
|
num_es_stack_entries = 0;
|
|
break;
|
|
}
|
|
|
|
if ((rdev->family == CHIP_RV610) ||
|
|
(rdev->family == CHIP_RV620) ||
|
|
(rdev->family == CHIP_RS780) ||
|
|
(rdev->family == CHIP_RS880) ||
|
|
(rdev->family == CHIP_RV710))
|
|
sq_config = 0;
|
|
else
|
|
sq_config = VC_ENABLE;
|
|
|
|
sq_config |= (DX9_CONSTS |
|
|
ALU_INST_PREFER_VECTOR |
|
|
PS_PRIO(0) |
|
|
VS_PRIO(1) |
|
|
GS_PRIO(2) |
|
|
ES_PRIO(3));
|
|
|
|
sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) |
|
|
NUM_VS_GPRS(num_vs_gprs) |
|
|
NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
|
|
sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) |
|
|
NUM_ES_GPRS(num_es_gprs));
|
|
sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) |
|
|
NUM_VS_THREADS(num_vs_threads) |
|
|
NUM_GS_THREADS(num_gs_threads) |
|
|
NUM_ES_THREADS(num_es_threads));
|
|
sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
|
|
NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
|
|
sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
|
|
NUM_ES_STACK_ENTRIES(num_es_stack_entries));
|
|
|
|
/* emit an IB pointing at default state */
|
|
dwords = ALIGN(rdev->r600_video.state_len, 0x10);
|
|
gpu_addr = rdev->r600_video.shader_gpu_addr + rdev->r600_video.state_offset;
|
|
radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
|
|
radeon_ring_write(rdev, (gpu_addr & 0xFFFFFFFC));
|
|
radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF);
|
|
radeon_ring_write(rdev, dwords);
|
|
|
|
/* SQ config */
|
|
radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 6));
|
|
radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
|
|
radeon_ring_write(rdev, sq_config);
|
|
radeon_ring_write(rdev, sq_gpr_resource_mgmt_1);
|
|
radeon_ring_write(rdev, sq_gpr_resource_mgmt_2);
|
|
radeon_ring_write(rdev, sq_thread_resource_mgmt);
|
|
radeon_ring_write(rdev, sq_stack_resource_mgmt_1);
|
|
radeon_ring_write(rdev, sq_stack_resource_mgmt_2);
|
|
}
|
|
|
|
static inline uint32_t i2f(uint32_t input)
|
|
{
|
|
u32 result, i, exponent, fraction;
|
|
|
|
if ((input & 0x3fff) == 0)
|
|
result = 0; /* 0 is a special case */
|
|
else {
|
|
exponent = 140; /* exponent biased by 127; */
|
|
fraction = (input & 0x3fff) << 10; /* cheat and only
|
|
handle numbers below 2^^15 */
|
|
for (i = 0; i < 14; i++) {
|
|
if (fraction & 0x800000)
|
|
break;
|
|
else {
|
|
fraction = fraction << 1; /* keep
|
|
shifting left until top bit = 1 */
|
|
exponent = exponent - 1;
|
|
}
|
|
}
|
|
result = exponent << 23 | (fraction & 0x7fffff); /* mask
|
|
off top bit; assumed 1 */
|
|
}
|
|
return result;
|
|
}
|
|
|
|
static int r600_vb_ib_get(struct radeon_device *rdev)
|
|
{
|
|
int r;
|
|
r = radeon_ib_get(rdev, &rdev->r600_video.vb_ib);
|
|
if (r) {
|
|
DRM_ERROR("failed to get IB for vertex buffer\n");
|
|
return r;
|
|
}
|
|
|
|
rdev->r600_video.vb_total = 64*1024;
|
|
rdev->r600_video.vb_used = 0;
|
|
return 0;
|
|
}
|
|
|
|
static void r600_vb_ib_put(struct radeon_device *rdev)
|
|
{
|
|
radeon_fence_emit(rdev, rdev->r600_video.vb_ib->fence);
|
|
radeon_ib_free(rdev, &rdev->r600_video.vb_ib);
|
|
}
|
|
|
|
|
|
int r600_video_prepare_copy(struct radeon_device *rdev, int size_bytes)
|
|
{
|
|
int r;
|
|
int ring_size, line_size;
|
|
int max_size;
|
|
/* loops of emits 64 + fence emit possible */
|
|
int dwords_per_loop = 76, num_loops;
|
|
|
|
r = r600_vb_ib_get(rdev);
|
|
if (r)
|
|
return r;
|
|
|
|
/* set_render_target emits 2 extra dwords on rv6xx */
|
|
if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770)
|
|
dwords_per_loop += 2;
|
|
|
|
/* 8 bpp vs 32 bpp for xfer unit */
|
|
if (size_bytes & 3)
|
|
line_size = 8192;
|
|
else
|
|
line_size = 8192*4;
|
|
|
|
max_size = 8192 * line_size;
|
|
|
|
/* major loops cover the max size transfer */
|
|
num_loops = ((size_bytes + max_size) / max_size);
|
|
/* minor loops cover the extra non aligned bits */
|
|
num_loops += ((size_bytes % line_size) ? 1 : 0);
|
|
/* calculate number of loops correctly */
|
|
ring_size = num_loops * dwords_per_loop;
|
|
/* set default + shaders */
|
|
ring_size += 40; /* shaders + def state */
|
|
ring_size += 10; /* fence emit for VB IB */
|
|
ring_size += 5; /* done copy */
|
|
ring_size += 10; /* fence emit for done copy */
|
|
r = radeon_ring_lock(rdev, ring_size);
|
|
if (r)
|
|
return r;
|
|
|
|
set_default_state(rdev); /* 14 */
|
|
set_shaders(rdev); /* 26 */
|
|
return 0;
|
|
}
|
|
|
|
void r600_video_done_copy(struct radeon_device *rdev, struct radeon_fence *fence)
|
|
{
|
|
int r;
|
|
|
|
if (rdev->r600_video.vb_ib)
|
|
r600_vb_ib_put(rdev);
|
|
|
|
if (fence)
|
|
r = radeon_fence_emit(rdev, fence);
|
|
|
|
radeon_ring_unlock_commit(rdev);
|
|
}
|
|
|
|
void r600_kms_video_blit(struct radeon_device *rdev,
|
|
u64 src_gpu_addr, int dstx, int dsty, int w, int h, int pitch)
|
|
{
|
|
u64 vb_gpu_addr;
|
|
u32 *vb;
|
|
|
|
// DRM_DEBUG("emitting video copy\n");
|
|
vb = (u32 *)(rdev->r600_video.vb_ib->ptr + rdev->r600_video.vb_used);
|
|
|
|
if ((rdev->r600_video.vb_used + 48) > rdev->r600_video.vb_total) {
|
|
// WARN_ON(1);
|
|
}
|
|
|
|
vb[0] = i2f(dstx);
|
|
vb[1] = i2f(dsty);
|
|
vb[2] = 0;
|
|
vb[3] = 0;
|
|
|
|
vb[4] = i2f(dstx);
|
|
vb[5] = i2f(dsty+h);
|
|
vb[6] = 0;
|
|
vb[7] = i2f(h);
|
|
|
|
vb[8] = i2f(dstx + w);
|
|
vb[9] = i2f(dsty + h);
|
|
vb[10] = i2f(w);
|
|
vb[11] = i2f(h);
|
|
|
|
/* src 9 */
|
|
set_tex_resource(rdev, FMT_8_8_8_8,
|
|
w, h, pitch/4, src_gpu_addr);
|
|
/* 5 */
|
|
cp_set_surface_sync(rdev,
|
|
PACKET3_TC_ACTION_ENA, pitch * h, src_gpu_addr);
|
|
|
|
/* dst 23 */
|
|
set_render_target(rdev, COLOR_8_8_8_8,
|
|
1024, 768, rdev->mc.vram_start);
|
|
|
|
/* scissors 12 */
|
|
set_scissors(rdev, 0, 0, 1024, 768);
|
|
|
|
/* Vertex buffer setup 14 */
|
|
vb_gpu_addr = rdev->r600_video.vb_ib->gpu_addr + rdev->r600_video.vb_used;
|
|
set_vtx_resource(rdev, vb_gpu_addr);
|
|
|
|
/* draw 10 */
|
|
draw_auto(rdev);
|
|
|
|
/* 5 */
|
|
cp_set_surface_sync(rdev,
|
|
PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA,
|
|
1024*4*768, rdev->mc.vram_start);
|
|
|
|
/* 78 ring dwords per loop */
|
|
vb += 12;
|
|
rdev->r600_video.vb_used += 12 * 4;
|
|
|
|
}
|
|
|
|
|
|
|
|
int r600_video_blit(uint64_t src_offset, int x, int y,
|
|
int w, int h, int pitch)
|
|
{
|
|
struct radeon_device *rdev = main_device;
|
|
static struct radeon_fence *fence;
|
|
unsigned long irq_flags;
|
|
|
|
int r;
|
|
|
|
if(fence == NULL)
|
|
{
|
|
r = radeon_fence_create(rdev, &fence);
|
|
if (r) {
|
|
printf("%s epic fail", __FUNCTION__);
|
|
return r;
|
|
}
|
|
};
|
|
|
|
fence->evnt = CreateEvent(NULL, 0);
|
|
|
|
mutex_lock(&rdev->r600_video.mutex);
|
|
rdev->r600_video.vb_ib = NULL;
|
|
r = r600_video_prepare_copy(rdev, h*pitch);
|
|
if (r) {
|
|
// if (rdev->r600_blit.vb_ib)
|
|
// radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
|
|
mutex_unlock(&rdev->r600_video.mutex);
|
|
return r;
|
|
}
|
|
|
|
r600_kms_video_blit(rdev, src_offset,x,y,w,h,pitch);
|
|
r600_video_done_copy(rdev, fence);
|
|
mutex_unlock(&rdev->r600_video.mutex);
|
|
|
|
r = radeon_fence_wait(fence, false);
|
|
|
|
write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
|
|
list_del(&fence->list);
|
|
fence->emited = false;
|
|
fence->signaled = false;
|
|
write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
|
|
|
|
return r;
|
|
};
|
|
|
|
|
|
int r600_create_video(int w, int h, u32_t *outp)
|
|
{
|
|
int r;
|
|
struct radeon_device *rdev = main_device;
|
|
struct radeon_bo *sobj = NULL;
|
|
uint64_t saddr;
|
|
void *uaddr;
|
|
|
|
size_t size;
|
|
size_t pitch;
|
|
|
|
pitch = radeon_align_pitch(rdev, w, 32, false) * 4;
|
|
|
|
size = pitch * h;
|
|
r = radeon_bo_create(rdev, size, PAGE_SIZE, true,
|
|
RADEON_GEM_DOMAIN_GTT, &sobj);
|
|
if (r) {
|
|
goto fail;
|
|
}
|
|
r = radeon_bo_reserve(sobj, false);
|
|
if (unlikely(r != 0))
|
|
goto fail;
|
|
r = radeon_bo_pin(sobj, RADEON_GEM_DOMAIN_GTT, &saddr);
|
|
// radeon_bo_unreserve(sobj);
|
|
if (r) {
|
|
goto fail;
|
|
}
|
|
|
|
r = radeon_bo_user_map(sobj, &uaddr);
|
|
if (r) {
|
|
goto fail;
|
|
}
|
|
|
|
((uint64_t*)outp)[0] = saddr;
|
|
outp[2] = uaddr;
|
|
outp[3] = pitch;
|
|
|
|
// dbgprintf("Create video surface %x, mapped at %x pitch %d\n",
|
|
// (uint32_t)saddr, uaddr, pitch);
|
|
return 0;
|
|
|
|
fail:
|
|
return -1;
|
|
};
|
|
|
|
|
|
|
|
|
|
|