877 lines
26 KiB
C
877 lines
26 KiB
C
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#include <linux/kernel.h>
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#include <linux/mutex.h>
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#include <linux/mod_devicetable.h>
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#include <pci.h>
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#include <errno-base.h>
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#include <syscall.h>
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static LIST_HEAD(devices);
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static pci_dev_t* pci_scan_device(u32_t bus, int devfn);
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/* PCI control bits. Shares IORESOURCE_BITS with above PCI ROM. */
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#define IORESOURCE_PCI_FIXED (1<<4) /* Do not move resource */
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#define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
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/*
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* Translate the low bits of the PCI base
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* to the resource type
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*/
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static inline unsigned int pci_calc_resource_flags(unsigned int flags)
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{
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if (flags & PCI_BASE_ADDRESS_SPACE_IO)
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return IORESOURCE_IO;
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if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
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return IORESOURCE_MEM | IORESOURCE_PREFETCH;
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return IORESOURCE_MEM;
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}
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static u32_t pci_size(u32_t base, u32_t maxbase, u32_t mask)
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{
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u32_t size = mask & maxbase; /* Find the significant bits */
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if (!size)
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return 0;
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/* Get the lowest of them to find the decode size, and
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from that the extent. */
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size = (size & ~(size-1)) - 1;
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/* base == maxbase can be valid only if the BAR has
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already been programmed with all 1s. */
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if (base == maxbase && ((base | size) & mask) != mask)
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return 0;
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return size;
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}
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static u64_t pci_size64(u64_t base, u64_t maxbase, u64_t mask)
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{
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u64_t size = mask & maxbase; /* Find the significant bits */
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if (!size)
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return 0;
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/* Get the lowest of them to find the decode size, and
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from that the extent. */
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size = (size & ~(size-1)) - 1;
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/* base == maxbase can be valid only if the BAR has
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already been programmed with all 1s. */
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if (base == maxbase && ((base | size) & mask) != mask)
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return 0;
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return size;
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}
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static inline int is_64bit_memory(u32_t mask)
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{
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if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
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(PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64))
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return 1;
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return 0;
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}
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static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
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{
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u32_t pos, reg, next;
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u32_t l, sz;
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struct resource *res;
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for(pos=0; pos < howmany; pos = next)
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{
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u64_t l64;
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u64_t sz64;
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u32_t raw_sz;
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next = pos + 1;
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res = &dev->resource[pos];
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reg = PCI_BASE_ADDRESS_0 + (pos << 2);
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l = PciRead32(dev->bus, dev->devfn, reg);
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PciWrite32(dev->bus, dev->devfn, reg, ~0);
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sz = PciRead32(dev->bus, dev->devfn, reg);
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PciWrite32(dev->bus, dev->devfn, reg, l);
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if (!sz || sz == 0xffffffff)
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continue;
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if (l == 0xffffffff)
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l = 0;
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raw_sz = sz;
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if ((l & PCI_BASE_ADDRESS_SPACE) ==
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PCI_BASE_ADDRESS_SPACE_MEMORY)
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{
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sz = pci_size(l, sz, (u32_t)PCI_BASE_ADDRESS_MEM_MASK);
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/*
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* For 64bit prefetchable memory sz could be 0, if the
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* real size is bigger than 4G, so we need to check
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* szhi for that.
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*/
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if (!is_64bit_memory(l) && !sz)
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continue;
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res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
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res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
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}
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else {
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sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
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if (!sz)
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continue;
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res->start = l & PCI_BASE_ADDRESS_IO_MASK;
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res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
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}
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res->end = res->start + (unsigned long) sz;
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res->flags |= pci_calc_resource_flags(l);
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if (is_64bit_memory(l))
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{
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u32_t szhi, lhi;
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lhi = PciRead32(dev->bus, dev->devfn, reg+4);
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PciWrite32(dev->bus, dev->devfn, reg+4, ~0);
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szhi = PciRead32(dev->bus, dev->devfn, reg+4);
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PciWrite32(dev->bus, dev->devfn, reg+4, lhi);
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sz64 = ((u64_t)szhi << 32) | raw_sz;
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l64 = ((u64_t)lhi << 32) | l;
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sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK);
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next++;
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#if BITS_PER_LONG == 64
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if (!sz64) {
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res->start = 0;
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res->end = 0;
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res->flags = 0;
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continue;
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}
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res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK;
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res->end = res->start + sz64;
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#else
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if (sz64 > 0x100000000ULL) {
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printk(KERN_ERR "PCI: Unable to handle 64-bit "
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"BAR for device %s\n", pci_name(dev));
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res->start = 0;
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res->flags = 0;
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}
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else if (lhi)
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{
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/* 64-bit wide address, treat as disabled */
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PciWrite32(dev->bus, dev->devfn, reg,
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l & ~(u32_t)PCI_BASE_ADDRESS_MEM_MASK);
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PciWrite32(dev->bus, dev->devfn, reg+4, 0);
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res->start = 0;
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res->end = sz;
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}
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#endif
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}
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}
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if ( rom )
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{
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dev->rom_base_reg = rom;
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res = &dev->resource[PCI_ROM_RESOURCE];
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l = PciRead32(dev->bus, dev->devfn, rom);
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PciWrite32(dev->bus, dev->devfn, rom, ~PCI_ROM_ADDRESS_ENABLE);
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sz = PciRead32(dev->bus, dev->devfn, rom);
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PciWrite32(dev->bus, dev->devfn, rom, l);
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if (l == 0xffffffff)
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l = 0;
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if (sz && sz != 0xffffffff)
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{
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sz = pci_size(l, sz, (u32_t)PCI_ROM_ADDRESS_MASK);
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if (sz)
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{
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res->flags = (l & IORESOURCE_ROM_ENABLE) |
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IORESOURCE_MEM | IORESOURCE_PREFETCH |
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IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
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res->start = l & PCI_ROM_ADDRESS_MASK;
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res->end = res->start + (unsigned long) sz;
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}
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}
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}
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}
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static void pci_read_irq(struct pci_dev *dev)
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{
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u8_t irq;
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irq = PciRead8(dev->bus, dev->devfn, PCI_INTERRUPT_PIN);
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dev->pin = irq;
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if (irq)
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irq = PciRead8(dev->bus, dev->devfn, PCI_INTERRUPT_LINE);
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dev->irq = irq;
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};
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static int pci_setup_device(struct pci_dev *dev)
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{
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u32_t class;
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class = PciRead32(dev->bus, dev->devfn, PCI_CLASS_REVISION);
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dev->revision = class & 0xff;
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class >>= 8; /* upper 3 bytes */
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dev->class = class;
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/* "Unknown power state" */
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// dev->current_state = PCI_UNKNOWN;
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/* Early fixups, before probing the BARs */
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// pci_fixup_device(pci_fixup_early, dev);
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class = dev->class >> 8;
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switch (dev->hdr_type)
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{
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case PCI_HEADER_TYPE_NORMAL: /* standard header */
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if (class == PCI_CLASS_BRIDGE_PCI)
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goto bad;
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pci_read_irq(dev);
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pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
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dev->subsystem_vendor = PciRead16(dev->bus, dev->devfn,PCI_SUBSYSTEM_VENDOR_ID);
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dev->subsystem_device = PciRead16(dev->bus, dev->devfn, PCI_SUBSYSTEM_ID);
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/*
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* Do the ugly legacy mode stuff here rather than broken chip
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* quirk code. Legacy mode ATA controllers have fixed
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* addresses. These are not always echoed in BAR0-3, and
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* BAR0-3 in a few cases contain junk!
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*/
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if (class == PCI_CLASS_STORAGE_IDE)
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{
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u8_t progif;
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progif = PciRead8(dev->bus, dev->devfn,PCI_CLASS_PROG);
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if ((progif & 1) == 0)
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{
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dev->resource[0].start = 0x1F0;
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dev->resource[0].end = 0x1F7;
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dev->resource[0].flags = LEGACY_IO_RESOURCE;
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dev->resource[1].start = 0x3F6;
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dev->resource[1].end = 0x3F6;
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dev->resource[1].flags = LEGACY_IO_RESOURCE;
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}
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if ((progif & 4) == 0)
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{
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dev->resource[2].start = 0x170;
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dev->resource[2].end = 0x177;
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dev->resource[2].flags = LEGACY_IO_RESOURCE;
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dev->resource[3].start = 0x376;
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dev->resource[3].end = 0x376;
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dev->resource[3].flags = LEGACY_IO_RESOURCE;
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};
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}
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break;
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case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
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if (class != PCI_CLASS_BRIDGE_PCI)
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goto bad;
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/* The PCI-to-PCI bridge spec requires that subtractive
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decoding (i.e. transparent) bridge must have programming
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interface code of 0x01. */
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pci_read_irq(dev);
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dev->transparent = ((dev->class & 0xff) == 1);
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pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
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break;
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case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
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if (class != PCI_CLASS_BRIDGE_CARDBUS)
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goto bad;
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pci_read_irq(dev);
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pci_read_bases(dev, 1, 0);
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dev->subsystem_vendor = PciRead16(dev->bus,
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dev->devfn,
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PCI_CB_SUBSYSTEM_VENDOR_ID);
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dev->subsystem_device = PciRead16(dev->bus,
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dev->devfn,
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PCI_CB_SUBSYSTEM_ID);
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break;
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default: /* unknown header */
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printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",
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pci_name(dev), dev->hdr_type);
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return -1;
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bad:
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printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
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pci_name(dev), class, dev->hdr_type);
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dev->class = PCI_CLASS_NOT_DEFINED;
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}
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/* We found a fine healthy device, go go go... */
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return 0;
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};
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static pci_dev_t* pci_scan_device(u32_t bus, int devfn)
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{
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pci_dev_t *dev;
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u32_t id;
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u8_t hdr;
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int timeout = 10;
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id = PciRead32(bus,devfn, PCI_VENDOR_ID);
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/* some broken boards return 0 or ~0 if a slot is empty: */
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if (id == 0xffffffff || id == 0x00000000 ||
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id == 0x0000ffff || id == 0xffff0000)
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return NULL;
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while (id == 0xffff0001)
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{
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delay(timeout/10);
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timeout *= 2;
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id = PciRead32(bus, devfn, PCI_VENDOR_ID);
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/* Card hasn't responded in 60 seconds? Must be stuck. */
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if (timeout > 60 * 100)
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{
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printk(KERN_WARNING "Device %04x:%02x:%02x.%d not "
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"responding\n", bus,PCI_SLOT(devfn),PCI_FUNC(devfn));
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return NULL;
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}
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};
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hdr = PciRead8(bus, devfn, PCI_HEADER_TYPE);
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dev = (pci_dev_t*)kzalloc(sizeof(pci_dev_t), 0);
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INIT_LIST_HEAD(&dev->link);
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if(unlikely(dev == NULL))
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return NULL;
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dev->pci_dev.bus = bus;
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dev->pci_dev.devfn = devfn;
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dev->pci_dev.hdr_type = hdr & 0x7f;
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dev->pci_dev.multifunction = !!(hdr & 0x80);
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dev->pci_dev.vendor = id & 0xffff;
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dev->pci_dev.device = (id >> 16) & 0xffff;
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pci_setup_device(&dev->pci_dev);
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return dev;
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};
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int pci_scan_slot(u32_t bus, int devfn)
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{
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int func, nr = 0;
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for (func = 0; func < 8; func++, devfn++)
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{
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pci_dev_t *dev;
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dev = pci_scan_device(bus, devfn);
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if( dev )
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{
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list_add(&dev->link, &devices);
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nr++;
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/*
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* If this is a single function device,
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* don't scan past the first function.
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*/
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if (!dev->pci_dev.multifunction)
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{
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if (func > 0) {
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dev->pci_dev.multifunction = 1;
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}
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else {
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break;
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}
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}
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}
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else {
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if (func == 0)
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break;
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}
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};
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return nr;
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};
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void pci_scan_bus(u32_t bus)
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{
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u32_t devfn;
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pci_dev_t *dev;
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for (devfn = 0; devfn < 0x100; devfn += 8)
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pci_scan_slot(bus, devfn);
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}
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int enum_pci_devices()
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{
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pci_dev_t *dev;
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u32_t last_bus;
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u32_t bus = 0 , devfn = 0;
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// list_initialize(&devices);
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last_bus = PciApi(1);
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if( unlikely(last_bus == -1))
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return -1;
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for(;bus <= last_bus; bus++)
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pci_scan_bus(bus);
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// for(dev = (dev_t*)devices.next;
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// &dev->link != &devices;
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// dev = (dev_t*)dev->link.next)
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// {
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// dbgprintf("PCI device %x:%x bus:%x devfn:%x\n",
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// dev->pci_dev.vendor,
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// dev->pci_dev.device,
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// dev->pci_dev.bus,
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// dev->pci_dev.devfn);
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//
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// }
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return 0;
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}
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#define PCI_FIND_CAP_TTL 48
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static int __pci_find_next_cap_ttl(unsigned int bus, unsigned int devfn,
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u8 pos, int cap, int *ttl)
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{
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u8 id;
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while ((*ttl)--) {
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pos = PciRead8(bus, devfn, pos);
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if (pos < 0x40)
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break;
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pos &= ~3;
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id = PciRead8(bus, devfn, pos + PCI_CAP_LIST_ID);
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if (id == 0xff)
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break;
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if (id == cap)
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return pos;
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pos += PCI_CAP_LIST_NEXT;
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}
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return 0;
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}
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static int __pci_find_next_cap(unsigned int bus, unsigned int devfn,
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u8 pos, int cap)
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{
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int ttl = PCI_FIND_CAP_TTL;
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return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
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}
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static int __pci_bus_find_cap_start(unsigned int bus,
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unsigned int devfn, u8 hdr_type)
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{
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u16 status;
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status = PciRead16(bus, devfn, PCI_STATUS);
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if (!(status & PCI_STATUS_CAP_LIST))
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return 0;
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switch (hdr_type) {
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case PCI_HEADER_TYPE_NORMAL:
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case PCI_HEADER_TYPE_BRIDGE:
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return PCI_CAPABILITY_LIST;
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case PCI_HEADER_TYPE_CARDBUS:
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return PCI_CB_CAPABILITY_LIST;
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default:
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return 0;
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}
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return 0;
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}
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int pci_find_capability(struct pci_dev *dev, int cap)
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{
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int pos;
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pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
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if (pos)
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pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
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return pos;
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}
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#if 0
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/**
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* pci_set_power_state - Set the power state of a PCI device
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* @dev: PCI device to be suspended
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* @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering
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*
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* Transition a device to a new power state, using the Power Management
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* Capabilities in the device's config space.
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*
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* RETURN VALUE:
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* -EINVAL if trying to enter a lower state than we're already in.
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* 0 if we're already in the requested state.
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* -EIO if device does not support PCI PM.
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* 0 if we can successfully change the power state.
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*/
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int
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pci_set_power_state(struct pci_dev *dev, pci_power_t state)
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{
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int pm, need_restore = 0;
|
|
u16 pmcsr, pmc;
|
|
|
|
/* bound the state we're entering */
|
|
if (state > PCI_D3hot)
|
|
state = PCI_D3hot;
|
|
|
|
/*
|
|
* If the device or the parent bridge can't support PCI PM, ignore
|
|
* the request if we're doing anything besides putting it into D0
|
|
* (which would only happen on boot).
|
|
*/
|
|
if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
|
|
return 0;
|
|
|
|
/* find PCI PM capability in list */
|
|
pm = pci_find_capability(dev, PCI_CAP_ID_PM);
|
|
|
|
/* abort if the device doesn't support PM capabilities */
|
|
if (!pm)
|
|
return -EIO;
|
|
|
|
/* Validate current state:
|
|
* Can enter D0 from any state, but if we can only go deeper
|
|
* to sleep if we're already in a low power state
|
|
*/
|
|
if (state != PCI_D0 && dev->current_state > state) {
|
|
printk(KERN_ERR "%s(): %s: state=%d, current state=%d\n",
|
|
__FUNCTION__, pci_name(dev), state, dev->current_state);
|
|
return -EINVAL;
|
|
} else if (dev->current_state == state)
|
|
return 0; /* we're already there */
|
|
|
|
|
|
pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc);
|
|
if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
|
|
printk(KERN_DEBUG
|
|
"PCI: %s has unsupported PM cap regs version (%u)\n",
|
|
pci_name(dev), pmc & PCI_PM_CAP_VER_MASK);
|
|
return -EIO;
|
|
}
|
|
|
|
/* check if this device supports the desired state */
|
|
if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1))
|
|
return -EIO;
|
|
else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2))
|
|
return -EIO;
|
|
|
|
pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
|
|
|
|
/* If we're (effectively) in D3, force entire word to 0.
|
|
* This doesn't affect PME_Status, disables PME_En, and
|
|
* sets PowerState to 0.
|
|
*/
|
|
switch (dev->current_state) {
|
|
case PCI_D0:
|
|
case PCI_D1:
|
|
case PCI_D2:
|
|
pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
|
|
pmcsr |= state;
|
|
break;
|
|
case PCI_UNKNOWN: /* Boot-up */
|
|
if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
|
|
&& !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
|
|
need_restore = 1;
|
|
/* Fall-through: force to D0 */
|
|
default:
|
|
pmcsr = 0;
|
|
break;
|
|
}
|
|
|
|
/* enter specified state */
|
|
pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr);
|
|
|
|
/* Mandatory power management transition delays */
|
|
/* see PCI PM 1.1 5.6.1 table 18 */
|
|
if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
|
|
msleep(pci_pm_d3_delay);
|
|
else if (state == PCI_D2 || dev->current_state == PCI_D2)
|
|
udelay(200);
|
|
|
|
/*
|
|
* Give firmware a chance to be called, such as ACPI _PRx, _PSx
|
|
* Firmware method after native method ?
|
|
*/
|
|
if (platform_pci_set_power_state)
|
|
platform_pci_set_power_state(dev, state);
|
|
|
|
dev->current_state = state;
|
|
|
|
/* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
|
|
* INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
|
|
* from D3hot to D0 _may_ perform an internal reset, thereby
|
|
* going to "D0 Uninitialized" rather than "D0 Initialized".
|
|
* For example, at least some versions of the 3c905B and the
|
|
* 3c556B exhibit this behaviour.
|
|
*
|
|
* At least some laptop BIOSen (e.g. the Thinkpad T21) leave
|
|
* devices in a D3hot state at boot. Consequently, we need to
|
|
* restore at least the BARs so that the device will be
|
|
* accessible to its driver.
|
|
*/
|
|
if (need_restore)
|
|
pci_restore_bars(dev);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
int pcibios_enable_resources(struct pci_dev *dev, int mask)
|
|
{
|
|
u16_t cmd, old_cmd;
|
|
int idx;
|
|
struct resource *r;
|
|
|
|
cmd = PciRead16(dev->bus, dev->devfn, PCI_COMMAND);
|
|
old_cmd = cmd;
|
|
for (idx = 0; idx < PCI_NUM_RESOURCES; idx++)
|
|
{
|
|
/* Only set up the requested stuff */
|
|
if (!(mask & (1 << idx)))
|
|
continue;
|
|
|
|
r = &dev->resource[idx];
|
|
if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
|
|
continue;
|
|
if ((idx == PCI_ROM_RESOURCE) &&
|
|
(!(r->flags & IORESOURCE_ROM_ENABLE)))
|
|
continue;
|
|
if (!r->start && r->end) {
|
|
printk(KERN_ERR "PCI: Device %s not available "
|
|
"because of resource %d collisions\n",
|
|
pci_name(dev), idx);
|
|
return -EINVAL;
|
|
}
|
|
if (r->flags & IORESOURCE_IO)
|
|
cmd |= PCI_COMMAND_IO;
|
|
if (r->flags & IORESOURCE_MEM)
|
|
cmd |= PCI_COMMAND_MEMORY;
|
|
}
|
|
if (cmd != old_cmd) {
|
|
printk("PCI: Enabling device %s (%04x -> %04x)\n",
|
|
pci_name(dev), old_cmd, cmd);
|
|
PciWrite16(dev->bus, dev->devfn, PCI_COMMAND, cmd);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
|
|
int pcibios_enable_device(struct pci_dev *dev, int mask)
|
|
{
|
|
int err;
|
|
|
|
if ((err = pcibios_enable_resources(dev, mask)) < 0)
|
|
return err;
|
|
|
|
// if (!dev->msi_enabled)
|
|
// return pcibios_enable_irq(dev);
|
|
return 0;
|
|
}
|
|
|
|
|
|
static int do_pci_enable_device(struct pci_dev *dev, int bars)
|
|
{
|
|
int err;
|
|
|
|
// err = pci_set_power_state(dev, PCI_D0);
|
|
// if (err < 0 && err != -EIO)
|
|
// return err;
|
|
err = pcibios_enable_device(dev, bars);
|
|
// if (err < 0)
|
|
// return err;
|
|
// pci_fixup_device(pci_fixup_enable, dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
static int __pci_enable_device_flags(struct pci_dev *dev,
|
|
resource_size_t flags)
|
|
{
|
|
int err;
|
|
int i, bars = 0;
|
|
|
|
// if (atomic_add_return(1, &dev->enable_cnt) > 1)
|
|
// return 0; /* already enabled */
|
|
|
|
for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
|
|
if (dev->resource[i].flags & flags)
|
|
bars |= (1 << i);
|
|
|
|
err = do_pci_enable_device(dev, bars);
|
|
// if (err < 0)
|
|
// atomic_dec(&dev->enable_cnt);
|
|
return err;
|
|
}
|
|
|
|
|
|
/**
|
|
* pci_enable_device - Initialize device before it's used by a driver.
|
|
* @dev: PCI device to be initialized
|
|
*
|
|
* Initialize device before it's used by a driver. Ask low-level code
|
|
* to enable I/O and memory. Wake up the device if it was suspended.
|
|
* Beware, this function can fail.
|
|
*
|
|
* Note we don't actually enable the device many times if we call
|
|
* this function repeatedly (we just increment the count).
|
|
*/
|
|
int pci_enable_device(struct pci_dev *dev)
|
|
{
|
|
return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
|
|
}
|
|
|
|
|
|
|
|
struct pci_device_id* find_pci_device(pci_dev_t* pdev, struct pci_device_id *idlist)
|
|
{
|
|
pci_dev_t *dev;
|
|
struct pci_device_id *ent;
|
|
|
|
for(dev = (pci_dev_t*)devices.next;
|
|
&dev->link != &devices;
|
|
dev = (pci_dev_t*)dev->link.next)
|
|
{
|
|
if( dev->pci_dev.vendor != idlist->vendor )
|
|
continue;
|
|
|
|
for(ent = idlist; ent->vendor != 0; ent++)
|
|
{
|
|
if(unlikely(ent->device == dev->pci_dev.device))
|
|
{
|
|
pdev->pci_dev = dev->pci_dev;
|
|
return ent;
|
|
}
|
|
};
|
|
}
|
|
|
|
return NULL;
|
|
};
|
|
|
|
|
|
|
|
/**
|
|
* pci_map_rom - map a PCI ROM to kernel space
|
|
* @pdev: pointer to pci device struct
|
|
* @size: pointer to receive size of pci window over ROM
|
|
* @return: kernel virtual pointer to image of ROM
|
|
*
|
|
* Map a PCI ROM into kernel space. If ROM is boot video ROM,
|
|
* the shadow BIOS copy will be returned instead of the
|
|
* actual ROM.
|
|
*/
|
|
|
|
#define legacyBIOSLocation 0xC0000
|
|
#define OS_BASE 0x80000000
|
|
|
|
void *pci_map_rom(struct pci_dev *pdev, size_t *size)
|
|
{
|
|
struct resource *res = &pdev->resource[PCI_ROM_RESOURCE];
|
|
u32_t start;
|
|
void *rom;
|
|
|
|
#if 0
|
|
/*
|
|
* IORESOURCE_ROM_SHADOW set on x86, x86_64 and IA64 supports legacy
|
|
* memory map if the VGA enable bit of the Bridge Control register is
|
|
* set for embedded VGA.
|
|
*/
|
|
if (res->flags & IORESOURCE_ROM_SHADOW) {
|
|
/* primary video rom always starts here */
|
|
start = (u32_t)0xC0000;
|
|
*size = 0x20000; /* cover C000:0 through E000:0 */
|
|
} else {
|
|
if (res->flags & (IORESOURCE_ROM_COPY | IORESOURCE_ROM_BIOS_COPY)) {
|
|
*size = pci_resource_len(pdev, PCI_ROM_RESOURCE);
|
|
return (void *)(unsigned long)
|
|
pci_resource_start(pdev, PCI_ROM_RESOURCE);
|
|
} else {
|
|
/* assign the ROM an address if it doesn't have one */
|
|
//if (res->parent == NULL &&
|
|
// pci_assign_resource(pdev,PCI_ROM_RESOURCE))
|
|
// return NULL;
|
|
start = pci_resource_start(pdev, PCI_ROM_RESOURCE);
|
|
*size = pci_resource_len(pdev, PCI_ROM_RESOURCE);
|
|
if (*size == 0)
|
|
return NULL;
|
|
|
|
/* Enable ROM space decodes */
|
|
if (pci_enable_rom(pdev))
|
|
return NULL;
|
|
}
|
|
}
|
|
|
|
rom = ioremap(start, *size);
|
|
if (!rom) {
|
|
/* restore enable if ioremap fails */
|
|
if (!(res->flags & (IORESOURCE_ROM_ENABLE |
|
|
IORESOURCE_ROM_SHADOW |
|
|
IORESOURCE_ROM_COPY)))
|
|
pci_disable_rom(pdev);
|
|
return NULL;
|
|
}
|
|
|
|
/*
|
|
* Try to find the true size of the ROM since sometimes the PCI window
|
|
* size is much larger than the actual size of the ROM.
|
|
* True size is important if the ROM is going to be copied.
|
|
*/
|
|
*size = pci_get_rom_size(rom, *size);
|
|
|
|
#endif
|
|
|
|
unsigned char tmp[32];
|
|
rom = NULL;
|
|
|
|
dbgprintf("Getting BIOS copy from legacy VBIOS location\n");
|
|
memcpy(tmp,(char*)(OS_BASE+legacyBIOSLocation), 32);
|
|
*size = tmp[2] * 512;
|
|
if (*size > 0x10000 )
|
|
{
|
|
*size = 0;
|
|
dbgprintf("Invalid BIOS length field\n");
|
|
}
|
|
else
|
|
rom = (void*)( OS_BASE+legacyBIOSLocation);
|
|
|
|
return rom;
|
|
}
|
|
|
|
|
|
int
|
|
pci_set_dma_mask(struct pci_dev *dev, u64 mask)
|
|
{
|
|
// if (!pci_dma_supported(dev, mask))
|
|
// return -EIO;
|
|
|
|
dev->dma_mask = mask;
|
|
|
|
return 0;
|
|
}
|
|
|
|
|