745 lines
20 KiB
C++
745 lines
20 KiB
C++
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#define UHCI_USBLEGSUP 0x00c0 /* legacy support */
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#define UHCI_USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */
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#define UHCI_USBLEGSUP_RWC 0x8f00 /* the R/WC bits */
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#define UHCI_USBLEGSUP_RO 0x5040 /* R/O and reserved bits */
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#define UHCI_USBCMD 0 /* command register */
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#define UHCI_USBINTR 4 /* interrupt register */
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#define UHCI_USBCMD_RUN 0x0001 /* RUN/STOP bit */
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#define UHCI_USBCMD_HCRESET 0x0002 /* Host Controller reset */
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#define UHCI_USBCMD_EGSM 0x0008 /* Global Suspend Mode */
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#define UHCI_USBCMD_CONFIGURE 0x0040 /* Config Flag */
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#define UHCI_USBINTR_RESUME 0x0002 /* Resume interrupt enable */
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#define USBCMD 0
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#define USBCMD_RS 0x0001 /* Run/Stop */
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#define USBCMD_HCRESET 0x0002 /* Host reset */
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#define USBCMD_GRESET 0x0004 /* Global reset */
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#define USBCMD_EGSM 0x0008 /* Global Suspend Mode */
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#define USBCMD_FGR 0x0010 /* Force Global Resume */
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#define USBCMD_SWDBG 0x0020 /* SW Debug mode */
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#define USBCMD_CF 0x0040 /* Config Flag (sw only) */
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#define USBCMD_MAXP 0x0080 /* Max Packet (0 = 32, 1 = 64) */
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#define USBSTS 2
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#define USBSTS_USBINT 0x0001 /* Interrupt due to IOC */
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#define USBSTS_ERROR 0x0002 /* Interrupt due to error */
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#define USBSTS_RD 0x0004 /* Resume Detect */
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#define USBSTS_HSE 0x0008 /* Host System Error: PCI problems */
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#define USBSTS_HCPE 0x0010 /* Host Controller Process Error:
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* the schedule is buggy */
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#define USBSTS_HCH 0x0020 /* HC Halted */
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#define USBFRNUM 6
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#define USBFLBASEADD 8
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#define USBSOF 12
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#define USBSOF_DEFAULT 64 /* Frame length is exactly 1 ms */
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#define USBPORTSC1 16
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#define USBPORTSC2 18
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#define UHCI_RH_MAXCHILD 7
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/*
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* Make sure the controller is completely inactive, unable to
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* generate interrupts or do DMA.
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*/
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void uhci_reset_hc(hc_t *hc)
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{
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/* Turn off PIRQ enable and SMI enable. (This also turns off the
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* BIOS's USB Legacy Support.) Turn off all the R/WC bits too.
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*/
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pciWriteWord(hc->PciTag, UHCI_USBLEGSUP, UHCI_USBLEGSUP_RWC);
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/* Reset the HC - this will force us to get a
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* new notification of any already connected
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* ports due to the virtual disconnect that it
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* implies.
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*/
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out16(hc->iobase + UHCI_USBCMD, UHCI_USBCMD_HCRESET);
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__asm__ __volatile__ ("":::"memory");
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delay(20/10);
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if (in16(hc->iobase + UHCI_USBCMD) & UHCI_USBCMD_HCRESET)
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dbgprintf("HCRESET not completed yet!\n");
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/* Just to be safe, disable interrupt requests and
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* make sure the controller is stopped.
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*/
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out16(hc->iobase + UHCI_USBINTR, 0);
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out16(hc->iobase + UHCI_USBCMD, 0);
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};
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int uhci_check_and_reset_hc(hc_t *hc)
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{
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u16_t legsup;
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unsigned int cmd, intr;
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/*
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* When restarting a suspended controller, we expect all the
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* settings to be the same as we left them:
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*
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* PIRQ and SMI disabled, no R/W bits set in USBLEGSUP;
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* Controller is stopped and configured with EGSM set;
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* No interrupts enabled except possibly Resume Detect.
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*
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* If any of these conditions are violated we do a complete reset.
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*/
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legsup = pciReadWord(hc->PciTag, UHCI_USBLEGSUP);
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if (legsup & ~(UHCI_USBLEGSUP_RO | UHCI_USBLEGSUP_RWC)) {
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dbgprintf("%s: legsup = 0x%04x\n",__FUNCTION__, legsup);
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goto reset_needed;
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}
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cmd = in16(hc->iobase + UHCI_USBCMD);
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if ( (cmd & UHCI_USBCMD_RUN) ||
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!(cmd & UHCI_USBCMD_CONFIGURE) ||
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!(cmd & UHCI_USBCMD_EGSM))
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{
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dbgprintf("%s: cmd = 0x%04x\n", __FUNCTION__, cmd);
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goto reset_needed;
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}
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intr = in16(hc->iobase + UHCI_USBINTR);
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if (intr & (~UHCI_USBINTR_RESUME))
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{
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dbgprintf("%s: intr = 0x%04x\n", __FUNCTION__, intr);
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goto reset_needed;
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}
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return 0;
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reset_needed:
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dbgprintf("Performing full reset\n");
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uhci_reset_hc(hc);
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return 1;
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}
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void hc_interrupt()
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{
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hc_t *hc;
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// printf("USB interrupt\n");
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hc = (hc_t*)hc_list.next;
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while( &hc->list != &hc_list)
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{
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hc_t *htmp;
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request_t *rq;
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u16_t status;
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htmp = hc;
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hc = (hc_t*)hc->list.next;
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status = in16(htmp->iobase + USBSTS);
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if (!(status & ~USBSTS_HCH)) /* shared interrupt, not mine */
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continue;
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out16(htmp->iobase + USBSTS, status); /* Clear it */
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rq = (request_t*)htmp->rq_list.next;
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while( &rq->list != &htmp->rq_list)
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{
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request_t *rtmp;
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td_t *td;
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rtmp = rq;
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rq = (request_t*)rq->list.next;
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td = rtmp->td_tail;
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if( td->status & TD_CTRL_ACTIVE)
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continue;
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list_del(&rtmp->list);
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RaiseEvent(rtmp->evh, 0, &rtmp->event);
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};
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}
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};
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bool init_hc(hc_t *hc)
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{
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int port;
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u32_t ifl;
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u16_t dev_status;
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td_t *td;
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int i;
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dbgprintf("\n\ninit uhci %x\n\n", hc->pciId);
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for(i=0;i<6;i++)
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{
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if(hc->ioBase[i]){
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hc->iobase = hc->ioBase[i];
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// dbgprintf("Io base_%d 0x%x\n", i,hc->ioBase[i]);
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break;
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};
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};
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/* The UHCI spec says devices must have 2 ports, and goes on to say
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* they may have more but gives no way to determine how many there
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* are. However according to the UHCI spec, Bit 7 of the port
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* status and control register is always set to 1. So we try to
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* use this to our advantage. Another common failure mode when
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* a nonexistent register is addressed is to return all ones, so
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* we test for that also.
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*/
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for (port = 0; port < 2; port++)
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{
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u32_t status;
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status = in16(hc->iobase + USBPORTSC1 + (port * 2));
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dbgprintf("port%d status %x\n", port, status);
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if (!(status & 0x0080) || status == 0xffff)
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break;
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}
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dbgprintf("detected %d ports\n\n", port);
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hc->numports = port;
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/* Kick BIOS off this hardware and reset if the controller
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* isn't already safely quiescent.
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*/
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uhci_check_and_reset_hc(hc);
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hc->frame_base = (u32_t*)KernelAlloc(4096);
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hc->frame_dma = GetPgAddr(hc->frame_base);
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hc->frame_number = 0;
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hc->td_pool = dma_pool_create("uhci_td", NULL,
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sizeof(td_t), 16, 0);
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if (!hc->td_pool)
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{
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dbgprintf("unable to create td dma_pool\n");
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goto err_create_td_pool;
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}
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for (i = 0; i < UHCI_NUM_SKELQH; i++)
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{
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qh_t *qh = alloc_qh();
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qh->qlink = 1;
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qh->qelem = 1;
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hc->qh[i] = qh;
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}
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for (i = SKEL_ISO + 1; i < SKEL_ASYNC; ++i)
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hc->qh[i]->qlink = hc->qh[SKEL_ASYNC]->dma | 2;
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for (i = 0; i < 1024; i++)
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{
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int qnum;
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qnum = 8 - (int) __bsf( i | 1024);
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if (qnum <= 1)
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qnum = 9;
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hc->frame_base[i] = hc->qh[qnum]->dma | 2;
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}
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mb();
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/* Set the frame length to the default: 1 ms exactly */
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out8(hc->iobase + USBSOF, USBSOF_DEFAULT);
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/* Store the frame list base address */
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out32(hc->iobase + USBFLBASEADD, hc->frame_dma);
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/* Set the current frame number */
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out16(hc->iobase + USBFRNUM, 0);
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out16(hc->iobase + USBSTS, 0x3F);
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out16(hc->iobase + UHCI_USBINTR, 4);
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AttachIntHandler(hc->irq_line, hc_interrupt, 0);
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pciWriteWord(hc->PciTag, UHCI_USBLEGSUP, UHCI_USBLEGSUP_DEFAULT);
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out16(hc->iobase + USBCMD, USBCMD_RS | USBCMD_CF |
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USBCMD_MAXP);
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for (port = 0; port < hc->numports; ++port)
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out16(hc->iobase + USBPORTSC1 + (port * 2), 0x200);
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for (port = 0; port < 2; ++port)
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{
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time_t timeout;
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delay(100/10);
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u32_t status = in16(hc->iobase + USBPORTSC1 + (port * 2));
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dbgprintf("port%d status %x\n", port, status);
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out16(hc->iobase + USBPORTSC1 + (port * 2), 0);
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timeout = 100/10;
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while(timeout--)
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{
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delay(10/10);
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status = in16(hc->iobase + USBPORTSC1 + (port * 2));
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if(status & 1)
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{
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udev_t *dev = kmalloc(sizeof(udev_t),0);
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out16(hc->iobase + USBPORTSC1 + (port * 2), 0x0E);
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delay(20/10);
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dbgprintf("enable port\n");
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status = in16(hc->iobase + USBPORTSC1 + (port * 2));
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dbgprintf("port%d status %x\n", port, status);
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INIT_LIST_HEAD(&dev->list);
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dev->host = hc;
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dev->port = port;
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dev->ep0_size = 8;
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dev->status = status;
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dbgprintf("port%d connected", port);
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if(status & 4)
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dbgprintf(" enabled");
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else
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dbgprintf(" disabled");
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if(status & 0x100){
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dev->speed = 0x4000000;
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dbgprintf(" low speed\n");
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} else {
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dev->speed = 0;
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dbgprintf(" full speed\n");
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};
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if(set_address(dev)) {
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list_add_tail(&dev->list, &newdev_list);
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hc->port_map |= 1<<port;
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}
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else {
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free(dev);
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out16(hc->iobase + USBPORTSC1 + (port * 2), 0);
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}
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break;
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};
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};
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};
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return true;
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err_create_td_pool:
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KernelFree(hc->frame_base);
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return false;
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};
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u16_t __attribute__((aligned(16)))
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req_descr[4] = {0x0680,0x0100,0x0000,8};
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/*
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IN(69) OUT(E1) SETUP(2D)
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SETUP(0) IN(1)
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SETUP(0) OUT(1) OUT(0) OUT(1)...IN(1)
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SETUP(0) IN(1) IN(0) IN(1)...OUT(0)
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*/
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bool set_address(udev_t *dev)
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{
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static udev_id = 0;
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static udev_addr = 0;
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static u16_t __attribute__((aligned(16)))
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req_addr[4] = {0x0500,0x0001,0x0000,0x0000};
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static u16_t __attribute__((aligned(16)))
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req_descr[4] = {0x0680,0x0100,0x0000,8};
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static u32_t data[2] __attribute__((aligned(16)));
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qh_t *qh;
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td_t *td0, *td1, *td2;
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u32_t dev_status;
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count_t timeout;
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int address;
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address = ++udev_addr;
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req_addr[1] = address;
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if( !ctrl_request(dev, &req_addr, DOUT, NULL, 0))
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return false;
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dev->addr = address;
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dev->id = (++udev_id << 8) | address;
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dbgprintf("set address %d\n", address);
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data[0] = 0;
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data[1] = 0;
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if( !ctrl_request(dev, &req_descr, DIN, data, 8))
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return false;
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dev_descr_t *descr = (dev_descr_t*)&data;
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dev->ep0_size = descr->bMaxPacketSize0;
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return true;
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}
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#define ALIGN16(x) (((x)+15)&~15)
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#define MakePtr( cast, ptr, addValue ) (cast)((addr_t)(ptr)+(addr_t)(addValue))
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request_t *alloc_rq_buffer(udev_t *dev, endp_t *enp, u32_t dir,
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size_t data_size)
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{
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size_t packet_size = dev->ep0_size;
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int dsize = data_size;
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size_t buf_size;
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addr_t buf_dma;
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addr_t td_dma;
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addr_t data_dma;
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request_t *rq;
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td_t *td, *td_prev;
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int td_count = 0;
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while(dsize > 0)
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{
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td_count++;
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dsize-= packet_size;
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};
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buf_size = ALIGN16(sizeof(request_t)) + ALIGN16(data_size) +
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td_count*sizeof(td_t);
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rq = (request_t*)hcd_buffer_alloc(buf_size, &buf_dma);
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memset(rq, 0, buf_size);
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data_dma = buf_dma + ALIGN16(sizeof(request_t));
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td_dma = data_dma + ALIGN16(data_size);
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INIT_LIST_HEAD(&rq->list);
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rq->data = MakePtr(addr_t, rq, ALIGN16(sizeof(request_t)));
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td = MakePtr(td_t*, rq->data, ALIGN16(data_size));
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rq->td_head = td;
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rq->size = data_size;
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rq->dev = dev;
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td_prev = NULL;
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dsize = data_size;
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while(dsize != 0)
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{
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if ( dsize < packet_size)
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{
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packet_size = dsize;
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};
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td->dma = td_dma;
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td->link = 1;
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if( td_prev )
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td_prev->link = td->dma | 4;
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td->status = TD_CTRL_ACTIVE | dev->speed;
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td->token = TOKEN(packet_size,enp->toggle,enp->address,
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dev->addr,dir);
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td->buffer = data_dma;
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td->bk = td_prev;
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td_prev = td;
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td++;
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td_dma+= sizeof(td_t);
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data_dma+= packet_size;
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dsize-= packet_size;
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enp->toggle ^= DATA1;
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};
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td_prev->status |= TD_CTRL_IOC;
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rq->td_tail = td_prev;
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rq->evh = CreateEvent(NULL, MANUAL_DESTROY);
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if(rq->evh.handle == 0)
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printf("%s: epic fail\n", __FUNCTION__);
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rq->event.code = 0xFF000001;
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rq->event.data[0] = (addr_t)rq;
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return rq;
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}
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bool ctrl_request(udev_t *dev, void *req, u32_t pid,
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void *data, size_t req_size)
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{
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size_t packet_size = dev->ep0_size;
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size_t size = req_size;
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u32_t toggle = DATA1;
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td_t *td0, *td, *td_prev;
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qh_t *qh;
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addr_t data_dma = 0;
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hc_t *hc = dev->host;
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addr_t td_dma = 0;
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bool retval;
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request_t *rq = (request_t*)kmalloc(sizeof(request_t),0);
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INIT_LIST_HEAD(&rq->list);
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rq->data = (addr_t)data;
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rq->size = req_size;
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rq->dev = dev;
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td0 = dma_pool_alloc(hc->td_pool, 0, &td_dma);
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td0->dma = td_dma;
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// dbgprintf("alloc td0 %x dma %x\n", td0, td_dma);
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td0->status = 0x00800000 | dev->speed;
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td0->token = TOKEN( 8, DATA0, 0, dev->addr, 0x2D);
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td0->buffer = DMA(req);
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td0->bk = NULL;
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if(data)
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data_dma = DMA(data);
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td_prev = td0;
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while(size > 0)
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{
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if ( size < packet_size)
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{
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packet_size = size;
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};
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|
td = dma_pool_alloc(hc->td_pool, 0, &td_dma);
|
|
td->dma = td_dma;
|
|
|
|
// dbgprintf("alloc td %x dma %x\n", td, td->dma);
|
|
|
|
td_prev->link = td->dma | 4;
|
|
td->status = TD_CTRL_ACTIVE | dev->speed;
|
|
td->token = TOKEN(packet_size, toggle, 0,dev->addr, pid);
|
|
td->buffer = data_dma;
|
|
td->bk = td_prev;
|
|
|
|
td_prev = td;
|
|
|
|
data_dma+= packet_size;
|
|
size-= packet_size;
|
|
toggle ^= DATA1;
|
|
}
|
|
|
|
td = dma_pool_alloc(hc->td_pool, 0, &td_dma);
|
|
td->dma = td_dma;
|
|
|
|
// dbgprintf("alloc td %x dma %x\n", td, td->dma);
|
|
|
|
td_prev->link = td->dma | 4;
|
|
|
|
pid = (pid == DIN) ? DOUT : DIN;
|
|
|
|
td->link = 1;
|
|
td->status = TD_CTRL_ACTIVE | TD_CTRL_IOC | dev->speed ;
|
|
td->token = (0x7FF<<21)|DATA1|(dev->addr<<8)|pid;
|
|
td->buffer = 0;
|
|
td->bk = td_prev;
|
|
|
|
rq->td_head = td0;
|
|
rq->td_tail = td;
|
|
|
|
rq->evh = CreateEvent(NULL, MANUAL_DESTROY);
|
|
|
|
if(rq->evh.handle == 0)
|
|
printf("%s: epic fail\n", __FUNCTION__);
|
|
|
|
rq->event.code = 0xFF000001;
|
|
rq->event.data[0] = (addr_t)rq;
|
|
|
|
u32_t efl = safe_cli();
|
|
|
|
list_add_tail(&rq->list, &dev->host->rq_list);
|
|
|
|
qh = dev->host->qh[SKEL_ASYNC];
|
|
|
|
qh->qelem = td0->dma;
|
|
|
|
mb();
|
|
|
|
safe_sti(efl);
|
|
|
|
WaitEvent(rq->evh.handle, rq->evh.euid);
|
|
|
|
dbgprintf("td0 status 0x%0x\n", td0->status);
|
|
dbgprintf("td status 0x%0x\n", td->status);
|
|
|
|
if( (td0->status & TD_ANY_ERROR) ||
|
|
(td_prev->status & TD_ANY_ERROR) ||
|
|
(td->status & TD_ANY_ERROR))
|
|
{
|
|
u32_t dev_status = in16(dev->host->iobase + USBSTS);
|
|
|
|
dbgprintf("\nframe %x, cmd %x status %x\n",
|
|
in16(dev->host->iobase + USBFRNUM),
|
|
in16(dev->host->iobase + USBCMD),
|
|
dev_status);
|
|
dbgprintf("td0 status %x\n",td0->status);
|
|
dbgprintf("td_prev status %x\n",td_prev->status);
|
|
dbgprintf("td status %x\n",td->status);
|
|
dbgprintf("qh %x \n", qh->qelem);
|
|
|
|
retval = false;
|
|
} else retval = true;
|
|
|
|
qh->qelem = 1;
|
|
|
|
mb();
|
|
|
|
do
|
|
{
|
|
td_prev = td->bk;
|
|
dma_pool_free(hc->td_pool, td, td->dma);
|
|
td = td_prev;
|
|
}while( td != NULL);
|
|
|
|
/*
|
|
delete event;
|
|
*/
|
|
kfree(rq);
|
|
|
|
return retval;
|
|
};
|
|
|
|
|
|
bool init_device(udev_t *dev)
|
|
{
|
|
static u16_t __attribute__((aligned(16)))
|
|
req_descr[4] = {0x0680,0x0100,0x0000,18};
|
|
|
|
static u16_t __attribute__((aligned(16)))
|
|
req_conf[4] = {0x0680,0x0200,0x0000,9};
|
|
|
|
static dev_descr_t __attribute__((aligned(16))) descr;
|
|
|
|
interface_descr_t *interface;
|
|
|
|
u32_t data[8];
|
|
|
|
u8_t *dptr;
|
|
conf_descr_t *conf;
|
|
|
|
dbgprintf("\ninit device %x, host %x, port %d\n\n",
|
|
dev->id, dev->host->pciId, dev->port);
|
|
|
|
if( !ctrl_request(dev, req_descr, DIN, &descr, 18))
|
|
{
|
|
dbgprintf("%s epic fail\n",__FUNCTION__);
|
|
return;
|
|
};
|
|
|
|
dev->dev_descr = descr;
|
|
|
|
dbgprintf("device descriptor:\n\n"
|
|
"bLength %d\n"
|
|
"bDescriptorType %d\n"
|
|
"bcdUSB %x\n"
|
|
"bDeviceClass %x\n"
|
|
"bDeviceSubClass %x\n"
|
|
"bDeviceProtocol %x\n"
|
|
"bMaxPacketSize0 %d\n"
|
|
"idVendor %x\n"
|
|
"idProduct %x\n"
|
|
"bcdDevice %x\n"
|
|
"iManufacturer %x\n"
|
|
"iProduct %x\n"
|
|
"iSerialNumber %x\n"
|
|
"bNumConfigurations %d\n\n",
|
|
descr.bLength, descr.bDescriptorType,
|
|
descr.bcdUSB, descr.bDeviceClass,
|
|
descr.bDeviceSubClass, descr.bDeviceProtocol,
|
|
descr.bMaxPacketSize0, descr.idVendor,
|
|
descr.idProduct, descr.bcdDevice,
|
|
descr.iManufacturer, descr.iProduct,
|
|
descr.iSerialNumber, descr.bNumConfigurations);
|
|
|
|
req_conf[3] = 8;
|
|
if( !ctrl_request(dev, req_conf, DIN, &data, 8))
|
|
return;
|
|
|
|
conf = (conf_descr_t*)&data;
|
|
|
|
size_t conf_size = conf->wTotalLength;
|
|
|
|
req_conf[3] = conf_size;
|
|
conf = malloc(conf_size);
|
|
|
|
if( !ctrl_request(dev, req_conf, DIN, conf, conf_size))
|
|
return;
|
|
|
|
dptr = (u8_t*)conf;
|
|
dptr+= conf->bLength;
|
|
|
|
dbgprintf("configuration descriptor\n\n"
|
|
"bLength %d\n"
|
|
"bDescriptorType %d\n"
|
|
"wTotalLength %d\n"
|
|
"bNumInterfaces %d\n"
|
|
"bConfigurationValue %x\n"
|
|
"iConfiguration %d\n"
|
|
"bmAttributes %x\n"
|
|
"bMaxPower %dmA\n\n",
|
|
conf->bLength,
|
|
conf->bDescriptorType,
|
|
conf->wTotalLength,
|
|
conf->bNumInterfaces,
|
|
conf->bConfigurationValue,
|
|
conf->iConfiguration,
|
|
conf->bmAttributes,
|
|
conf->bMaxPower*2);
|
|
|
|
interface = (interface_descr_t*)dptr;
|
|
|
|
switch(interface->bInterfaceClass)
|
|
{
|
|
case USB_CLASS_AUDIO:
|
|
dbgprintf( "audio device\n");
|
|
break;
|
|
case USB_CLASS_HID:
|
|
dev->conf = conf;
|
|
list_del(&dev->list);
|
|
return init_hid(dev);
|
|
|
|
case USB_CLASS_PRINTER:
|
|
dbgprintf("printer\n");
|
|
break;
|
|
case USB_CLASS_MASS_STORAGE:
|
|
dbgprintf("mass storage device\n");
|
|
break;
|
|
case USB_CLASS_HUB:
|
|
dbgprintf("hub device\n");
|
|
break;
|
|
default:
|
|
dbgprintf("unknown device\n");
|
|
};
|
|
};
|