431 lines
12 KiB
C
431 lines
12 KiB
C
/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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/* RS600 / Radeon X1250/X1270 integrated GPU
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*
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* This file gather function specific to RS600 which is the IGP of
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* the X1250/X1270 family supporting intel CPU (while RS690/RS740
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* is the X1250/X1270 supporting AMD CPU). The display engine are
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* the avivo one, bios is an atombios, 3D block are the one of the
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* R4XX family. The GART is different from the RS400 one and is very
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* close to the one of the R600 family (R600 likely being an evolution
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* of the RS600 GART block).
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*/
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#include "drmP.h"
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#include "radeon.h"
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#include "atom.h"
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#include "rs600d.h"
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#include "rs600_reg_safe.h"
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void rs600_gpu_init(struct radeon_device *rdev);
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int rs600_mc_wait_for_idle(struct radeon_device *rdev);
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/*
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* GART.
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*/
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void rs600_gart_tlb_flush(struct radeon_device *rdev)
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{
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uint32_t tmp;
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tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
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tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
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WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
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tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
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tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) & S_000100_INVALIDATE_L2_CACHE(1);
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WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
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tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
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tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
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WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
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tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
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}
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int rs600_gart_init(struct radeon_device *rdev)
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{
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int r;
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if (rdev->gart.table.vram.robj) {
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WARN(1, "RS600 GART already initialized.\n");
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return 0;
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}
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/* Initialize common gart structure */
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r = radeon_gart_init(rdev);
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if (r) {
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return r;
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}
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rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
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return radeon_gart_table_vram_alloc(rdev);
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}
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int rs600_gart_enable(struct radeon_device *rdev)
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{
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u32 tmp;
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int r, i;
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if (rdev->gart.table.vram.robj == NULL) {
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dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
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return -EINVAL;
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}
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r = radeon_gart_table_vram_pin(rdev);
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if (r)
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return r;
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/* Enable bus master */
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tmp = RREG32(R_00004C_BUS_CNTL) & C_00004C_BUS_MASTER_DIS;
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WREG32(R_00004C_BUS_CNTL, tmp);
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/* FIXME: setup default page */
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WREG32_MC(R_000100_MC_PT0_CNTL,
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(S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
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S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
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for (i = 0; i < 19; i++) {
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WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
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S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
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S_00016C_SYSTEM_ACCESS_MODE_MASK(
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V_00016C_SYSTEM_ACCESS_MODE_IN_SYS) |
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S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
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V_00016C_SYSTEM_APERTURE_UNMAPPED_DEFAULT_PAGE) |
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S_00016C_EFFECTIVE_L1_CACHE_SIZE(1) |
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S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |
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S_00016C_EFFECTIVE_L1_QUEUE_SIZE(1));
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}
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/* System context map to GART space */
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WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.gtt_start);
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WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.gtt_end);
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/* enable first context */
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WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
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WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
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WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,
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S_000102_ENABLE_PAGE_TABLE(1) |
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S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
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/* disable all other contexts */
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for (i = 1; i < 8; i++) {
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WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);
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}
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/* setup the page table */
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WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
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rdev->gart.table_addr);
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WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
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/* enable page tables */
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tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
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WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));
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tmp = RREG32_MC(R_000009_MC_CNTL1);
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WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)));
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rs600_gart_tlb_flush(rdev);
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rdev->gart.ready = true;
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return 0;
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}
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void rs600_gart_disable(struct radeon_device *rdev)
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{
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uint32_t tmp;
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/* FIXME: disable out of gart access */
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WREG32_MC(R_000100_MC_PT0_CNTL, 0);
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tmp = RREG32_MC(R_000009_MC_CNTL1);
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WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
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if (rdev->gart.table.vram.robj) {
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// radeon_object_kunmap(rdev->gart.table.vram.robj);
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// radeon_object_unpin(rdev->gart.table.vram.robj);
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}
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}
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void rs600_gart_fini(struct radeon_device *rdev)
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{
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rs600_gart_disable(rdev);
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radeon_gart_table_vram_free(rdev);
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radeon_gart_fini(rdev);
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}
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#define R600_PTE_VALID (1 << 0)
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#define R600_PTE_SYSTEM (1 << 1)
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#define R600_PTE_SNOOPED (1 << 2)
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#define R600_PTE_READABLE (1 << 5)
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#define R600_PTE_WRITEABLE (1 << 6)
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int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
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{
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void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
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if (i < 0 || i > rdev->gart.num_gpu_pages) {
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return -EINVAL;
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}
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addr = addr & 0xFFFFFFFFFFFFF000ULL;
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addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
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addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
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writeq(addr, ((void __iomem *)ptr) + (i * 8));
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return 0;
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}
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static inline uint32_t rs600_irq_ack(struct radeon_device *rdev, u32 *r500_disp_int)
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{
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uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
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uint32_t irq_mask = ~C_000044_SW_INT;
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if (G_000044_DISPLAY_INT_STAT(irqs)) {
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*r500_disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
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if (G_007EDC_LB_D1_VBLANK_INTERRUPT(*r500_disp_int)) {
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WREG32(R_006534_D1MODE_VBLANK_STATUS,
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S_006534_D1MODE_VBLANK_ACK(1));
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}
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if (G_007EDC_LB_D2_VBLANK_INTERRUPT(*r500_disp_int)) {
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WREG32(R_006D34_D2MODE_VBLANK_STATUS,
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S_006D34_D2MODE_VBLANK_ACK(1));
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}
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} else {
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*r500_disp_int = 0;
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}
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if (irqs) {
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WREG32(R_000044_GEN_INT_STATUS, irqs);
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}
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return irqs & irq_mask;
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}
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void rs600_irq_disable(struct radeon_device *rdev)
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{
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u32 tmp;
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WREG32(R_000040_GEN_INT_CNTL, 0);
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WREG32(R_006540_DxMODE_INT_MASK, 0);
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/* Wait and acknowledge irq */
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mdelay(1);
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rs600_irq_ack(rdev, &tmp);
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}
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u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
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{
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if (crtc == 0)
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return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);
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else
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return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);
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}
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int rs600_mc_wait_for_idle(struct radeon_device *rdev)
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{
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unsigned i;
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for (i = 0; i < rdev->usec_timeout; i++) {
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if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS)))
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return 0;
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udelay(1);
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}
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return -1;
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}
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void rs600_gpu_init(struct radeon_device *rdev)
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{
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/* FIXME: HDP same place on rs600 ? */
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r100_hdp_reset(rdev);
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/* FIXME: is this correct ? */
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r420_pipes_init(rdev);
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/* Wait for mc idle */
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if (rs600_mc_wait_for_idle(rdev))
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dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
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}
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void rs600_vram_info(struct radeon_device *rdev)
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{
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/* FIXME: to do or is these values sane ? */
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rdev->mc.vram_is_ddr = true;
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rdev->mc.vram_width = 128;
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}
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void rs600_bandwidth_update(struct radeon_device *rdev)
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{
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/* FIXME: implement, should this be like rs690 ? */
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}
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uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
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{
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WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
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S_000070_MC_IND_CITF_ARB0(1));
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return RREG32(R_000074_MC_IND_DATA);
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}
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void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
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{
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WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
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S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1));
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WREG32(R_000074_MC_IND_DATA, v);
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}
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void rs600_debugfs(struct radeon_device *rdev)
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{
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if (r100_debugfs_rbbm_init(rdev))
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DRM_ERROR("Failed to register debugfs file for RBBM !\n");
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}
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void rs600_set_safe_registers(struct radeon_device *rdev)
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{
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rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
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rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
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}
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static void rs600_mc_program(struct radeon_device *rdev)
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{
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struct rv515_mc_save save;
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/* Stops all mc clients */
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rv515_mc_stop(rdev, &save);
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/* Wait for mc idle */
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if (rs600_mc_wait_for_idle(rdev))
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dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
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/* FIXME: What does AGP means for such chipset ? */
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WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF);
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WREG32_MC(R_000006_AGP_BASE, 0);
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WREG32_MC(R_000007_AGP_BASE_2, 0);
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/* Program MC */
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WREG32_MC(R_000004_MC_FB_LOCATION,
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S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
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S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
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WREG32(R_000134_HDP_FB_LOCATION,
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S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
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rv515_mc_resume(rdev, &save);
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}
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static int rs600_startup(struct radeon_device *rdev)
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{
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int r;
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rs600_mc_program(rdev);
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/* Resume clock */
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rv515_clock_startup(rdev);
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/* Initialize GPU configuration (# pipes, ...) */
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rs600_gpu_init(rdev);
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/* Initialize GART (initialize after TTM so we can allocate
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* memory through TTM but finalize after TTM) */
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r = rs600_gart_enable(rdev);
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if (r)
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return r;
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/* Enable IRQ */
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// rdev->irq.sw_int = true;
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// rs600_irq_set(rdev);
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/* 1M ring buffer */
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// r = r100_cp_init(rdev, 1024 * 1024);
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// if (r) {
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// dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
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// return r;
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// }
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// r = r100_wb_init(rdev);
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// if (r)
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// dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
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// r = r100_ib_init(rdev);
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// if (r) {
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// dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
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// return r;
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// }
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return 0;
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}
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int rs600_init(struct radeon_device *rdev)
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{
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int r;
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/* Disable VGA */
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rv515_vga_render_disable(rdev);
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/* Initialize scratch registers */
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radeon_scratch_init(rdev);
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/* Initialize surface registers */
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radeon_surface_init(rdev);
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/* BIOS */
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if (!radeon_get_bios(rdev)) {
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if (ASIC_IS_AVIVO(rdev))
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return -EINVAL;
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}
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if (rdev->is_atom_bios) {
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r = radeon_atombios_init(rdev);
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if (r)
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return r;
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} else {
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dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n");
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return -EINVAL;
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}
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/* Reset gpu before posting otherwise ATOM will enter infinite loop */
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if (radeon_gpu_reset(rdev)) {
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dev_warn(rdev->dev,
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"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
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RREG32(R_000E40_RBBM_STATUS),
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RREG32(R_0007C0_CP_STAT));
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}
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/* check if cards are posted or not */
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if (!radeon_card_posted(rdev) && rdev->bios) {
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DRM_INFO("GPU not posted. posting now...\n");
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atom_asic_init(rdev->mode_info.atom_context);
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}
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/* Initialize clocks */
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radeon_get_clock_info(rdev->ddev);
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/* Get vram informations */
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rs600_vram_info(rdev);
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/* Initialize memory controller (also test AGP) */
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r = r420_mc_init(rdev);
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if (r)
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return r;
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rs600_debugfs(rdev);
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/* Fence driver */
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// r = radeon_fence_driver_init(rdev);
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// if (r)
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// return r;
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// r = radeon_irq_kms_init(rdev);
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// if (r)
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// return r;
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/* Memory manager */
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r = radeon_object_init(rdev);
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if (r)
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return r;
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r = rs600_gart_init(rdev);
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if (r)
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return r;
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rs600_set_safe_registers(rdev);
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rdev->accel_working = true;
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r = rs600_startup(rdev);
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if (r) {
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/* Somethings want wront with the accel init stop accel */
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dev_err(rdev->dev, "Disabling GPU acceleration\n");
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// rs600_suspend(rdev);
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// r100_cp_fini(rdev);
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// r100_wb_fini(rdev);
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// r100_ib_fini(rdev);
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rs600_gart_fini(rdev);
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// radeon_irq_kms_fini(rdev);
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rdev->accel_working = false;
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}
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return 0;
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}
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