992 lines
31 KiB
NASM
992 lines
31 KiB
NASM
;*****************************************************************************
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;*
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;* Open Watcom Project
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;*
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;* Portions Copyright (c) 1983-2002 Sybase, Inc. All Rights Reserved.
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;*
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;* ========================================================================
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;*
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;* This file contains Original Code and/or Modifications of Original
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;* Code as defined in and that are subject to the Sybase Open Watcom
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;* Public License version 1.0 (the 'License'). You may not use this file
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;* except in compliance with the License. BY USING THIS FILE YOU AGREE TO
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;* ALL TERMS AND CONDITIONS OF THE LICENSE. A copy of the License is
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;* provided with the Original Code and Modifications, and is also
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;* available at www.sybase.com/developer/opensource.
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;*
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;* The Original Code and all software distributed under the License are
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;* distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
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;* EXPRESS OR IMPLIED, AND SYBASE AND ALL CONTRIBUTORS HEREBY DISCLAIM
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;* ALL SUCH WARRANTIES, INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF
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;* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR
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;* NON-INFRINGEMENT. Please see the License for the specific language
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;* governing rights and limitations under the License.
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;*
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;* ========================================================================
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;*
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;* Description: WHEN YOU FIGURE OUT WHAT THIS FILE DOES, PLEASE
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;* DESCRIBE IT HERE!
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;*
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;*****************************************************************************
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; static char sccs_id[] = "@(#)patch32.asm 1.12 12/21/94 14:53:51";
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;
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; This code is being published by Intel to users of the Pentium(tm)
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; processor. Recipients are authorized to copy, modify, compile, use and
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; distribute the code.
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;
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; Intel makes no warranty of any kind with regard to this code, including
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; but not limited to, implied warranties or merchantability and fitness for
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; a particular purpose. Intel assumes no responsibility for any errors that
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; may appear in this code.
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;
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; No patent licenses are granted, express or implied.
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;
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;
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include mdef.inc
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.386
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.387
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DENOM EQU 0
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NUMER EQU 12
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PREV_CW EQU 28 ; 24 + 4 (return size)
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PATCH_CW EQU 32 ; 28 + 4 (return size)
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DENOM_SAVE EQU 32
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MAIN_DENOM EQU 4
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MAIN_NUMER EQU 16
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SPILL_SIZE EQU 12
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MEM_OPERAND EQU 8
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STACK_SIZE EQU 44
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SPILL_MEM_OPERAND EQU 20
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ONESMASK EQU 0e000000h
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SINGLE_NAN EQU 07f800000h
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DOUBLE_NAN EQU 07ff00000h
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ILLEGAL_OPC EQU 6
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f_stsw macro where
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fstsw where
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endm
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fdivr_st MACRO reg_index, reg_index_minus1
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fstp tbyte ptr [esp+DENOM]
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IF reg_index_minus1 GE 1
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fxch st(reg_index_minus1)
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ENDIF
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fstp tbyte ptr [esp+NUMER]
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call fdiv_main_routine
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IF reg_index_minus1 GE 1
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fxch st(reg_index_minus1)
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ENDIF
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fld tbyte ptr [esp+NUMER]
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fxch st(reg_index)
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add esp, STACK_SIZE
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ENDM
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fdivr_sti MACRO reg_index, reg_index_minus1
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fstp tbyte ptr [esp+NUMER]
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IF reg_index_minus1 GE 1
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fxch st(reg_index_minus1)
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ENDIF
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fstp tbyte ptr [esp+DENOM]
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call fdiv_main_routine
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IF reg_index_minus1 GE 1
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fxch st(reg_index_minus1)
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ENDIF
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fld tbyte ptr [esp+NUMER]
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add esp, STACK_SIZE
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ENDM
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fdivrp_sti MACRO reg_index, reg_index_minus1
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fstp tbyte ptr [esp+NUMER]
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IF reg_index_minus1 GE 1
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fxch st(reg_index_minus1)
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ENDIF
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fstp tbyte ptr [esp+DENOM]
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call fdiv_main_routine
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IF reg_index_minus1 GE 1
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fxch st(reg_index_minus1)
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ENDIF
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add esp, STACK_SIZE
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ENDM
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fdiv_st MACRO reg_index, reg_index_minus1
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fstp tbyte ptr [esp+NUMER]
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IF reg_index_minus1 GE 1
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fxch st(reg_index_minus1)
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ENDIF
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fld st
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fstp tbyte ptr [esp+DENOM]
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fstp tbyte ptr [esp+DENOM_SAVE] ; save original denom,
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call fdiv_main_routine
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IF reg_index_minus1 GE 1
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fxch st(reg_index_minus1)
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ENDIF
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fld tbyte ptr [esp+DENOM_SAVE]
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fxch st(reg_index)
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add esp, STACK_SIZE
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ENDM
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fdiv_sti MACRO reg_index, reg_index_minus1
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fxch st(reg_index)
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fstp tbyte ptr [esp+NUMER]
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IF reg_index_minus1 GE 1
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fxch st(reg_index_minus1)
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ENDIF
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fld st
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fstp tbyte ptr [esp+DENOM]
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fstp tbyte ptr [esp+DENOM_SAVE] ; save original denom,
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call fdiv_main_routine
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IF reg_index_minus1 GE 1
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fxch st(reg_index_minus1)
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ENDIF
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fld tbyte ptr [esp+DENOM_SAVE]
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add esp, STACK_SIZE
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ENDM
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fdivp_sti MACRO reg_index, reg_index_minus1
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fstp tbyte ptr [esp+DENOM]
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IF reg_index_minus1 GE 1
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fxch st(reg_index_minus1)
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ENDIF
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fstp tbyte ptr [esp+NUMER]
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call fdiv_main_routine
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IF reg_index_minus1 GE 1
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fxch st(reg_index_minus1)
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ENDIF
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add esp, STACK_SIZE
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ENDM
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_TEXT SEGMENT DWORD USE32 PUBLIC 'CODE'
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_TEXT ENDS
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_DATA SEGMENT DWORD USE32 PUBLIC 'DATA'
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_DATA ENDS
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CONST SEGMENT DWORD USE32 PUBLIC 'DATA'
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CONST ENDS
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_BSS SEGMENT DWORD USE32 PUBLIC 'BSS'
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_BSS ENDS
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DGROUP GROUP CONST,_DATA,_BSS
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_DATA SEGMENT DWORD USE32 PUBLIC 'DATA'
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fdiv_risc_table DB 0, 1, 0, 0, 4, 0, 0, 7, 0, 0, 10, 0, 0, 13, 0, 0
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fdiv_scale_1 DD 03f700000h ;0.9375
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fdiv_scale_2 DD 03f880000h ;1.0625
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one_shl_63 DD 05f000000h
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dispatch_table DD offset label0
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DD offset label1
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DD offset label2
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DD offset label3
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DD offset label4
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DD offset label5
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DD offset label6
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DD offset label7
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DD offset label8
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DD offset label9
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DD offset label10
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DD offset label11
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DD offset label12
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DD offset label13
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DD offset label14
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DD offset label15
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DD offset label16
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DD offset label17
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DD offset label18
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DD offset label19
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DD offset label20
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DD offset label21
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DD offset label22
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DD offset label23
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DD offset label24
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DD offset label25
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DD offset label26
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DD offset label27
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DD offset label28
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DD offset label29
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DD offset label30
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DD offset label31
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DD offset label32
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DD offset label33
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DD offset label34
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DD offset label35
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DD offset label36
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DD offset label37
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DD offset label38
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DD offset label39
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DD offset label40
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DD offset label41
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DD offset label42
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DD offset label43
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DD offset label44
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DD offset label45
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DD offset label46
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DD offset label47
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DD offset label48
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DD offset label49
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DD offset label50
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DD offset label51
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DD offset label52
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DD offset label53
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DD offset label54
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DD offset label55
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DD offset label56
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DD offset label57
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DD offset label58
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DD offset label59
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DD offset label60
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DD offset label61
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DD offset label62
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DD offset label63
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_DATA ENDS
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_TEXT SEGMENT DWORD USE32 PUBLIC 'CODE'
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assume cs:_TEXT, ds:DGROUP, es:DGROUP, ss:nothing
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;
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; PRELIMINARY VERSION for register-register divides.
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;
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; In this implementation the
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; fdiv_main_routine is called,
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; therefore all the stack frame
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; locations are adjusted for the
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; return pointer.
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fdiv_main_routine PROC NEAR
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fld tbyte ptr [esp+MAIN_NUMER] ; load the numerator
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fld tbyte ptr [esp+MAIN_DENOM] ; load the denominator
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retry:
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; The following three lines test for denormals and zeros.
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; A denormal or zero has a 0 in the explicit digit to the left of the
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; binary point. Since that bit is the high bit of the word, adding
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; it to itself will produce a carry if and only if the number is not
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; denormal or zero.
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;
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mov eax, [esp+MAIN_DENOM+4] ; get mantissa bits 32-64
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add eax,eax ; shift the one's bit onto carry
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jnc denormal ; if no carry, we're denormal
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; The following three lines test the three bits after the four bit
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; pattern (1,4,7,a,d). If these three bits are not all one, then
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; the denominator cannot expose the flaw. This condition is tested by
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; inverting the bits and testing that all are equal to zero afterward.
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xor eax, ONESMASK ; invert the bits that must be ones
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test eax, ONESMASK ; and make sure they are all ones
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jz scale_if_needed ; if all are one scale numbers
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fdivp st(1), st ; use of hardware is OK.
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ret
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;
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; Now we test the four bits for one of the five patterns.
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;
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scale_if_needed:
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shr eax, 28 ; keep first 4 bits after point
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cmp byte ptr fdiv_risc_table[eax], 0 ; check for (1,4,7,a,d)
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jnz divide_scaled ; are in potential problem area
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fdivp st(1), st ; use of hardware is OK.
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ret
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divide_scaled:
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mov eax, [esp + MAIN_DENOM+8] ; test denominator exponent
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and eax, 07fffh ; if pseudodenormal ensure that only
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jz invalid_denom ; invalid exception flag is set
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cmp eax, 07fffh ; if NaN or infinity ensure that only
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je invalid_denom ; invalid exception flag is set
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;
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; The following six lines turn off exceptions and set the
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; precision control to 80 bits. The former is necessary to
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; force any traps to be taken at the divide instead of the scaling
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; code. The latter is necessary in order to get full precision for
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; codes with incoming 32 and 64 bit precision settings. If
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; it can be guaranteed that before reaching this point, the underflow
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; exception is masked and the precision control is at 80 bits, these
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; six lines can be omitted.
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;
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fnstcw [esp+PREV_CW] ; save caller's control word
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mov eax, [esp+PREV_CW]
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or eax, 033fh ; mask exceptions, pc=80
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and eax, 0f3ffh ; set rounding mode to nearest
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mov [esp+PATCH_CW], eax
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fldcw [esp+PATCH_CW] ; mask exceptions & pc=80
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; The following lines check the numerator exponent before scaling.
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; This in order to prevent undeflow when scaling the numerator,
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; which will cause a denormal exception flag to be set when the
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; actual divide is preformed. This flag would not have been set
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; normally. If there is a risk of underflow, the scale factor is
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; 17/16 instead of 15/16.
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;
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mov eax, [esp+MAIN_NUMER+8] ; test numerator exponent
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and eax, 07fffh
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cmp eax, 00001h
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je small_numer
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fmul fdiv_scale_1 ; scale denominator by 15/16
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fxch
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fmul fdiv_scale_1 ; scale numerator by 15/16
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fxch
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;
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; The next line restores the users control word. If the incoming
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; control word had the underflow exception masked and precision
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; control set to 80 bits, this line can be omitted.
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;
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fldcw [esp+PREV_CW] ; restore caller's control word
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fdivp st(1), st ; use of hardware is OK.
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ret
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small_numer:
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fmul fdiv_scale_2 ; scale denominator by 17/16
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fxch
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fmul fdiv_scale_2 ; scale numerator by 17/16
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fxch
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;
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; The next line restores the users control word. If the incoming
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; control word had the underflow exception masked and precision
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; control set to 80 bits, this line can be omitted.
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;
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fldcw [esp+PREV_CW] ; restore caller's control word
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fdivp st(1), st ; use of hardware is OK.
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ret
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denormal:
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mov eax, [esp+MAIN_DENOM] ; test for whole mantissa == 0
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or eax, [esp+MAIN_DENOM+4] ; test for whole mantissa == 0
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jnz denormal_divide_scaled ; denominator is not zero
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invalid_denom: ; zero or invalid denominator
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fdivp st(1), st ; use of hardware is OK.
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ret
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denormal_divide_scaled:
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mov eax, [esp + MAIN_DENOM + 8] ; get exponent
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and eax, 07fffh ; check for zero exponent
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jnz invalid_denom ;
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;
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; The following six lines turn off exceptions and set the
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; precision control to 80 bits. The former is necessary to
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; force any traps to be taken at the divide instead of the scaling
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; code. The latter is necessary in order to get full precision for
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; codes with incoming 32 and 64 bit precision settings. If
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; it can be guaranteed that before reaching this point, the underflow
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; exception is masked and the precision control is at 80 bits, these
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; five lines can be omitted.
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;
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fnstcw [esp+PREV_CW] ; save caller's control word
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mov eax, [esp+PREV_CW]
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or eax, 033fh ; mask exceptions, pc=80
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and eax, 0f3ffh ; set rounding mode to nearest
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mov [esp+PATCH_CW], eax
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fldcw [esp+PATCH_CW] ; mask exceptions & pc=80
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mov eax, [esp + MAIN_NUMER +8] ; test numerator exponent
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and eax, 07fffh ; check for denormal numerator
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je denormal_numer
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cmp eax, 07fffh ; NaN or infinity
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je invalid_numer
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mov eax, [esp + MAIN_NUMER + 4] ; get bits 32..63 of mantissa
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add eax, eax ; shift the first bit into carry
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jnc invalid_numer ; if there is no carry, we have an
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; invalid numer
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jmp numer_ok
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denormal_numer:
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mov eax, [esp + MAIN_NUMER + 4] ; get bits 32..63 of mantissa
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add eax, eax ; shift the first bit into carry
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jc invalid_numer ; if there is a carry, we have an
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; invalid numer
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numer_ok:
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fxch
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fstp st ; pop numerator
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fld st ; make copy of denominator
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fmul dword ptr[one_shl_63] ; make denominator not denormal
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fstp tbyte ptr [esp+MAIN_DENOM] ; save modified denominator
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fld tbyte ptr [esp+MAIN_NUMER] ; load numerator
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fxch ; restore proper order
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fwait
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; The next line restores the users control word. If the incoming
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; control word had the underflow exception masked and precision
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; control set to 80 bits, this line can be omitted.
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;
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fldcw [esp+PREV_CW] ; restore caller's control word
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jmp retry ; start the whole thing over
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invalid_numer:
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;
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; The next line restores the users control word. If the incoming
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; control word had the underflow exception masked and precision
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; control set to 80 bits, this line can be omitted.
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;
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fldcw [esp + PREV_CW]
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fdivp st(1), st ; use of hardware is OK.
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ret
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fdiv_main_routine ENDP
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public __fdiv_fpr
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defpe __fdiv_fpr
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sub esp, STACK_SIZE
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jmp dword ptr dispatch_table[eax*4]
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label0:
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fdiv st,st(0) ; D8 F0 FDIV ST,ST(0)
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add esp, STACK_SIZE
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ret
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label1:
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add esp, STACK_SIZE
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int ILLEGAL_OPC
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label2:
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fdivr st,st(0) ; D8 F8 FDIVR ST,ST(0)
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add esp, STACK_SIZE
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ret
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label3:
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add esp, STACK_SIZE
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int ILLEGAL_OPC
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label4:
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fdiv st(0),st ; DC F8/D8 F0 FDIV ST(0),ST
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add esp, STACK_SIZE
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ret
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label5:
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fdivp st(0),st ; DE F8 FDIVP ST(0),ST
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add esp, STACK_SIZE
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ret
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label6:
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fdivr st(0),st ; DC F0/DE F0 FDIVR ST(0),ST
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add esp, STACK_SIZE
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ret
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label7:
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fdivrp st(0),st ; DE F0 FDIVRP ST(0),ST
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add esp, STACK_SIZE
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ret
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label8:
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fdiv_st 1, 0
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ret
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label9:
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add esp, STACK_SIZE
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int ILLEGAL_OPC
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label10:
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fdivr_st 1, 0
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ret
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label11:
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add esp, STACK_SIZE
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int ILLEGAL_OPC
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label12:
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fdiv_sti 1, 0
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ret
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label13:
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fdivp_sti 1, 0
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ret
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label14:
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fdivr_sti 1, 0
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ret
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label15:
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fdivrp_sti 1, 0
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ret
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label16:
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fdiv_st 2, 1
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ret
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label17:
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add esp, STACK_SIZE
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int ILLEGAL_OPC
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label18:
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fdivr_st 2, 1
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ret
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label19:
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add esp, STACK_SIZE
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int ILLEGAL_OPC
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label20:
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fdiv_sti 2, 1
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ret
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label21:
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fdivp_sti 2, 1
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ret
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label22:
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fdivr_sti 2, 1
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ret
|
|
label23:
|
|
fdivrp_sti 2, 1
|
|
ret
|
|
label24:
|
|
fdiv_st 3, 2
|
|
ret
|
|
label25:
|
|
add esp, STACK_SIZE
|
|
int ILLEGAL_OPC
|
|
label26:
|
|
fdivr_st 3, 2
|
|
ret
|
|
label27:
|
|
add esp, STACK_SIZE
|
|
int ILLEGAL_OPC
|
|
label28:
|
|
fdiv_sti 3, 2
|
|
ret
|
|
label29:
|
|
fdivp_sti 3, 2
|
|
ret
|
|
label30:
|
|
fdivr_sti 3, 2
|
|
ret
|
|
label31:
|
|
fdivrp_sti 3, 2
|
|
ret
|
|
label32:
|
|
fdiv_st 4, 3
|
|
ret
|
|
label33:
|
|
add esp, STACK_SIZE
|
|
int ILLEGAL_OPC
|
|
label34:
|
|
fdivr_st 4, 3
|
|
ret
|
|
label35:
|
|
add esp, STACK_SIZE
|
|
int ILLEGAL_OPC
|
|
label36:
|
|
fdiv_sti 4, 3
|
|
ret
|
|
label37:
|
|
fdivp_sti 4, 3
|
|
ret
|
|
label38:
|
|
fdivr_sti 4, 3
|
|
ret
|
|
label39:
|
|
fdivrp_sti 4, 3
|
|
ret
|
|
label40:
|
|
fdiv_st 5, 4
|
|
ret
|
|
label41:
|
|
add esp, STACK_SIZE
|
|
int ILLEGAL_OPC
|
|
label42:
|
|
fdivr_st 5, 4
|
|
ret
|
|
label43:
|
|
add esp, STACK_SIZE
|
|
int ILLEGAL_OPC
|
|
label44:
|
|
fdiv_sti 5, 4
|
|
ret
|
|
label45:
|
|
fdivp_sti 5, 4
|
|
ret
|
|
label46:
|
|
fdivr_sti 5, 4
|
|
ret
|
|
label47:
|
|
fdivrp_sti 5, 4
|
|
ret
|
|
label48:
|
|
fdiv_st 6, 5
|
|
ret
|
|
label49:
|
|
add esp, STACK_SIZE
|
|
int ILLEGAL_OPC
|
|
label50:
|
|
fdivr_st 6, 5
|
|
ret
|
|
label51:
|
|
add esp, STACK_SIZE
|
|
int ILLEGAL_OPC
|
|
label52:
|
|
fdiv_sti 6, 5
|
|
ret
|
|
label53:
|
|
fdivp_sti 6, 5
|
|
ret
|
|
label54:
|
|
fdivr_sti 6, 5
|
|
ret
|
|
label55:
|
|
fdivrp_sti 6, 5
|
|
ret
|
|
label56:
|
|
fdiv_st 7, 6
|
|
ret
|
|
label57:
|
|
add esp, STACK_SIZE
|
|
int ILLEGAL_OPC
|
|
label58:
|
|
fdivr_st 7, 6
|
|
ret
|
|
label59:
|
|
add esp, STACK_SIZE
|
|
int ILLEGAL_OPC
|
|
label60:
|
|
fdiv_sti 7, 6
|
|
ret
|
|
label61:
|
|
fdivp_sti 7, 6
|
|
ret
|
|
label62:
|
|
fdivr_sti 7, 6
|
|
ret
|
|
label63:
|
|
fdivrp_sti 7, 6
|
|
ret
|
|
__fdiv_fpr ENDP
|
|
|
|
|
|
__fdivp_sti_st PROC NEAR
|
|
; for calling from mem routines
|
|
sub esp, STACK_SIZE
|
|
fdivp_sti 1, 0
|
|
ret
|
|
__fdivp_sti_st ENDP
|
|
|
|
__fdivrp_sti_st PROC NEAR
|
|
; for calling from mem routines
|
|
sub esp, STACK_SIZE
|
|
fdivrp_sti 1, 0
|
|
ret
|
|
__fdivrp_sti_st ENDP
|
|
|
|
public __fdiv_chk
|
|
defpe __fdiv_chk
|
|
; for calling from mem routines
|
|
sub esp, STACK_SIZE
|
|
fdivrp_sti 1, 0
|
|
ret
|
|
__fdiv_chk ENDP
|
|
|
|
;
|
|
; PRELIMINARY VERSIONS of the routines for register-memory
|
|
; divide instructions
|
|
;
|
|
|
|
;;; FDIV_M32 - FDIV m32real FIX
|
|
;;
|
|
;; Input : Value of the m32real in the top of STACK
|
|
;;
|
|
;; Output: Result of FDIV in ST
|
|
|
|
PUBLIC __fdiv_m32
|
|
defpe __fdiv_m32
|
|
|
|
push eax ; save eax
|
|
mov eax, [esp + MEM_OPERAND] ; check for
|
|
and eax, SINGLE_NAN ; NaN
|
|
cmp eax, SINGLE_NAN ;
|
|
je memory_divide_m32 ;
|
|
|
|
f_stsw ax ; get status word
|
|
and eax, 3800h ; get top of stack
|
|
je spill_fpstack ; is FP stack full?
|
|
fld dword ptr[esp + MEM_OPERAND] ; load m32real in ST
|
|
call __fdivp_sti_st ; do actual divide
|
|
pop eax
|
|
ret 4
|
|
spill_fpstack:
|
|
fxch
|
|
sub esp, SPILL_SIZE ; make temp space
|
|
fstp tbyte ptr[esp ] ; save user's ST(1)
|
|
fld dword ptr[esp + SPILL_MEM_OPERAND] ; load m32 real
|
|
call __fdivp_sti_st ; do actual divide
|
|
fld tbyte ptr[esp] ; restore user's ST(1)
|
|
;esp is adjusted by fdivrp fn
|
|
fxch
|
|
add esp, SPILL_SIZE
|
|
pop eax
|
|
ret 4
|
|
memory_divide_m32:
|
|
fdiv dword ptr[esp + MEM_OPERAND] ; do actual divide
|
|
pop eax
|
|
ret 4
|
|
|
|
__fdiv_m32 ENDP
|
|
|
|
|
|
;;; FDIV_M64 - FDIV m64real FIX
|
|
;;
|
|
;; Input : Value of the m64real in the top of STACK
|
|
;;
|
|
;; Output: Result of FDIV in ST
|
|
|
|
PUBLIC __fdiv_m64
|
|
defpe __fdiv_m64
|
|
|
|
push eax ; save eax
|
|
mov eax, [esp + MEM_OPERAND + 4] ; check for
|
|
and eax, DOUBLE_NAN ; NaN
|
|
cmp eax, DOUBLE_NAN ;
|
|
je memory_divide_m64 ;
|
|
|
|
f_stsw ax ; get status word
|
|
and eax, 3800h ; get top of stack
|
|
je spill_fpstack_m64 ; is FP stack full?
|
|
fld qword ptr[esp + MEM_OPERAND] ; load m64real in ST
|
|
call __fdivp_sti_st ; do actual divide
|
|
pop eax
|
|
ret 8
|
|
spill_fpstack_m64:
|
|
fxch
|
|
sub esp, SPILL_SIZE ; make temp space
|
|
fstp tbyte ptr[esp] ; save user's ST(1)
|
|
fld qword ptr[esp + SPILL_MEM_OPERAND] ; load m64real
|
|
call __fdivp_sti_st ; do actual divide
|
|
fld tbyte ptr[esp] ; restore user's ST(1)
|
|
;esp is adjusted by fdivrp fn
|
|
fxch
|
|
add esp, SPILL_SIZE
|
|
pop eax
|
|
ret 8
|
|
|
|
memory_divide_m64:
|
|
fdiv qword ptr[esp + MEM_OPERAND] ; do actual divide
|
|
pop eax
|
|
ret 8
|
|
|
|
__fdiv_m64 ENDP
|
|
|
|
|
|
|
|
;;; FDIVR_M32 - FDIVR m32real FIX
|
|
;;
|
|
;; Input : Value of the m32real in the top of STACK
|
|
;;
|
|
;; Output: Result of FDIVR in ST
|
|
|
|
PUBLIC __fdiv_m32r
|
|
defpe __fdiv_m32r
|
|
push eax ; save eax
|
|
mov eax, [esp + MEM_OPERAND] ; check for
|
|
and eax, SINGLE_NAN ; NaN
|
|
cmp eax, SINGLE_NAN ;
|
|
je memory_divide_m32r ;
|
|
|
|
f_stsw ax ; get status word
|
|
and eax, 3800h ; get top of stack
|
|
je spill_fpstack_m32r ; is FP stack full?
|
|
fld dword ptr[esp + MEM_OPERAND] ; load m32real in ST
|
|
call __fdivrp_sti_st ; do actual divide
|
|
pop eax
|
|
ret 4
|
|
spill_fpstack_m32r:
|
|
fxch
|
|
sub esp, SPILL_SIZE ; make temp space
|
|
fstp tbyte ptr[esp ] ; save user's ST(1)
|
|
fld dword ptr[esp + SPILL_MEM_OPERAND] ; load m32 real
|
|
call __fdivrp_sti_st ; do actual divide
|
|
fld tbyte ptr[esp] ; restore user's ST(1)
|
|
;esp is adjusted by fdivp fn
|
|
fxch
|
|
add esp, SPILL_SIZE
|
|
pop eax
|
|
ret 4
|
|
memory_divide_m32r:
|
|
fdivr dword ptr[esp + MEM_OPERAND] ; do actual divide
|
|
pop eax
|
|
ret 4
|
|
|
|
__fdiv_m32r ENDP
|
|
|
|
|
|
;;; FDIVR_M64 - FDIVR m64real FIX
|
|
;;
|
|
;; Input : Value of the m64real in the top of STACK
|
|
;;
|
|
;; Output: Result of FDIVR in ST
|
|
|
|
PUBLIC __fdiv_m64r
|
|
defpe __fdiv_m64r
|
|
push eax ; save eax
|
|
mov eax, [esp + MEM_OPERAND + 4] ; check for
|
|
and eax, DOUBLE_NAN ; NaN
|
|
cmp eax, DOUBLE_NAN ;
|
|
je memory_divide_m64r ;
|
|
|
|
f_stsw ax ; get status word
|
|
and eax, 3800h ; get top of stack
|
|
je spill_fpstack_m64r ; is FP stack full?
|
|
fld qword ptr[esp + MEM_OPERAND] ; load m64real in ST
|
|
call __fdivrp_sti_st ; do actual divide
|
|
pop eax
|
|
ret 8
|
|
spill_fpstack_m64r:
|
|
fxch
|
|
sub esp, SPILL_SIZE ; make temp space
|
|
fstp tbyte ptr[esp ] ; save user's ST(1)
|
|
fld qword ptr[esp + SPILL_MEM_OPERAND] ; load m64real
|
|
call __fdivrp_sti_st ; do actual divide
|
|
fld tbyte ptr[esp] ; restore user's ST(1)
|
|
;esp is adjusted by fdivp fn
|
|
fxch
|
|
add esp, SPILL_SIZE
|
|
pop eax
|
|
ret 8
|
|
memory_divide_m64r:
|
|
fdivr qword ptr[esp + MEM_OPERAND] ; do actual divide
|
|
pop eax
|
|
ret 8
|
|
|
|
|
|
__fdiv_m64r ENDP
|
|
|
|
comment ~******************************************************************
|
|
;;; FDIV_M16I - FDIV m16int FIX
|
|
;;
|
|
;; Input : Value of the m16int in the top of STACK
|
|
;;
|
|
;; Output: Result of FDIV in ST
|
|
|
|
PUBLIC FDIV_M16I
|
|
FDIV_M16I PROC NEAR
|
|
push eax ; save eax
|
|
f_stsw ax ; get status word
|
|
and eax, 3800h ; get top of stack
|
|
je spill_fpstack_m16i ; is FP stack full?
|
|
fild word ptr[esp + MEM_OPERAND] ; load m16int in ST
|
|
call __fdivp_sti_st ; do actual divide
|
|
pop eax
|
|
ret
|
|
spill_fpstack_m16i:
|
|
fxch
|
|
sub esp, SPILL_SIZE ; make temp space
|
|
fstp tbyte ptr[esp ] ; save user's ST(1)
|
|
fild word ptr[esp + SPILL_MEM_OPERAND] ; load m16int
|
|
call __fdivp_sti_st ; do actual divide
|
|
fld tbyte ptr[esp] ; restore user's ST(1)
|
|
;esp is adjusted by fdivrp fn
|
|
fxch
|
|
add esp, SPILL_SIZE
|
|
pop eax
|
|
ret
|
|
|
|
FDIV_M16I ENDP
|
|
|
|
;;; FDIV_M32I - FDIV m16int FIX
|
|
;;
|
|
;; Input : Value of the m16int in the top of STACK
|
|
;;
|
|
;; Output: Result of FDIV in ST
|
|
|
|
PUBLIC FDIV_M32I
|
|
FDIV_M32I PROC NEAR
|
|
push eax ; save eax
|
|
f_stsw ax ; get status word
|
|
and eax, 3800h ; get top of stack
|
|
je spill_fpstack_m32i ; is FP stack full?
|
|
fild dword ptr[esp + MEM_OPERAND] ; load m32int in ST
|
|
call __fdivp_sti_st ; do actual divide
|
|
pop eax
|
|
ret
|
|
spill_fpstack_m32i:
|
|
fxch
|
|
sub esp, SPILL_SIZE ; make temp space
|
|
fstp tbyte ptr[esp ] ; save user's ST(1)
|
|
fild dword ptr[esp + SPILL_MEM_OPERAND] ; load m32int
|
|
call __fdivp_sti_st ; do actual divide
|
|
fld tbyte ptr[esp] ; restore user's ST(1)
|
|
;esp is adjusted by fdivrp fn
|
|
fxch
|
|
add esp, SPILL_SIZE
|
|
pop eax
|
|
ret
|
|
|
|
|
|
FDIV_M32I ENDP
|
|
|
|
|
|
;;; FDIVR_M16I - FDIVR m16int FIX
|
|
;;
|
|
;; Input : Value of the m16int in the top of STACK
|
|
;;
|
|
;; Output: Result of FDIVR in ST
|
|
|
|
PUBLIC FDIVR_M16I
|
|
FDIVR_M16I PROC NEAR
|
|
push eax ; save eax
|
|
f_stsw ax ; get status word
|
|
and eax, 3800h ; get top of stack
|
|
je spill_fpstack_m16ir ; is FP stack full?
|
|
fild word ptr[esp + MEM_OPERAND] ; load m16int in ST
|
|
call __fdivrp_sti_st ; do actual divide
|
|
pop eax
|
|
ret
|
|
spill_fpstack_m16ir:
|
|
fxch
|
|
sub esp, SPILL_SIZE ; make temp space
|
|
fstp tbyte ptr[esp ] ; save user's ST(1)
|
|
fild word ptr[esp + SPILL_MEM_OPERAND] ; load m16int
|
|
call __fdivrp_sti_st ; do actual divide
|
|
fld tbyte ptr[esp] ; restore user's ST(1)
|
|
;esp is adjusted by fdivp fn
|
|
fxch
|
|
add esp, SPILL_SIZE
|
|
pop eax
|
|
ret
|
|
|
|
|
|
FDIVR_M16I ENDP
|
|
|
|
|
|
;;; FDIVR_M32I - FDIVR m32int FIX
|
|
;;
|
|
;; Input : Value of the m32int in the top of STACK
|
|
;;
|
|
;; Output: Result of FDIVR in ST
|
|
|
|
PUBLIC FDIVR_M32I
|
|
FDIVR_M32I PROC NEAR
|
|
push eax ; save eax
|
|
f_stsw ax ; get status word
|
|
and eax, 3800h ; get top of stack
|
|
je spill_fpstack_m32ir ; is FP stack full?
|
|
fild dword ptr[esp + MEM_OPERAND] ; load m32int in ST
|
|
call __fdivrp_sti_st ; do actual divide
|
|
pop eax
|
|
ret
|
|
spill_fpstack_m32ir:
|
|
fxch
|
|
sub esp, SPILL_SIZE ; make temp space
|
|
fstp tbyte ptr[esp ] ; save user's ST(1)
|
|
fild dword ptr[esp + SPILL_MEM_OPERAND] ; load m32int
|
|
call __fdivrp_sti_st ; do actual divide
|
|
fld tbyte ptr[esp] ; restore user's ST(1)
|
|
;esp is adjusted by fdivp fn
|
|
fxch
|
|
add esp, SPILL_SIZE
|
|
pop eax
|
|
ret
|
|
|
|
FDIVR_M32I ENDP
|
|
**********************************************************************~
|
|
|
|
|
|
|
|
_TEXT ENDS
|
|
|
|
end
|