233 lines
6.1 KiB
C
233 lines
6.1 KiB
C
/*
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* ARM specific render optims live here
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*/
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#include "fitz.h"
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typedef unsigned char byte;
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/* always surround cpu specific code with HAVE_XXX */
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#ifdef ARCH_ARM
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/* from imagescalearm.s */
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extern void fz_srow4_arm(byte *src, byte *dst, int w, int denom);
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extern void fz_scol4_arm(byte *src, byte *dst, int w, int denom);
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static void
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path_w4i1o4_arm(byte * restrict rgba, byte * restrict src, byte cov, int len, byte * restrict dst)
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{
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/* The ARM code here is a hand coded implementation of the optimized C version. */
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if (len <= 0)
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return;
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asm volatile(
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"ldr %0, [%0] @ %0 = rgba \n"
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"mov r11,#0 \n"
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"mov r8, #0xFF00 \n"
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"mov r14,%0,lsr #24 @ r14= alpha \n"
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"orr %0, %0, #0xFF000000 @ %0 = rgba |= 0xFF000000 \n"
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"orr r8, r8, r8, LSL #16 @ r8 = 0xFF00FF00 \n"
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"adds r14,r14,r14,LSR #7 @ r14 = alpha += alpha>>7 \n"
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"beq 9f @ if (alpha == 0) bale \n"
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"and r6, %0, r8 @ r6 = ga<<8 \n"
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"bic %0, %0, r8 @ %0 = rb \n"
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"mov r6, r6, LSR #8 @ r6 = ga \n"
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"cmp r14,#256 @ if (alpha == 256) \n"
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"beq 4f @ no-alpha loop \n"
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"B 2f @ enter the loop \n"
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"1: @ Loop used for when coverage*alpha == 0 \n"
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"subs %3, %3, #1 @ len-- \n"
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"ble 9f \n"
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"2: \n"
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"ldrb r12,[%1] @ r12= *src \n"
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"ldr r9, [%4], #4 @ r9 = drb = *dst32++ \n"
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"strb r11,[%1], #1 @ r11= *src++ = 0 \n"
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"add %2, r12, %2 @ %2 = cov += r12 \n"
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"ands %2, %2, #255 @ %2 = cov &= 255 \n"
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"beq 1b @ if coverage == 0 loop back \n"
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"add r10,%2, %2, LSR #7 @ r10= ca = cov+(cov>>7) \n"
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"mul r10,r14,r10 @ r10= ca *= alpha \n"
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"and r7, r8, r9 @ r7 = dga = drb & MASK \n"
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"mov r10,r10,LSR #8 @ r10= ca >>= 8 \n"
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"and r9, r8, r9, LSL #8 @ r9 = drb = (drb<<8) & MASK \n"
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"sub r12,r6, r7, LSR #8 @ r12= cga = ga - (dga>>8) \n"
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"sub r5, %0, r9, LSR #8 @ r5 = crb = rb - (drb>>8) \n"
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"mla r7, r12,r10,r7 @ r7 = dga += cga * ca \n"
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"subs %3, %3, #1 @ len-- \n"
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"mla r9, r5, r10,r9 @ r9 = drb += crb * ca \n"
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"and r7, r8, r7 @ r7 = dga &= MASK \n"
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"and r9, r8, r9 @ r9 = drb &= MASK \n"
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"orr r9, r7, r9, LSR #8 @ r9 = drb = dga | (drb>>8) \n"
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"str r9, [%4, #-4] @ dst32[-1] = r9 \n"
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"bgt 2b \n"
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"b 9f \n"
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"@ --- Solid alpha loop --------------------------------------- \n"
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"3: @ Loop used when coverage == 256 \n"
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"orr r9, %0, r6, LSL #8 @ r9 = rgba \n"
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"str r9, [%4, #-4] @ dst32[-1] = r9 \n"
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"4: @ Loop used for when coverage*alpha == 0 \n"
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"subs %3, %3, #1 @ len-- \n"
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"ble 9f \n"
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"5: \n"
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"ldrb r12,[%1] @ r12= *src \n"
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"ldr r9, [%4], #4 @ r9 = drb = *dst32++ \n"
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"strb r11,[%1], #1 @ r11= *src++ = 0 \n"
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"add %2, r12, %2 @ %2 = cov += r12 \n"
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"ands %2, %2, #255 @ %2 = cov &= 255 \n"
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"beq 4b @ if coverage == 0 loop back \n"
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"cmp %2, #255 @ if coverage == solid \n"
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"beq 3b @ loop back \n"
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"add r10,%2, %2, LSR #7 @ r10= ca = cov+(cov>>7) \n"
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"and r7, r8, r9 @ r7 = dga = drb & MASK \n"
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"and r9, r8, r9, LSL #8 @ r9 = dga = (drb<<8) & MASK \n"
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"sub r12,r6, r7, LSR #8 @ r12= cga = ga - (dga>>8) \n"
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"sub r5, %0, r9, LSR #8 @ r5 = crb = rb - (drb>>8) \n"
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"mla r7, r12,r10,r7 @ r7 = dga += cga * ca \n"
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"subs %3, %3, #1 @ len-- \n"
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"mla r9, r5, r10,r9 @ r9 = drb += crb * ca \n"
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"and r7, r8, r7 @ r7 = dga &= MASK \n"
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"and r9, r8, r9 @ r9 = drb &= MASK \n"
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"orr r9, r7, r9, LSR #8 @ r9 = drb = dga | (drb>>8) \n"
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"str r9, [%4, #-4] @ dst32[-1] = r9 \n"
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"bgt 5b \n"
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"9: @ End \n"
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:
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"+r" (rgba),
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"+r" (src),
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"+r" (cov),
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"+r" (len),
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"+r" (dst)
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:
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:
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"r5","r6","r7","r8","r9","r10","r11","r12","r14","memory","cc"
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);
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}
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static void load_tile8_arm(byte * restrict src, int sw, byte * restrict dst, int dw, int w, int h, int pad)
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{
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if ((h == 0) || (w == 0))
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return;
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switch (pad)
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{
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case 0:
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while (h--)
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{
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memcpy(dst, src, w);
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src += sw;
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dst += dw;
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}
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break;
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case 1:
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sw -= w;
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dw -= w<<1;
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asm volatile(
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"MOV r11,#255 \n"
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"1: \n"
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"MOV r5, %[w] @ r5 = x = w \n"
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"2: \n"
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"LDRB r4, [%[src]], #1 @ r4 = *src++ \n"
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"SUBS r5, r5, #1 \n"
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"STRB r4, [%[dst]], #1 @ *dst++ = r4 \n"
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"STRB r11,[%[dst]], #1 @ *dst++ = 255 \n"
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"BGT 2b \n"
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"ADD %[src],%[src],%[sw] @ src += sw \n"
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"ADD %[dst],%[dst],%[dw] @ dst += dw \n"
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"SUBS %[h],%[h],#1 \n"
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"BGT 1b \n"
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:
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[src] "+r" (src),
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[sw] "+r" (sw),
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[dst] "+r" (dst),
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[dw] "+r" (dw),
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[h] "+r" (h),
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[w] "+r" (w)
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:
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:
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"r4","r5","r11","memory","cc"
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);
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break;
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case 3:
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sw -= w;
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asm volatile(
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"MOV r11,#255 \n"
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"1: \n"
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"MOV r5, %[w] @ r5 = x = w \n"
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"MOV r8, %[dst] @ r8 = dp = dst \n"
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"2: \n"
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"LDRB r4, [%[src]], #1 @ r4 = *src++ \n"
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"LDRB r6, [%[src]], #1 @ r6 = *src++ \n"
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"LDRB r7, [%[src]], #1 @ r7 = *src++ \n"
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"SUBS r5, r5, #3 \n"
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"STRB r4, [r8], #1 @ *dp++ = r4 \n"
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"STRB r6, [r8], #1 @ *dp++ = r6 \n"
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"STRB r7, [r8], #1 @ *dp++ = r7 \n"
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"STRB r11,[r8], #1 @ *dp++ = 255 \n"
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"BGT 2b \n"
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"ADD %[src],%[src],%[sw] @ src += sw \n"
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"ADD %[dst],%[dst],%[dw] @ dst += dw \n"
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"SUBS %[h],%[h],#1 \n"
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"BGT 1b \n"
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:
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[src] "+r" (src),
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[sw] "+r" (sw),
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[dst] "+r" (dst),
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[dw] "+r" (dw),
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[h] "+r" (h),
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[w] "+r" (w)
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:
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:
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"r4","r5","r6","r7","r8","r11","memory","cc"
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);
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break;
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default:
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sw -= w;
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asm volatile(
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"mov r9,#255 \n"
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"1: \n"
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"mov r7, %[dst] @ r7 = dp = dst \n"
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"mov r8, #1 @ r8 = tpad = 1 \n"
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"mov r14,%[w] @ r11= x = w \n"
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"2: \n"
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"ldrb r10,[%[src]],#1 \n"
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"subs r8, r8, #1 \n"
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"moveq r8, %[pad] \n"
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"streqb r9, [r7], #1 \n"
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"strb r10,[r7], #1 \n"
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"subs r14,r14, #1 \n"
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"bgt 2b \n"
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"add %[src],%[src],%[sw] \n"
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"add %[dst],%[dst],%[dw] \n"
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"subs %[h], %[h], #1 \n"
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"bgt 1b \n"
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:
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[src] "+r" (src),
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[sw] "+r" (sw),
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[dst] "+r" (dst),
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[dw] "+r" (dw),
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[h] "+r" (h),
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[w] "+r" (w),
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[pad] "+r" (pad)
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:
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:
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"r7","r8","r9","r10","r14","memory","cc"
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);
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break;
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}
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}
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void
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fz_accelerate_arch(void)
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{
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fz_path_w4i1o4 = path_w4i1o4_arm;
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fz_loadtile8 = load_tile8_arm;
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fz_srow4 = fz_srow4_arm;
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fz_scol4 = fz_scol4_arm;
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}
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#endif
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