fb8dc89b4d
git-svn-id: svn://kolibrios.org@1029 a494cfbc-eb01-0410-851d-a64ba20cac60
549 lines
16 KiB
C
549 lines
16 KiB
C
/*
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* Copyright 2007-2008 Luc Verhaegen <lverhaegen@novell.com>
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* Copyright 2007-2008 Matthias Hopf <mhopf@novell.com>
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* Copyright 2007-2008 Egbert Eich <eich@novell.com>
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* Copyright 2007-2008 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/*
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* Deals with the Primary TMDS device (TMDSA) of R500s, R600s.
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* Gets replaced by DDIA on RS690 and DIG/UNIPHY on RV620.
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "xf86.h"
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/* for usleep */
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#if HAVE_XF86_ANSIC_H
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# include "xf86_ansic.h"
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#else
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# include <unistd.h>
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#endif
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#include "rhd.h"
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#include "rhd_crtc.h"
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#include "rhd_connector.h"
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#include "rhd_output.h"
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#include "rhd_regs.h"
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#include "rhd_hdmi.h"
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#ifdef ATOM_BIOS
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#include "rhd_atombios.h"
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#endif
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struct rhdTMDSPrivate {
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Bool RunsDualLink;
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DisplayModePtr Mode;
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Bool Coherent;
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int PowerState;
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struct rhdHdmi *Hdmi;
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Bool Stored;
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CARD32 StoreControl;
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CARD32 StoreSource;
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CARD32 StoreFormat;
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CARD32 StoreForce;
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CARD32 StoreReduction;
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CARD32 StoreDCBalancer;
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CARD32 StoreDataSynchro;
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CARD32 StoreTXEnable;
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CARD32 StoreMacro;
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CARD32 StoreTXControl;
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CARD32 StoreTXAdjust;
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};
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/*
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* We cannot sense for dual link here at all, plus, we need a bit more work
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* for enabling the transmitter for sensing to happen on most R5xx cards.
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* RV570 (0x7280) and R600 and above seem ok.
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*/
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static enum rhdSensedOutput
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TMDSASense(struct rhdOutput *Output, struct rhdConnector *Connector)
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{
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RHDPtr rhdPtr = RHDPTRI(Output);
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CARD32 Enable, Control, Detect;
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enum rhdConnectorType Type = Connector->Type;
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Bool ret;
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RHDFUNC(Output);
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if ((Type != RHD_CONNECTOR_DVI) && (Type != RHD_CONNECTOR_DVI_SINGLE)) {
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xf86DrvMsg(Output->scrnIndex, X_WARNING,
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"%s: connector type %d is not supported.\n",
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__func__, Type);
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return RHD_SENSED_NONE;
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}
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Enable = RHDRegRead(Output, TMDSA_TRANSMITTER_ENABLE);
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Control = RHDRegRead(Output, TMDSA_TRANSMITTER_CONTROL);
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Detect = RHDRegRead(Output, TMDSA_LOAD_DETECT);
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if (rhdPtr->ChipSet < RHD_R600) {
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RHDRegMask(Output, TMDSA_TRANSMITTER_ENABLE, 0x00000003, 0x00000003);
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RHDRegMask(Output, TMDSA_TRANSMITTER_CONTROL, 0x00000001, 0x00000003);
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}
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RHDRegMask(Output, TMDSA_LOAD_DETECT, 0x00000001, 0x00000001);
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usleep(1);
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ret = RHDRegRead(Output, TMDSA_LOAD_DETECT) & 0x00000010;
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RHDRegMask(Output, TMDSA_LOAD_DETECT, Detect, 0x00000001);
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if (rhdPtr->ChipSet < RHD_R600) {
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RHDRegWrite(Output, TMDSA_TRANSMITTER_ENABLE, Enable);
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RHDRegWrite(Output, TMDSA_TRANSMITTER_CONTROL, Control);
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}
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RHDDebug(Output->scrnIndex, "%s: %s\n", __func__,
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ret ? "Attached" : "Disconnected");
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if (ret)
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return RHD_SENSED_DVI;
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else
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return RHD_SENSED_NONE;
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}
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/*
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*
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*/
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static ModeStatus
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TMDSAModeValid(struct rhdOutput *Output, DisplayModePtr Mode)
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{
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RHDFUNC(Output);
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if (Mode->Flags & V_INTERLACE)
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return MODE_NO_INTERLACE;
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if (Mode->Clock < 25000)
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return MODE_CLOCK_LOW;
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if (Output->Connector->Type == RHD_CONNECTOR_DVI_SINGLE) {
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if (Mode->Clock > 165000)
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return MODE_CLOCK_HIGH;
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} else if (Output->Connector->Type == RHD_CONNECTOR_DVI) {
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if (Mode->Clock > 330000) /* could go higher still */
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return MODE_CLOCK_HIGH;
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}
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return MODE_OK;
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}
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/*
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* This information is not provided in an atombios data table.
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*/
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static struct R5xxTMDSAMacro {
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CARD16 Device;
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CARD32 Macro;
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} R5xxTMDSAMacro[] = {
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{ 0x7104, 0x00C00414 }, /* R520 */
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{ 0x7142, 0x00A00415 }, /* RV515 */
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{ 0x7145, 0x00A00416 }, /* M54 */
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{ 0x7146, 0x00C0041F }, /* RV515 */
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{ 0x7147, 0x00C00418 }, /* RV505 */
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{ 0x7149, 0x00800416 }, /* M56 */
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{ 0x7152, 0x00A00415 }, /* RV515 */
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{ 0x7183, 0x00600412 }, /* RV530 */
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{ 0x71C1, 0x00C0041F }, /* RV535 */
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{ 0x71C2, 0x00A00416 }, /* RV530 */
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{ 0x71C4, 0x00A00416 }, /* M56 */
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{ 0x71C5, 0x00A00416 }, /* M56 */
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{ 0x71C6, 0x00A00513 }, /* RV530 */
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{ 0x71D2, 0x00A00513 }, /* RV530 */
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{ 0x71D5, 0x00A00513 }, /* M66 */
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{ 0x7249, 0x00A00513 }, /* R580 */
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{ 0x724B, 0x00A00513 }, /* R580 */
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{ 0x7280, 0x00C0041F }, /* RV570 */
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{ 0x7288, 0x00C0041F }, /* RV570 */
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{ 0x9400, 0x00910419 }, /* R600: */
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{ 0, 0} /* End marker */
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};
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static struct Rv6xxTMDSAMacro {
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CARD16 Device;
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CARD32 PLL;
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CARD32 TX;
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} Rv6xxTMDSAMacro[] = {
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{ 0x94C1, 0x00010416, 0x00010308 }, /* RV610 */
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{ 0x94C3, 0x00010416, 0x00010308 }, /* RV610 */
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{ 0x9501, 0x00010416, 0x00010308 }, /* RV670: != atombios */
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{ 0x9505, 0x00010416, 0x00010308 }, /* RV670: != atombios */
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{ 0x950F, 0x00010416, 0x00010308 }, /* R680 : != atombios */
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{ 0x9581, 0x00030410, 0x00301044 }, /* M76 */
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{ 0x9587, 0x00010416, 0x00010308 }, /* RV630 */
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{ 0x9588, 0x00010416, 0x00010388 }, /* RV630 */
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{ 0x9589, 0x00010416, 0x00010388 }, /* RV630 */
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{ 0, 0, 0} /* End marker */
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};
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static void
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TMDSAVoltageControl(struct rhdOutput *Output)
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{
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RHDPtr rhdPtr = RHDPTRI(Output);
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int i;
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if (rhdPtr->ChipSet < RHD_RV610) {
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for (i = 0; R5xxTMDSAMacro[i].Device; i++)
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if (R5xxTMDSAMacro[i].Device == rhdPtr->PciDeviceID) {
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RHDRegWrite(Output, TMDSA_MACRO_CONTROL, R5xxTMDSAMacro[i].Macro);
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return;
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}
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xf86DrvMsg(Output->scrnIndex, X_ERROR, "%s: unhandled chipset: 0x%04X.\n",
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__func__, rhdPtr->PciDeviceID);
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xf86DrvMsg(Output->scrnIndex, X_INFO, "TMDSA_MACRO_CONTROL: 0x%08X\n",
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(unsigned int) RHDRegRead(Output, TMDSA_MACRO_CONTROL));
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} else {
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for (i = 0; Rv6xxTMDSAMacro[i].Device; i++)
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if (Rv6xxTMDSAMacro[i].Device == rhdPtr->PciDeviceID) {
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RHDRegWrite(Output, TMDSA_PLL_ADJUST, Rv6xxTMDSAMacro[i].PLL);
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RHDRegWrite(Output, TMDSA_TRANSMITTER_ADJUST, Rv6xxTMDSAMacro[i].TX);
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return;
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}
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xf86DrvMsg(Output->scrnIndex, X_ERROR, "%s: unhandled chipset: 0x%04X.\n",
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__func__, rhdPtr->PciDeviceID);
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xf86DrvMsg(Output->scrnIndex, X_INFO, "TMDSA_PLL_ADJUST: 0x%08X\n",
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(unsigned int) RHDRegRead(Output, TMDSA_PLL_ADJUST));
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xf86DrvMsg(Output->scrnIndex, X_INFO, "TMDSA_TRANSMITTER_ADJUST: 0x%08X\n",
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(unsigned int) RHDRegRead(Output, TMDSA_TRANSMITTER_ADJUST));
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}
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}
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/*
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*
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*/
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static Bool
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TMDSAPropertyControl(struct rhdOutput *Output,
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enum rhdPropertyAction Action, enum rhdOutputProperty Property, union rhdPropertyData *val)
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{
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struct rhdTMDSPrivate *Private = (struct rhdTMDSPrivate *) Output->Private;
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RHDFUNC(Output);
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switch (Action) {
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case rhdPropertyCheck:
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switch (Property) {
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case RHD_OUTPUT_COHERENT:
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return TRUE;
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default:
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return FALSE;
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}
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case rhdPropertyGet:
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switch (Property) {
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case RHD_OUTPUT_COHERENT:
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val->Bool = Private->Coherent;
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return TRUE;
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break;
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default:
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return FALSE;
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}
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break;
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case rhdPropertySet:
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switch (Property) {
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case RHD_OUTPUT_COHERENT:
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Private->Coherent = val->Bool;
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Output->Mode(Output, Private->Mode);
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Output->Power(Output, RHD_POWER_ON);
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break;
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default:
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return FALSE;
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}
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break;
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}
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return TRUE;
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}
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/*
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*
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*/
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static void
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TMDSASet(struct rhdOutput *Output, DisplayModePtr Mode)
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{
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RHDPtr rhdPtr = RHDPTRI(Output);
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struct rhdTMDSPrivate *Private = (struct rhdTMDSPrivate *) Output->Private;
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RHDFUNC(Output);
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/* Clear out some HPD events first: this should be under driver control. */
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RHDRegMask(Output, TMDSA_TRANSMITTER_CONTROL, 0, 0x0000000C);
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RHDRegMask(Output, TMDSA_TRANSMITTER_ENABLE, 0, 0x00070000);
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RHDRegMask(Output, TMDSA_CNTL, 0, 0x00000010);
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/* Disable the transmitter */
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RHDRegMask(Output, TMDSA_TRANSMITTER_ENABLE, 0, 0x00001D1F);
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/* Disable bit reduction and reset temporal dither */
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RHDRegMask(Output, TMDSA_BIT_DEPTH_CONTROL, 0, 0x00010101);
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if (rhdPtr->ChipSet < RHD_R600) {
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RHDRegMask(Output, TMDSA_BIT_DEPTH_CONTROL, 0x04000000, 0x04000000);
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usleep(2);
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RHDRegMask(Output, TMDSA_BIT_DEPTH_CONTROL, 0, 0x04000000);
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} else {
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RHDRegMask(Output, TMDSA_BIT_DEPTH_CONTROL, 0x02000000, 0x02000000);
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usleep(2);
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RHDRegMask(Output, TMDSA_BIT_DEPTH_CONTROL, 0, 0x02000000);
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}
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/* reset phase on vsync and use RGB */
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RHDRegMask(Output, TMDSA_CNTL, 0x00001000, 0x00011000);
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/* Select CRTC, select syncA, no stereosync */
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RHDRegMask(Output, TMDSA_SOURCE_SELECT, Output->Crtc->Id, 0x00010101);
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/* Single link, for now */
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RHDRegWrite(Output, TMDSA_COLOR_FORMAT, 0);
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/* store this for TRANSMITTER_ENABLE in TMDSAPower */
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Private->Mode = Mode;
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if (Mode->SynthClock > 165000) {
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RHDRegMask(Output, TMDSA_CNTL, 0x01000000, 0x01000000);
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Private->RunsDualLink = TRUE; /* for TRANSMITTER_ENABLE in TMDSAPower */
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} else {
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RHDRegMask(Output, TMDSA_CNTL, 0, 0x01000000);
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Private->RunsDualLink = FALSE;
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}
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/* Disable force data */
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RHDRegMask(Output, TMDSA_FORCE_OUTPUT_CNTL, 0, 0x00000001);
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/* DC balancer enable */
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RHDRegMask(Output, TMDSA_DCBALANCER_CONTROL, 0x00000001, 0x00000001);
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TMDSAVoltageControl(Output);
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/* use IDCLK */
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RHDRegMask(Output, TMDSA_TRANSMITTER_CONTROL, 0x00000010, 0x00000010);
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if (Private->Coherent)
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RHDRegMask(Output, TMDSA_TRANSMITTER_CONTROL, 0x00000000, 0x10000000);
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else
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RHDRegMask(Output, TMDSA_TRANSMITTER_CONTROL, 0x10000000, 0x10000000);
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RHDHdmiSetMode(Private->Hdmi, Mode);
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}
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/*
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*
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*/
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static void
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TMDSAPower(struct rhdOutput *Output, int Power)
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{
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RHDPtr rhdPtr = RHDPTRI(Output);
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struct rhdTMDSPrivate *Private = (struct rhdTMDSPrivate *) Output->Private;
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RHDDebug(Output->scrnIndex, "%s(%s,%s)\n",__func__,Output->Name,
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rhdPowerString[Power]);
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switch (Power) {
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case RHD_POWER_ON:
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if (Private->PowerState == RHD_POWER_SHUTDOWN
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|| Private->PowerState == RHD_POWER_UNKNOWN) {
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RHDRegMask(Output, TMDSA_CNTL, 0x1, 0x00000001);
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RHDRegMask(Output, TMDSA_TRANSMITTER_CONTROL, 0x00000001, 0x00000001);
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usleep(20);
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/* reset transmitter PLL */
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RHDRegMask(Output, TMDSA_TRANSMITTER_CONTROL, 0x00000002, 0x00000002);
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usleep(2);
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RHDRegMask(Output, TMDSA_TRANSMITTER_CONTROL, 0, 0x00000002);
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usleep(30);
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/* restart data synchronisation */
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if (rhdPtr->ChipSet < RHD_R600) {
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RHDRegMask(Output, TMDSA_DATA_SYNCHRONIZATION_R500, 0x00000001, 0x00000001);
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usleep(2);
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RHDRegMask(Output, TMDSA_DATA_SYNCHRONIZATION_R500, 0x00000100, 0x00000100);
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RHDRegMask(Output, TMDSA_DATA_SYNCHRONIZATION_R500, 0, 0x00000001);
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} else {
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RHDRegMask(Output, TMDSA_DATA_SYNCHRONIZATION_R600, 0x00000001, 0x00000001);
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usleep(2);
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RHDRegMask(Output, TMDSA_DATA_SYNCHRONIZATION_R600, 0x00000100, 0x00000100);
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RHDRegMask(Output, TMDSA_DATA_SYNCHRONIZATION_R600, 0, 0x00000001);
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}
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}
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if (Private->RunsDualLink) {
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/* bit 9 is not known by anything below RV610, but is ignored by
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the hardware anyway */
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RHDRegMask(Output, TMDSA_TRANSMITTER_ENABLE, 0x00001F1F, 0x00001F1F);
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} else
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RHDRegMask(Output, TMDSA_TRANSMITTER_ENABLE, 0x0000001F, 0x00001F1F);
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if(Output->Connector != NULL && RHDConnectorEnableHDMI(Output->Connector))
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RHDHdmiEnable(Private->Hdmi, TRUE);
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else
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RHDHdmiEnable(Private->Hdmi, FALSE);
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Private->PowerState = RHD_POWER_ON;
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return;
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case RHD_POWER_RESET:
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RHDRegMask(Output, TMDSA_TRANSMITTER_ENABLE, 0, 0x00001F1F);
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/* if we do a RESET after a SHUTDOWN don't raise the power level,
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* and similarly, don't raise from UNKNOWN state. */
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if (Private->PowerState == RHD_POWER_ON)
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Private->PowerState = RHD_POWER_RESET;
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return;
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case RHD_POWER_SHUTDOWN:
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default:
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RHDRegMask(Output, TMDSA_TRANSMITTER_CONTROL, 0x00000002, 0x00000002);
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usleep(2);
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RHDRegMask(Output, TMDSA_TRANSMITTER_CONTROL, 0, 0x00000001);
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RHDRegMask(Output, TMDSA_TRANSMITTER_ENABLE, 0, 0x00001F1F);
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RHDRegMask(Output, TMDSA_CNTL, 0, 0x00000001);
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RHDHdmiEnable(Private->Hdmi, FALSE);
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Private->PowerState = RHD_POWER_SHUTDOWN;
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return;
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}
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}
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/*
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*
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*/
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static void
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TMDSASave(struct rhdOutput *Output)
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{
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int ChipSet = RHDPTRI(Output)->ChipSet;
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struct rhdTMDSPrivate *Private = (struct rhdTMDSPrivate *) Output->Private;
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RHDFUNC(Output);
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Private->StoreControl = RHDRegRead(Output, TMDSA_CNTL);
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Private->StoreSource = RHDRegRead(Output, TMDSA_SOURCE_SELECT);
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Private->StoreFormat = RHDRegRead(Output, TMDSA_COLOR_FORMAT);
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Private->StoreForce = RHDRegRead(Output, TMDSA_FORCE_OUTPUT_CNTL);
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Private->StoreReduction = RHDRegRead(Output, TMDSA_BIT_DEPTH_CONTROL);
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Private->StoreDCBalancer = RHDRegRead(Output, TMDSA_DCBALANCER_CONTROL);
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if (ChipSet < RHD_R600)
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Private->StoreDataSynchro = RHDRegRead(Output, TMDSA_DATA_SYNCHRONIZATION_R500);
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else
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Private->StoreDataSynchro = RHDRegRead(Output, TMDSA_DATA_SYNCHRONIZATION_R600);
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Private->StoreTXEnable = RHDRegRead(Output, TMDSA_TRANSMITTER_ENABLE);
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Private->StoreMacro = RHDRegRead(Output, TMDSA_MACRO_CONTROL);
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Private->StoreTXControl = RHDRegRead(Output, TMDSA_TRANSMITTER_CONTROL);
|
|
|
|
if (ChipSet >= RHD_RV610)
|
|
Private->StoreTXAdjust = RHDRegRead(Output, TMDSA_TRANSMITTER_ADJUST);
|
|
|
|
RHDHdmiSave(Private->Hdmi);
|
|
|
|
Private->Stored = TRUE;
|
|
}
|
|
|
|
/*
|
|
*
|
|
*/
|
|
static void
|
|
TMDSARestore(struct rhdOutput *Output)
|
|
{
|
|
int ChipSet = RHDPTRI(Output)->ChipSet;
|
|
struct rhdTMDSPrivate *Private = (struct rhdTMDSPrivate *) Output->Private;
|
|
|
|
RHDFUNC(Output);
|
|
|
|
if (!Private->Stored) {
|
|
xf86DrvMsg(Output->scrnIndex, X_ERROR,
|
|
"%s: No registers stored.\n", __func__);
|
|
return;
|
|
}
|
|
|
|
RHDRegWrite(Output, TMDSA_CNTL, Private->StoreControl);
|
|
RHDRegWrite(Output, TMDSA_SOURCE_SELECT, Private->StoreSource);
|
|
RHDRegWrite(Output, TMDSA_COLOR_FORMAT, Private->StoreFormat);
|
|
RHDRegWrite(Output, TMDSA_FORCE_OUTPUT_CNTL, Private->StoreForce);
|
|
RHDRegWrite(Output, TMDSA_BIT_DEPTH_CONTROL, Private->StoreReduction);
|
|
RHDRegWrite(Output, TMDSA_DCBALANCER_CONTROL, Private->StoreDCBalancer);
|
|
|
|
if (ChipSet < RHD_R600)
|
|
RHDRegWrite(Output, TMDSA_DATA_SYNCHRONIZATION_R500, Private->StoreDataSynchro);
|
|
else
|
|
RHDRegWrite(Output, TMDSA_DATA_SYNCHRONIZATION_R600, Private->StoreDataSynchro);
|
|
|
|
RHDRegWrite(Output, TMDSA_TRANSMITTER_ENABLE, Private->StoreTXEnable);
|
|
RHDRegWrite(Output, TMDSA_MACRO_CONTROL, Private->StoreMacro);
|
|
RHDRegWrite(Output, TMDSA_TRANSMITTER_CONTROL, Private->StoreTXControl);
|
|
|
|
if (ChipSet >= RHD_RV610)
|
|
RHDRegWrite(Output, TMDSA_TRANSMITTER_ADJUST, Private->StoreTXAdjust);
|
|
|
|
RHDHdmiRestore(Private->Hdmi);
|
|
}
|
|
|
|
/*
|
|
*
|
|
*/
|
|
static void
|
|
TMDSADestroy(struct rhdOutput *Output)
|
|
{
|
|
struct rhdTMDSPrivate *Private = (struct rhdTMDSPrivate *) Output->Private;
|
|
RHDFUNC(Output);
|
|
|
|
if (!Private)
|
|
return;
|
|
|
|
RHDHdmiDestroy(Private->Hdmi);
|
|
|
|
xfree(Private);
|
|
Output->Private = NULL;
|
|
}
|
|
|
|
/*
|
|
*
|
|
*/
|
|
struct rhdOutput *
|
|
RHDTMDSAInit(RHDPtr rhdPtr)
|
|
{
|
|
struct rhdOutput *Output;
|
|
struct rhdTMDSPrivate *Private;
|
|
|
|
RHDFUNC(rhdPtr);
|
|
|
|
Output = xnfcalloc(sizeof(struct rhdOutput), 1);
|
|
|
|
Output->scrnIndex = rhdPtr->scrnIndex;
|
|
Output->Name = "TMDS A";
|
|
Output->Id = RHD_OUTPUT_TMDSA;
|
|
|
|
Output->Sense = TMDSASense;
|
|
Output->ModeValid = TMDSAModeValid;
|
|
Output->Mode = TMDSASet;
|
|
Output->Power = TMDSAPower;
|
|
Output->Save = TMDSASave;
|
|
Output->Restore = TMDSARestore;
|
|
Output->Destroy = TMDSADestroy;
|
|
Output->Property = TMDSAPropertyControl;
|
|
|
|
Private = xnfcalloc(sizeof(struct rhdTMDSPrivate), 1);
|
|
Private->RunsDualLink = FALSE;
|
|
Private->Coherent = FALSE;
|
|
Private->PowerState = RHD_POWER_UNKNOWN;
|
|
|
|
Output->Private = Private;
|
|
|
|
return Output;
|
|
}
|