240 lines
10 KiB
C
240 lines
10 KiB
C
/*====================================================================/*
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opcodes_dd_fd.c -> This file executes the DD/FD PREFIX opcodes.
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The DD prefix "creates" some new instructions by changing HL to IX
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on the opcode defined by the next byte on memory.
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The FD prefix "creates" some new instructions by changing HL to IY
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on the opcode defined by the next byte on memory.
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Change the REGISTER variable to IX or HY before including this file.
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Something like:
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#define REGISTER regs->IX
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#include "op_dd_fd.c"
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#undef REGISTER
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On this code, this REGISTER variable is used as REGISTER.W or
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REGISTER.B.h and REGISTER.B.l ...
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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Copyright (c) 2000 Santiago Romero Iglesias.
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Email: sromero@escomposlinux.org
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=====================================================================*/
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/* 8 clock cycles minimum = DD opcode = FD opcode = 4 + 4 */
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#define REG REGISTER.W
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#define REGL REGISTER.B.l
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#define REGH REGISTER.B.h
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opcode = Z80ReadMem( r_PC );
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r_PC++;
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switch(opcode)
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{
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case ADD_IXY_BC : ADD_WORD(REG, r_BC); AddCycles( 4+4+7 ); break;
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case ADD_IXY_DE : ADD_WORD(REG, r_DE); AddCycles( 4+4+7 ); break;
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case ADD_IXY_SP : ADD_WORD(REG, r_SP); AddCycles( 4+4+7 ); break;
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case ADD_IXY_IXY : ADD_WORD(REG, REG); AddCycles( 4+4+7 ); break;
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case DEC_IXY : REG--; AddCycles( 4+4+2 ); break;
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case INC_IXY : REG++; AddCycles( 4+4 ); break;
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case JP_IXY : r_PC = REG; AddCycles( 4+4 );break;
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case LD_SP_IXY : r_SP = REG; AddCycles( 4+4+2 ); break;
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case PUSH_IXY : PUSH_IXYr(); AddCycles( 4+4+3+3+1 ); break;
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case POP_IXY : POP_IXYr(); AddCycles( 4+4+3+3 ); break;
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case EX_IXY_xSP : r_meml = Z80ReadMem(r_SP);
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r_memh = Z80ReadMem(r_SP+1);
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Z80WriteMem( r_SP, REGL, regs );
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Z80WriteMem( r_SP+1, REGH, regs );
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REGL=r_meml; REGH=r_memh;
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AddCycles( 4+4+3+3+3+3+3 ); break;
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case LD_A_xIXY : r_A = Z80ReadMem( REG+ ((offset) Z80ReadMem(r_PC)) );
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r_PC++; AddCycles( 4+3+3+3+3+3 ); break;
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case LD_B_xIXY : r_B = Z80ReadMem( REG+ ((offset) Z80ReadMem(r_PC)) );
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r_PC++; AddCycles( 4+3+3+3+3+3 ); break;
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case LD_C_xIXY : r_C = Z80ReadMem( REG+ ((offset) Z80ReadMem(r_PC)) );
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r_PC++; AddCycles( 4+3+3+3+3+3 ); break;
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case LD_D_xIXY : r_D = Z80ReadMem( REG+ ((offset) Z80ReadMem(r_PC)) );
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r_PC++; AddCycles( 4+3+3+3+3+3 ); break;
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case LD_E_xIXY : r_E = Z80ReadMem( REG+ ((offset) Z80ReadMem(r_PC)) );
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r_PC++; AddCycles( 4+3+3+3+3+3 ); break;
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case LD_xIXY_A : Z80WriteMem( REG+(offset)Z80ReadMem(r_PC), r_A, regs );
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r_PC++; AddCycles( 4+3+3+3+3+3 ); break;
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case LD_xIXY_B : Z80WriteMem( REG+(offset)Z80ReadMem(r_PC), r_B, regs );
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r_PC++; AddCycles( 4+3+3+3+3+3 ); break;
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case LD_xIXY_C : Z80WriteMem( REG+(offset)Z80ReadMem(r_PC), r_C, regs );
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r_PC++; AddCycles( 4+3+3+3+3+3 ); break;
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case LD_xIXY_D : Z80WriteMem( REG+(offset)Z80ReadMem(r_PC), r_D, regs );
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r_PC++; AddCycles( 4+3+3+3+3+3 ); break;
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case LD_xIXY_E : Z80WriteMem( REG+(offset)Z80ReadMem(r_PC), r_E, regs );
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r_PC++; AddCycles( 4+3+3+3+3+3 ); break;
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case INC_xIXY : r_mem = REG+(offset)Z80ReadMem(r_PC);
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r_PC++;
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tmpreg.B.l = Z80ReadMem(r_mem);
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INC(tmpreg.B.l);
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Z80WriteMem(r_mem, tmpreg.B.l, regs );
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AddCycles( 4+3+3 + 3+3+3+ 3+1); break;
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case DEC_xIXY : r_mem = REG+(offset)Z80ReadMem(r_PC);
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r_PC++;
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tmpreg.B.l = Z80ReadMem(r_mem);
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DEC(tmpreg.B.l);
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Z80WriteMem(r_mem, tmpreg.B.l, regs );
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AddCycles( 4+3+3 + 3+3+3+ 3+1); break;
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case ADC_xIXY : r_meml = Z80ReadMem(REG+(offset)Z80ReadMem(r_PC)); r_PC++;
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ADC(r_meml); AddCycles( 4+3+3+3+3+3 ); break;
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case SBC_xIXY : r_meml = Z80ReadMem(REG+(offset)Z80ReadMem(r_PC));
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r_PC++;
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SBC(r_meml); AddCycles( 4+3+3+3+3+3 ); break;
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case ADD_xIXY : r_meml = Z80ReadMem(REG+(offset)Z80ReadMem(r_PC));
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r_PC++;
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ADD(r_meml); AddCycles( 4+3+3+3+3+3 ); break;
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case SUB_xIXY : r_meml = Z80ReadMem(REG+(offset)Z80ReadMem(r_PC));
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r_PC++;
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SUB(r_meml); AddCycles( 4+3+3+3+3+3 ); break;
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case AND_xIXY : r_meml = Z80ReadMem(REG+(offset)Z80ReadMem(r_PC));
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r_PC++;
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AND(r_meml); AddCycles( 4+3+3+3+3+3 ); break;
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case OR_xIXY : r_meml = Z80ReadMem(REG+(offset)Z80ReadMem(r_PC));
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r_PC++;
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OR(r_meml); AddCycles( 4+3+3+3+3+3 ); break;
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case XOR_xIXY : r_meml = Z80ReadMem(REG+(offset)Z80ReadMem(r_PC));
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r_PC++;
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XOR(r_meml); AddCycles( 4+3+3+3+3+3 ); break;
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case CP_xIXY : r_meml = Z80ReadMem(REG+(offset)Z80ReadMem(r_PC));
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r_PC++;
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CP(r_meml); AddCycles( 4+3+3+3+3+3 ); break;
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case LD_IXY_NN : REGL = Z80ReadMem(r_PC); r_PC++;
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REGH = Z80ReadMem(r_PC); r_PC++;
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AddCycles( 4+1+3+3+3 ); break;
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case LD_xIXY_N : r_mem = REG + (offset) Z80ReadMem(r_PC); r_PC++;
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Z80WriteMem( r_mem, Z80ReadMem(r_PC), regs ); r_PC++;
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AddCycles( 4+3+3+3+3+3 ); break;
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case LD_IXY_xNN : LOAD_rr_nn(REG);
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AddCycles( 4+3+3+3+3+3+1 ); break;
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case LD_xNN_IXY : STORE_nn_rr(REG);
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AddCycles( 4+3+3+ 3+3+3+1 ); break;
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/* some undocumented opcodes: may be wrong: */
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case LD_A_IXYh : r_A = REGH; AddCycles(4+4); break;
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case LD_A_IXYl : r_A = REGL; AddCycles(4+4); break;
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case LD_B_IXYh : r_B = REGH; AddCycles(4+4); break;
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case LD_B_IXYl : r_B = REGL; AddCycles(4+4); break;
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case LD_C_IXYh : r_C = REGH; AddCycles(4+4); break;
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case LD_C_IXYl : r_C = REGL; AddCycles(4+4); break;
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case LD_D_IXYh : r_D = REGH; AddCycles(4+4); break;
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case LD_D_IXYl : r_D = REGL; AddCycles(4+4); break;
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case LD_E_IXYh : r_E = REGH; AddCycles(4+4); break;
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case LD_E_IXYl : r_E = REGL; AddCycles(4+4); break;
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case LD_IXYh_A : REGH = r_A; AddCycles(4+4); break;
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case LD_IXYh_B : REGH = r_B; AddCycles(4+4); break;
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case LD_IXYh_C : REGH = r_C; AddCycles(4+4); break;
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case LD_IXYh_D : REGH = r_D; AddCycles(4+4); break;
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case LD_IXYh_E : REGH = r_E; AddCycles(4+4); break;
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case LD_IXYh_IXYh : AddCycles(4+4); break;
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case LD_IXYh_IXYl : REGH = REGL; AddCycles(4+4); break;
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case LD_IXYl_A : REGL = r_A; AddCycles(4+4); break;
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case LD_IXYl_B : REGL = r_B; AddCycles(4+4); break;
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case LD_IXYl_C : REGL = r_C; AddCycles(4+4); break;
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case LD_IXYl_D : REGL = r_D; AddCycles(4+4); break;
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case LD_IXYl_E : REGL = r_E; AddCycles(4+4); break;
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case LD_IXYl_IXYh : REGL = REGH; AddCycles(4+4); break;
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case LD_IXYl_IXYl : AddCycles(4+4); break;
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case LD_IXYh_N : REGH = Z80ReadMem(r_PC); r_PC++;
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AddCycles(4+4+3); break;
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case LD_IXYl_N : REGL = Z80ReadMem(r_PC); r_PC++;
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AddCycles(4+4+3); break;
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case ADD_IXYh : ADD(REGH); AddCycles(4+4); break;
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case ADD_IXYl : ADD(REGL); AddCycles(4+4); break;
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case ADC_IXYh : ADC(REGH); AddCycles(4+4); break;
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case ADC_IXYl : ADC(REGL); AddCycles(4+4); break;
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case SUB_IXYh : SUB(REGH); AddCycles(4+4); break;
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case SUB_IXYl : SUB(REGL); AddCycles(4+4); break;
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case SBC_IXYh : SBC(REGH); AddCycles(4+4); break;
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case SBC_IXYl : SBC(REGL); AddCycles(4+4); break;
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case AND_IXYh : AND(REGH); AddCycles(4+4); break;
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case AND_IXYl : AND(REGL); AddCycles(4+4); break;
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case XOR_IXYh : XOR(REGH); AddCycles(4+4); break;
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case XOR_IXYl : XOR(REGL); AddCycles(4+4); break;
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case OR_IXYh : OR(REGH); AddCycles(4+4); break;
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case OR_IXYl : OR(REGL); AddCycles(4+4); break;
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case CP_IXYh : CP(REGH); AddCycles(4+4); break;
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case CP_IXYl : CP(REGL); AddCycles(4+4); break;
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case INC_IXYh : INC(REGH); AddCycles(4+4); break;
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case INC_IXYl : INC(REGL); AddCycles(4+4); break;
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case DEC_IXYh : DEC(REGH); AddCycles(4+4); break;
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case DEC_IXYl : DEC(REGL); AddCycles(4+4); break;
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case LD_xIXY_H : r_meml =Z80ReadMem(r_PC); r_PC++;
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Z80WriteMem( REG+(offset)(r_meml), r_H, regs );
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AddCycles( 4+3+3+3+3+3 ); break;
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case LD_xIXY_L : r_meml =Z80ReadMem(r_PC); r_PC++;
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Z80WriteMem( REG+(offset)(r_meml), r_L, regs );
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AddCycles( 4+3+3+3+3+3 ); break;
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case LD_H_xIXY : r_meml =Z80ReadMem(r_PC); r_PC++;
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r_H = Z80ReadMem( REG+(offset)(r_meml));
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AddCycles( 4+3+3+3+3+3 ); break;
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case LD_L_xIXY : r_meml =Z80ReadMem(r_PC); r_PC++;
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r_L = Z80ReadMem( REG+(offset)(r_meml));
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AddCycles( 4+3+3+3+3+3 ); break;
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case PREFIX_CB:
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#include "opddfdcb.c"
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break;
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/*
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case PREFIX_DD:
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case PREFIX_FD: AddCycles( 4 );
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r_PC--; // decode it the next time :)
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break;
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*/
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default: AddCycles( 4 );
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r_PC--; /* decode it the next time :) */
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SubR(1);
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// exit(1);
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// if( regs->DecodingErrors )
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// {
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// printf("z80 core: Unknown instruction: ");
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// if ( regs->we_are_on_ddfd == WE_ARE_ON_DD )
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// printf("DD ");
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// else
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// printf("FD ");
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// printf("%02Xh at PC=%04Xh.\n", Z80ReadMem(r_PC-1), r_PC-2 );
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// }
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break;
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}
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#undef REG
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#undef REGL
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#undef REGH
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