forked from KolibriOS/kolibrios
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git-svn-id: svn://kolibrios.org@4926 a494cfbc-eb01-0410-851d-a64ba20cac60
This commit is contained in:
Sergey Semyonov (Serge)
parent
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commit
06465dfb69
537
contrib/sdk/includes/pciaccess.h
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537
contrib/sdk/includes/pciaccess.h
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/*
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* (C) Copyright IBM Corporation 2006
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* Copyright 2009 Red Hat, Inc.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* on the rights to use, copy, modify, merge, publish, distribute, sub
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* license, and/or sell copies of the Software, and to permit persons to whom
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* the Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* IBM AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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/*
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* Copyright (c) 2007 Paulo R. Zanoni, Tiago Vignatti
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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/**
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* \file pciaccess.h
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*
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* \author Ian Romanick <idr@us.ibm.com>
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*/
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#ifndef PCIACCESS_H
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#define PCIACCESS_H
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#include <inttypes.h>
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#if __GNUC__ >= 3
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#define __deprecated __attribute__((deprecated))
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#else
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#define __deprecated
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#endif
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typedef uint64_t pciaddr_t;
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struct pci_device;
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struct pci_device_iterator;
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struct pci_id_match;
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struct pci_slot_match;
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#ifdef __cplusplus
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extern "C" {
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#endif
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int pci_device_has_kernel_driver(struct pci_device *dev);
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int pci_device_is_boot_vga(struct pci_device *dev);
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int pci_device_read_rom(struct pci_device *dev, void *buffer);
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int __deprecated pci_device_map_region(struct pci_device *dev,
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unsigned region, int write_enable);
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int __deprecated pci_device_unmap_region(struct pci_device *dev,
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unsigned region);
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int pci_device_map_range(struct pci_device *dev, pciaddr_t base,
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pciaddr_t size, unsigned map_flags, void **addr);
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int pci_device_unmap_range(struct pci_device *dev, void *memory,
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pciaddr_t size);
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int __deprecated pci_device_map_memory_range(struct pci_device *dev,
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pciaddr_t base, pciaddr_t size, int write_enable, void **addr);
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int __deprecated pci_device_unmap_memory_range(struct pci_device *dev,
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void *memory, pciaddr_t size);
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int pci_device_probe(struct pci_device *dev);
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const struct pci_agp_info *pci_device_get_agp_info(struct pci_device *dev);
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const struct pci_bridge_info *pci_device_get_bridge_info(
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struct pci_device *dev);
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const struct pci_pcmcia_bridge_info *pci_device_get_pcmcia_bridge_info(
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struct pci_device *dev);
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int pci_device_get_bridge_buses(struct pci_device *dev, int *primary_bus,
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int *secondary_bus, int *subordinate_bus);
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int pci_system_init(void);
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void pci_system_init_dev_mem(int fd);
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void pci_system_cleanup(void);
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struct pci_device_iterator *pci_slot_match_iterator_create(
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const struct pci_slot_match *match);
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struct pci_device_iterator *pci_id_match_iterator_create(
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const struct pci_id_match *match);
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void pci_iterator_destroy(struct pci_device_iterator *iter);
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struct pci_device *pci_device_next(struct pci_device_iterator *iter);
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struct pci_device *pci_device_find_by_slot(uint32_t domain, uint32_t bus,
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uint32_t dev, uint32_t func);
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struct pci_device *pci_device_get_parent_bridge(struct pci_device *dev);
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void pci_get_strings(const struct pci_id_match *m,
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const char **device_name, const char **vendor_name,
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const char **subdevice_name, const char **subvendor_name);
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const char *pci_device_get_device_name(const struct pci_device *dev);
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const char *pci_device_get_subdevice_name(const struct pci_device *dev);
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const char *pci_device_get_vendor_name(const struct pci_device *dev);
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const char *pci_device_get_subvendor_name(const struct pci_device *dev);
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void pci_device_enable(struct pci_device *dev);
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int pci_device_cfg_read (struct pci_device *dev, void *data,
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pciaddr_t offset, pciaddr_t size, pciaddr_t *bytes_read);
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int pci_device_cfg_read_u8 (struct pci_device *dev, uint8_t *data,
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pciaddr_t offset);
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int pci_device_cfg_read_u16(struct pci_device *dev, uint16_t *data,
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pciaddr_t offset);
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int pci_device_cfg_read_u32(struct pci_device *dev, uint32_t *data,
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pciaddr_t offset);
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int pci_device_cfg_write (struct pci_device *dev, const void *data,
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pciaddr_t offset, pciaddr_t size, pciaddr_t *bytes_written);
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int pci_device_cfg_write_u8 (struct pci_device *dev, uint8_t data,
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pciaddr_t offset);
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int pci_device_cfg_write_u16(struct pci_device *dev, uint16_t data,
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pciaddr_t offset);
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int pci_device_cfg_write_u32(struct pci_device *dev, uint32_t data,
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pciaddr_t offset);
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int pci_device_cfg_write_bits(struct pci_device *dev, uint32_t mask,
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uint32_t data, pciaddr_t offset);
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#ifdef __cplusplus
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}
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#endif
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/**
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* \name Mapping flags passed to \c pci_device_map_range
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*/
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/*@{*/
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#define PCI_DEV_MAP_FLAG_WRITABLE (1U<<0)
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#define PCI_DEV_MAP_FLAG_WRITE_COMBINE (1U<<1)
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#define PCI_DEV_MAP_FLAG_CACHABLE (1U<<2)
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/*@}*/
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#define PCI_MATCH_ANY (~0)
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/**
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* Compare two PCI ID values (either vendor or device). This is used
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* internally to compare the fields of \c pci_id_match to the fields of
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* \c pci_device.
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*/
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#define PCI_ID_COMPARE(a, b) \
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(((a) == PCI_MATCH_ANY) || ((a) == (b)))
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/**
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*/
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struct pci_id_match {
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/**
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* \name Device / vendor matching controls
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*
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* Control the search based on the device, vendor, subdevice, or subvendor
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* IDs. Setting any of these fields to \c PCI_MATCH_ANY will cause the
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* field to not be used in the comparison.
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*/
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/*@{*/
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uint32_t vendor_id;
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uint32_t device_id;
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uint32_t subvendor_id;
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uint32_t subdevice_id;
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/*@}*/
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/**
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* \name Device class matching controls
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*
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*/
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/*@{*/
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uint32_t device_class;
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uint32_t device_class_mask;
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/*@}*/
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intptr_t match_data;
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};
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/**
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*/
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struct pci_slot_match {
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/**
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* \name Device slot matching controls
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*
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* Control the search based on the domain, bus, slot, and function of
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* the device. Setting any of these fields to \c PCI_MATCH_ANY will cause
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* the field to not be used in the comparison.
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*/
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/*@{*/
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uint32_t domain;
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uint32_t bus;
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uint32_t dev;
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uint32_t func;
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/*@}*/
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intptr_t match_data;
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};
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/**
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* BAR descriptor for a PCI device.
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*/
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struct pci_mem_region {
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/**
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* When the region is mapped, this is the pointer to the memory.
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*
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* This field is \b only set when the deprecated \c pci_device_map_region
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* interface is used. Use \c pci_device_map_range instead.
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*
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* \deprecated
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*/
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void *memory;
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/**
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* Base physical address of the region within its bus / domain.
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*
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* \warning
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* This address is really only useful to other devices in the same
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* domain. It's probably \b not the address applications will ever
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* use.
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*
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* \warning
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* Most (all?) platform back-ends leave this field unset.
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*/
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pciaddr_t bus_addr;
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/**
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* Base physical address of the region from the CPU's point of view.
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*
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* This address is typically passed to \c pci_device_map_range to create
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* a mapping of the region to the CPU's virtual address space.
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*/
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pciaddr_t base_addr;
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/**
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* Size, in bytes, of the region.
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*/
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pciaddr_t size;
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/**
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* Is the region I/O ports or memory?
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*/
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unsigned is_IO:1;
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/**
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* Is the memory region prefetchable?
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*
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* \note
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* This can only be set if \c is_IO is not set.
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*/
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unsigned is_prefetchable:1;
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/**
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* Is the memory at a 64-bit address?
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*
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* \note
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* This can only be set if \c is_IO is not set.
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*/
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unsigned is_64:1;
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};
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/**
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* PCI device.
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*
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* Contains all of the information about a particular PCI device.
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*/
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struct pci_device {
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/**
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* \name Device bus identification.
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*
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* Complete bus identification, including domain, of the device. On
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* platforms that do not support PCI domains (e.g., 32-bit x86 hardware),
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* the domain will always be zero.
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*/
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/*@{*/
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uint16_t domain;
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uint8_t bus;
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uint8_t dev;
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uint8_t func;
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/*@}*/
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/**
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* \name Vendor / device ID
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*
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* The vendor ID, device ID, and sub-IDs for the device.
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*/
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/*@{*/
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uint16_t vendor_id;
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uint16_t device_id;
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uint16_t subvendor_id;
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uint16_t subdevice_id;
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/*@}*/
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/**
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* Device's class, subclass, and programming interface packed into a
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* single 32-bit value. The class is at bits [23:16], subclass is at
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* bits [15:8], and programming interface is at [7:0].
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*/
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uint32_t device_class;
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/**
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* Device revision number, as read from the configuration header.
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*/
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uint8_t revision;
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/**
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* BAR descriptors for the device.
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*/
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struct pci_mem_region regions[6];
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/**
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* Size, in bytes, of the device's expansion ROM.
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*/
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pciaddr_t rom_size;
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/**
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* IRQ associated with the device. If there is no IRQ, this value will
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* be -1.
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*/
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int irq;
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/**
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* Storage for user data. Users of the library can store arbitrary
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|
* data in this pointer. The library will not use it for any purpose.
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* It is the user's responsability to free this memory before destroying
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* the \c pci_device structure.
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|
*/
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intptr_t user_data;
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|
/**
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|
* Used by the VGA arbiter. Type of resource decoded by the device and
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|
* the file descriptor (/dev/vga_arbiter). */
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|
int vgaarb_rsrc;
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|
};
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|
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|
/**
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||||||
|
* Description of the AGP capability of the device.
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|
*
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|
* \sa pci_device_get_agp_info
|
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|
*/
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|
struct pci_agp_info {
|
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|
/**
|
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|
* Offset of the AGP registers in the devices configuration register
|
||||||
|
* space. This is generally used so that the offset of the AGP command
|
||||||
|
* register can be determined.
|
||||||
|
*/
|
||||||
|
unsigned config_offset;
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* \name AGP major / minor version.
|
||||||
|
*/
|
||||||
|
/*@{*/
|
||||||
|
uint8_t major_version;
|
||||||
|
uint8_t minor_version;
|
||||||
|
/*@}*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Logical OR of the supported AGP rates. For example, a value of 0x07
|
||||||
|
* means that the device can support 1x, 2x, and 4x. A value of 0x0c
|
||||||
|
* means that the device can support 8x and 4x.
|
||||||
|
*/
|
||||||
|
uint8_t rates;
|
||||||
|
|
||||||
|
unsigned int fast_writes:1; /**< Are fast-writes supported? */
|
||||||
|
unsigned int addr64:1;
|
||||||
|
unsigned int htrans:1;
|
||||||
|
unsigned int gart64:1;
|
||||||
|
unsigned int coherent:1;
|
||||||
|
unsigned int sideband:1; /**< Is side-band addressing supported? */
|
||||||
|
unsigned int isochronus:1;
|
||||||
|
|
||||||
|
uint8_t async_req_size;
|
||||||
|
uint8_t calibration_cycle_timing;
|
||||||
|
uint8_t max_requests;
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Description of a PCI-to-PCI bridge device.
|
||||||
|
*
|
||||||
|
* \sa pci_device_get_bridge_info
|
||||||
|
*/
|
||||||
|
struct pci_bridge_info {
|
||||||
|
uint8_t primary_bus;
|
||||||
|
uint8_t secondary_bus;
|
||||||
|
uint8_t subordinate_bus;
|
||||||
|
uint8_t secondary_latency_timer;
|
||||||
|
|
||||||
|
uint8_t io_type;
|
||||||
|
uint8_t mem_type;
|
||||||
|
uint8_t prefetch_mem_type;
|
||||||
|
|
||||||
|
uint16_t secondary_status;
|
||||||
|
uint16_t bridge_control;
|
||||||
|
|
||||||
|
uint32_t io_base;
|
||||||
|
uint32_t io_limit;
|
||||||
|
|
||||||
|
uint32_t mem_base;
|
||||||
|
uint32_t mem_limit;
|
||||||
|
|
||||||
|
uint64_t prefetch_mem_base;
|
||||||
|
uint64_t prefetch_mem_limit;
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Description of a PCI-to-PCMCIA bridge device.
|
||||||
|
*
|
||||||
|
* \sa pci_device_get_pcmcia_bridge_info
|
||||||
|
*/
|
||||||
|
struct pci_pcmcia_bridge_info {
|
||||||
|
uint8_t primary_bus;
|
||||||
|
uint8_t card_bus;
|
||||||
|
uint8_t subordinate_bus;
|
||||||
|
uint8_t cardbus_latency_timer;
|
||||||
|
|
||||||
|
uint16_t secondary_status;
|
||||||
|
uint16_t bridge_control;
|
||||||
|
|
||||||
|
struct {
|
||||||
|
uint32_t base;
|
||||||
|
uint32_t limit;
|
||||||
|
} io[2];
|
||||||
|
|
||||||
|
struct {
|
||||||
|
uint32_t base;
|
||||||
|
uint32_t limit;
|
||||||
|
} mem[2];
|
||||||
|
|
||||||
|
};
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* VGA Arbiter definitions, functions and related.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Legacy VGA regions */
|
||||||
|
#define VGA_ARB_RSRC_NONE 0x00
|
||||||
|
#define VGA_ARB_RSRC_LEGACY_IO 0x01
|
||||||
|
#define VGA_ARB_RSRC_LEGACY_MEM 0x02
|
||||||
|
/* Non-legacy access */
|
||||||
|
#define VGA_ARB_RSRC_NORMAL_IO 0x04
|
||||||
|
#define VGA_ARB_RSRC_NORMAL_MEM 0x08
|
||||||
|
|
||||||
|
int pci_device_vgaarb_init (void);
|
||||||
|
void pci_device_vgaarb_fini (void);
|
||||||
|
int pci_device_vgaarb_set_target (struct pci_device *dev);
|
||||||
|
/* use the targetted device */
|
||||||
|
int pci_device_vgaarb_decodes (int new_vga_rsrc);
|
||||||
|
int pci_device_vgaarb_lock (void);
|
||||||
|
int pci_device_vgaarb_trylock (void);
|
||||||
|
int pci_device_vgaarb_unlock (void);
|
||||||
|
/* return the current device count + resource decodes for the device */
|
||||||
|
int pci_device_vgaarb_get_info (struct pci_device *dev, int *vga_count, int *rsrc_decodes);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* I/O space access.
|
||||||
|
*/
|
||||||
|
|
||||||
|
struct pci_io_handle;
|
||||||
|
|
||||||
|
struct pci_io_handle *pci_device_open_io(struct pci_device *dev, pciaddr_t base,
|
||||||
|
pciaddr_t size);
|
||||||
|
struct pci_io_handle *pci_legacy_open_io(struct pci_device *dev, pciaddr_t base,
|
||||||
|
pciaddr_t size);
|
||||||
|
void pci_device_close_io(struct pci_device *dev, struct pci_io_handle *handle);
|
||||||
|
uint32_t pci_io_read32(struct pci_io_handle *handle, uint32_t reg);
|
||||||
|
uint16_t pci_io_read16(struct pci_io_handle *handle, uint32_t reg);
|
||||||
|
uint8_t pci_io_read8(struct pci_io_handle *handle, uint32_t reg);
|
||||||
|
void pci_io_write32(struct pci_io_handle *handle, uint32_t reg, uint32_t data);
|
||||||
|
void pci_io_write16(struct pci_io_handle *handle, uint32_t reg, uint16_t data);
|
||||||
|
void pci_io_write8(struct pci_io_handle *handle, uint32_t reg, uint8_t data);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Legacy memory access
|
||||||
|
*/
|
||||||
|
|
||||||
|
int pci_device_map_legacy(struct pci_device *dev, pciaddr_t base,
|
||||||
|
pciaddr_t size, unsigned map_flags, void **addr);
|
||||||
|
int pci_device_unmap_legacy(struct pci_device *dev, void *addr, pciaddr_t size);
|
||||||
|
|
||||||
|
#endif /* PCIACCESS_H */
|
||||||
Loading…
Reference in New Issue
Block a user