From 17e3dfb91d2dfd71cdd5ee9e73b0f8a70cb74e74 Mon Sep 17 00:00:00 2001 From: "Sergey Semyonov (Serge)" Date: Tue, 1 Jul 2008 09:36:00 +0000 Subject: [PATCH] use R300 pio mode git-svn-id: svn://kolibrios.org@812 a494cfbc-eb01-0410-851d-a64ba20cac60 --- programs/system/drivers/ati2d/accel_2d.inc | 52 +++-- programs/system/drivers/ati2d/accel_3d.inc | 67 ++---- programs/system/drivers/ati2d/ati2d.h | 32 ++- programs/system/drivers/ati2d/microcode.h | 259 +++++++++++++++++++++ programs/system/drivers/ati2d/pci.c | 94 ++++++++ programs/system/drivers/ati2d/r500.inc | 44 +++- 6 files changed, 472 insertions(+), 76 deletions(-) diff --git a/programs/system/drivers/ati2d/accel_2d.inc b/programs/system/drivers/ati2d/accel_2d.inc index 6e8d11e0ba..6a79022d7b 100644 --- a/programs/system/drivers/ati2d/accel_2d.inc +++ b/programs/system/drivers/ati2d/accel_2d.inc @@ -1,6 +1,8 @@ #define BRUSH_MONO (0<<4) +#define R300_PIO + int DrawRect(draw_t* draw) { int x0, y0, x1, y1; @@ -25,6 +27,24 @@ int DrawRect(draw_t* draw) ifl = safe_cli(); + +#ifdef R300_PIO + + R5xxFIFOWait(7); + + OUTREG(R5XX_DP_GUI_MASTER_CNTL, rhd.gui_control | R5XX_ROP3_P | + R5XX_GMC_BRUSH_SOLID_COLOR | + R5XX_GMC_SRC_DATATYPE_COLOR); + + OUTREG(R5XX_DP_BRUSH_FRGD_CLR, draw->color); + OUTREG(R5XX_DP_WRITE_MASK, 0xFFFFFFFF); + OUTREG(R5XX_DP_CNTL, R5XX_DST_X_LEFT_TO_RIGHT | R5XX_DST_Y_TOP_TO_BOTTOM); + OUTREG(R5XX_DST_PITCH_OFFSET, rhd.dst_pitch_offset); + OUTREG(R5XX_DST_Y_X,(y0<<16)|x0); + OUTREG( R5XX_DST_WIDTH_HEIGHT,(w<<16)|h); + +#else + BEGIN_RING(); OUT_RING(CP_PACKET3(RADEON_CNTL_PAINT_MULTI, 4)); @@ -41,25 +61,8 @@ int DrawRect(draw_t* draw) OUT_RING((w<<16)|h); COMMIT_RING(); -/* -#if 1 - -#else - - R5xxFIFOWait(7); - - OUTREG(R5XX_DP_GUI_MASTER_CNTL, rhd.gui_control | R5XX_ROP3_P | - R5XX_GMC_BRUSH_SOLID_COLOR | - R5XX_GMC_SRC_DATATYPE_COLOR); - - OUTREG(R5XX_DP_BRUSH_FRGD_CLR, draw->color); - OUTREG(R5XX_DP_WRITE_MASK, 0xFFFFFFFF); - OUTREG(R5XX_DP_CNTL, R5XX_DST_X_LEFT_TO_RIGHT | R5XX_DST_Y_TOP_TO_BOTTOM); - OUTREG(R5XX_DST_PITCH_OFFSET, rhd.dst_pitch_offset); - OUTREG(R5XX_DST_Y_X,(y0<<16)|x0); - OUTREG( R5XX_DST_WIDTH_HEIGHT,(w<<16)|h); #endif -*/ + safe_sti(ifl); } ; return 0; @@ -85,6 +88,10 @@ int FillRect(fill_t *fill) ifl = safe_cli(); +#ifdef R300_PIO + +#else + BEGIN_RING(); OUT_RING(CP_PACKET3(RADEON_CNTL_PAINT, 7)); OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL | @@ -104,6 +111,8 @@ int FillRect(fill_t *fill) OUT_RING((y1<<16)|x1); COMMIT_RING(); +#endif + safe_sti(ifl); }; return 0; @@ -131,6 +140,11 @@ int Blit(blit_t *blit) ifl = safe_cli(); +#ifdef R300_PIO + + +#else + BEGIN_RING(); OUT_RING(CP_PACKET3(RADEON_CNTL_BITBLT, 5)); @@ -150,6 +164,8 @@ int Blit(blit_t *blit) OUT_RING((w<<16)|h); COMMIT_RING(); +#endif + safe_sti(ifl); } ; return 0; diff --git a/programs/system/drivers/ati2d/accel_3d.inc b/programs/system/drivers/ati2d/accel_3d.inc index 9b820f49e7..c58f976d70 100644 --- a/programs/system/drivers/ati2d/accel_3d.inc +++ b/programs/system/drivers/ati2d/accel_3d.inc @@ -10,45 +10,6 @@ #define IS_R300_3D 0 #define IS_R500_3D 1 -typedef enum { - CHIP_FAMILY_UNKNOW, - CHIP_FAMILY_LEGACY, - CHIP_FAMILY_RADEON, - CHIP_FAMILY_RV100, - CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/ - CHIP_FAMILY_RV200, - CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), RS250 (IGP 7000) */ - CHIP_FAMILY_R200, - CHIP_FAMILY_RV250, - CHIP_FAMILY_RS300, /* RS300/RS350 */ - CHIP_FAMILY_RV280, - CHIP_FAMILY_R300, - CHIP_FAMILY_R350, - CHIP_FAMILY_RV350, - CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */ - CHIP_FAMILY_R420, /* R420/R423/M18 */ - CHIP_FAMILY_RV410, /* RV410, M26 */ - CHIP_FAMILY_RS400, /* xpress 200, 200m (RS400) Intel */ - CHIP_FAMILY_RS480, /* xpress 200, 200m (RS410/480/482/485) AMD */ - CHIP_FAMILY_RV515, /* rv515 */ - CHIP_FAMILY_R520, /* r520 */ - CHIP_FAMILY_RV530, /* rv530 */ - CHIP_FAMILY_R580, /* r580 */ - CHIP_FAMILY_RV560, /* rv560 */ - CHIP_FAMILY_RV570, /* rv570 */ - CHIP_FAMILY_RS600, - CHIP_FAMILY_RS690, - CHIP_FAMILY_RS740, - CHIP_FAMILY_R600, /* r600 */ - CHIP_FAMILY_R630, - CHIP_FAMILY_RV610, - CHIP_FAMILY_RV630, - CHIP_FAMILY_RV670, - CHIP_FAMILY_RV620, - CHIP_FAMILY_RV635, - CHIP_FAMILY_RS780, - CHIP_FAMILY_LAST -} RADEONChipFamily; static void Init3DEngine(RHDPtr rhdPtr) { @@ -155,16 +116,16 @@ static void Init3DEngine(RHDPtr rhdPtr) (5 << R300_PVS_NUM_CNTLRS_SHIFT) | (5 << R300_VF_MAX_VTX_NUM_SHIFT)); - if (rhdPtr->ChipSet == CHIP_FAMILY_RV515) + if (rhdPtr->ChipSet == RHD_FAMILY_RV515) vap_cntl |= (2 << R300_PVS_NUM_FPUS_SHIFT); - else if ((rhdPtr->ChipSet == CHIP_FAMILY_RV530) || - (rhdPtr->ChipSet == CHIP_FAMILY_RV560)) + else if ((rhdPtr->ChipSet == RHD_FAMILY_RV530) || + (rhdPtr->ChipSet == RHD_FAMILY_RV560)) vap_cntl |= (5 << R300_PVS_NUM_FPUS_SHIFT); - else if (rhdPtr->ChipSet == CHIP_FAMILY_R420) + else if (rhdPtr->ChipSet == RHD_FAMILY_R420) vap_cntl |= (6 << R300_PVS_NUM_FPUS_SHIFT); - else if ((rhdPtr->ChipSet == CHIP_FAMILY_R520) || - (rhdPtr->ChipSet == CHIP_FAMILY_R580) || - (rhdPtr->ChipSet == CHIP_FAMILY_RV570)) + else if ((rhdPtr->ChipSet == RHD_FAMILY_R520) || + (rhdPtr->ChipSet == RHD_FAMILY_R580) || + (rhdPtr->ChipSet == RHD_FAMILY_RV570)) vap_cntl |= (8 << R300_PVS_NUM_FPUS_SHIFT); else vap_cntl |= (4 << R300_PVS_NUM_FPUS_SHIFT); @@ -605,13 +566,13 @@ static void Init3DEngine(RHDPtr rhdPtr) OUT_ACCEL_REG(R300_SC_CLIP_RULE, 0xAAAA); OUT_ACCEL_REG(R300_SC_SCREENDOOR, 0xffffff); FINISH_ACCEL(); - } else if ((rhdPtr->ChipSet == CHIP_FAMILY_RV250) || - (rhdPtr->ChipSet == CHIP_FAMILY_RV280) || - (rhdPtr->ChipSet == CHIP_FAMILY_RS300) || - (rhdPtr->ChipSet == CHIP_FAMILY_R200)) { + } else if ((rhdPtr->ChipSet == RHD_FAMILY_RV250) || + (rhdPtr->ChipSet == RHD_FAMILY_RV280) || + (rhdPtr->ChipSet == RHD_FAMILY_RS300) || + (rhdPtr->ChipSet == RHD_FAMILY_R200)) { BEGIN_ACCEL(7); - if (rhdPtr->ChipSet == CHIP_FAMILY_RS300) { + if (rhdPtr->ChipSet == RHD_FAMILY_RS300) { OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, RADEON_TCL_BYPASS); } else { OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, 0); @@ -639,8 +600,8 @@ static void Init3DEngine(RHDPtr rhdPtr) FINISH_ACCEL(); } else { BEGIN_ACCEL(2); - if ((rhdPtr->ChipSet == CHIP_FAMILY_RADEON) || - (rhdPtr->ChipSet == CHIP_FAMILY_RV200)) + if ((rhdPtr->ChipSet == RHD_FAMILY_RADEON) || + (rhdPtr->ChipSet == RHD_FAMILY_RV200)) OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, 0); else OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, RADEON_TCL_BYPASS); diff --git a/programs/system/drivers/ati2d/ati2d.h b/programs/system/drivers/ati2d/ati2d.h index 96379acbc2..b45f863510 100644 --- a/programs/system/drivers/ati2d/ati2d.h +++ b/programs/system/drivers/ati2d/ati2d.h @@ -3,6 +3,11 @@ enum RHD_CHIPSETS { RHD_UNKNOWN = 0, + RHD_R300, + RHD_R350, + RHD_RV350, + RHD_RV370, + RHD_RV380, /* R500 */ RHD_RV505, RHD_RV515, @@ -43,11 +48,33 @@ enum RHD_CHIPSETS { RHD_M82, RHD_RV635, RHD_M86, + RHD_RS780, RHD_CHIP_END }; enum RHD_FAMILIES { RHD_FAMILY_UNKNOWN = 0, + + RHD_FAMILY_RADEON, + + RHD_FAMILY_RV100, + RHD_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/ + RHD_FAMILY_RV200, + RHD_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), RS250 (IGP 7000) */ + RHD_FAMILY_R200, + RHD_FAMILY_RV250, + RHD_FAMILY_RS300, /* RS300/RS350 */ + RHD_FAMILY_RV280, + + RHD_FAMILY_R300, + RHD_FAMILY_R350, + RHD_FAMILY_RV350, + RHD_FAMILY_RV380, /* RV370/RV380/M22/M24 */ + RHD_FAMILY_R420, /* R420/R423/M18 */ + RHD_FAMILY_RV410, /* RV410, M26 */ + RHD_FAMILY_RS400, /* xpress 200, 200m (RS400) Intel */ + RHD_FAMILY_RS480, /* xpress 200, 200m (RS410/480/482/485) AMD */ + RHD_FAMILY_RV515, RHD_FAMILY_R520, RHD_FAMILY_RV530, @@ -60,7 +87,8 @@ enum RHD_FAMILIES { RHD_FAMILY_RV630, RHD_FAMILY_RV670, RHD_FAMILY_RV620, - RHD_FAMILY_RV635 + RHD_FAMILY_RV635, + RHD_FAMILY_RS780 }; #define RHD_FB_BAR 0 @@ -88,6 +116,8 @@ typedef struct RHDRec unsigned int FbScanoutSize; enum RHD_CHIPSETS ChipSet; + enum RHD_FAMILIES ChipFamily; + char *ChipName; Bool IsIGP; diff --git a/programs/system/drivers/ati2d/microcode.h b/programs/system/drivers/ati2d/microcode.h index 2d6eb96158..98bf666817 100644 --- a/programs/system/drivers/ati2d/microcode.h +++ b/programs/system/drivers/ati2d/microcode.h @@ -1,4 +1,263 @@ +static const u32 R300_cp_microcode[][2]={ + { 0x4200e000, 0000000000 }, + { 0x4000e000, 0000000000 }, + { 0x000000ae, 0x00000008 }, + { 0x000000b2, 0x00000008 }, + { 0x67554b4a, 0000000000 }, + { 0x4a4a4475, 0000000000 }, + { 0x55527d83, 0000000000 }, + { 0x4a8c8b65, 0000000000 }, + { 0x4aef4af6, 0000000000 }, + { 0x4ae14a4a, 0000000000 }, + { 0xe4979797, 0000000000 }, + { 0xdb4aebdd, 0000000000 }, + { 0x9ccc4a4a, 0000000000 }, + { 0xd1989898, 0000000000 }, + { 0x4a0f9ad6, 0000000000 }, + { 0x000ca000, 0x00000004 }, + { 0x000d0012, 0x00000038 }, + { 0x0000e8b4, 0x00000004 }, + { 0x000d0014, 0x00000038 }, + { 0x0000e8b6, 0x00000004 }, + { 0x000d0016, 0x00000038 }, + { 0x0000e854, 0x00000004 }, + { 0x000d0018, 0x00000038 }, + { 0x0000e855, 0x00000004 }, + { 0x000d001a, 0x00000038 }, + { 0x0000e856, 0x00000004 }, + { 0x000d001c, 0x00000038 }, + { 0x0000e857, 0x00000004 }, + { 0x000d001e, 0x00000038 }, + { 0x0000e824, 0x00000004 }, + { 0x000d0020, 0x00000038 }, + { 0x0000e825, 0x00000004 }, + { 0x000d0022, 0x00000038 }, + { 0x0000e830, 0x00000004 }, + { 0x000d0024, 0x00000038 }, + { 0x0000f0c0, 0x00000004 }, + { 0x000d0026, 0x00000038 }, + { 0x0000f0c1, 0x00000004 }, + { 0x000d0028, 0x00000038 }, + { 0x0000f041, 0x00000004 }, + { 0x000d002a, 0x00000038 }, + { 0x0000f184, 0x00000004 }, + { 0x000d002c, 0x00000038 }, + { 0x0000f185, 0x00000004 }, + { 0x000d002e, 0x00000038 }, + { 0x0000f186, 0x00000004 }, + { 0x000d0030, 0x00000038 }, + { 0x0000f187, 0x00000004 }, + { 0x000d0032, 0x00000038 }, + { 0x0000f180, 0x00000004 }, + { 0x000d0034, 0x00000038 }, + { 0x0000f393, 0x00000004 }, + { 0x000d0036, 0x00000038 }, + { 0x0000f38a, 0x00000004 }, + { 0x000d0038, 0x00000038 }, + { 0x0000f38e, 0x00000004 }, + { 0x0000e821, 0x00000004 }, + { 0x0140a000, 0x00000004 }, + { 0x00000043, 0x00000018 }, + { 0x00cce800, 0x00000004 }, + { 0x001b0001, 0x00000004 }, + { 0x08004800, 0x00000004 }, + { 0x001b0001, 0x00000004 }, + { 0x08004800, 0x00000004 }, + { 0x001b0001, 0x00000004 }, + { 0x08004800, 0x00000004 }, + { 0x0000003a, 0x00000008 }, + { 0x0000a000, 0000000000 }, + { 0x2000451d, 0x00000004 }, + { 0x0000e580, 0x00000004 }, + { 0x000ce581, 0x00000004 }, + { 0x08004580, 0x00000004 }, + { 0x000ce581, 0x00000004 }, + { 0x00000047, 0x00000008 }, + { 0x0000a000, 0000000000 }, + { 0x000c2000, 0x00000004 }, + { 0x0000e50e, 0x00000004 }, + { 0x00032000, 0x00000004 }, + { 0x00022051, 0x00000028 }, + { 0x00000051, 0x00000024 }, + { 0x0800450f, 0x00000004 }, + { 0x0000a04b, 0x00000008 }, + { 0x0000e565, 0x00000004 }, + { 0x0000e566, 0x00000004 }, + { 0x00000052, 0x00000008 }, + { 0x03cca5b4, 0x00000004 }, + { 0x05432000, 0x00000004 }, + { 0x00022000, 0x00000004 }, + { 0x4ccce05e, 0x00000030 }, + { 0x08274565, 0x00000004 }, + { 0x0000005e, 0x00000030 }, + { 0x08004564, 0x00000004 }, + { 0x0000e566, 0x00000004 }, + { 0x00000055, 0x00000008 }, + { 0x00802061, 0x00000010 }, + { 0x00202000, 0x00000004 }, + { 0x001b00ff, 0x00000004 }, + { 0x01000064, 0x00000010 }, + { 0x001f2000, 0x00000004 }, + { 0x001c00ff, 0x00000004 }, + { 0000000000, 0x0000000c }, + { 0x00000080, 0x00000030 }, + { 0x00000055, 0x00000008 }, + { 0x0000e576, 0x00000004 }, + { 0x000ca000, 0x00000004 }, + { 0x00012000, 0x00000004 }, + { 0x00082000, 0x00000004 }, + { 0x1800650e, 0x00000004 }, + { 0x00092000, 0x00000004 }, + { 0x000a2000, 0x00000004 }, + { 0x000f0000, 0x00000004 }, + { 0x00400000, 0x00000004 }, + { 0x00000074, 0x00000018 }, + { 0x0000e563, 0x00000004 }, + { 0x00c0e5f9, 0x000000c2 }, + { 0x00000069, 0x00000008 }, + { 0x0000a069, 0x00000008 }, + { 0x0000e576, 0x00000004 }, + { 0x0000e577, 0x00000004 }, + { 0x0000e50e, 0x00000004 }, + { 0x0000e50f, 0x00000004 }, + { 0x0140a000, 0x00000004 }, + { 0x00000077, 0x00000018 }, + { 0x00c0e5f9, 0x000000c2 }, + { 0x00000077, 0x00000008 }, + { 0x0014e50e, 0x00000004 }, + { 0x0040e50f, 0x00000004 }, + { 0x00c0007a, 0x00000008 }, + { 0x0000e570, 0x00000004 }, + { 0x0000e571, 0x00000004 }, + { 0x0000e572, 0x0000000c }, + { 0x0000a000, 0x00000004 }, + { 0x0140a000, 0x00000004 }, + { 0x0000e568, 0x00000004 }, + { 0x000c2000, 0x00000004 }, + { 0x00000084, 0x00000018 }, + { 0x000b0000, 0x00000004 }, + { 0x18c0e562, 0x00000004 }, + { 0x00000086, 0x00000008 }, + { 0x00c00085, 0x00000008 }, + { 0x000700e3, 0x00000004 }, + { 0x00000092, 0x00000038 }, + { 0x000ca094, 0x00000030 }, + { 0x080045bb, 0x00000004 }, + { 0x000c2095, 0x00000030 }, + { 0x0800e5bc, 0000000000 }, + { 0x0000e5bb, 0x00000004 }, + { 0x0000e5bc, 0000000000 }, + { 0x00120000, 0x0000000c }, + { 0x00120000, 0x00000004 }, + { 0x001b0002, 0x0000000c }, + { 0x0000a000, 0x00000004 }, + { 0x0000e821, 0x00000004 }, + { 0x0000e800, 0000000000 }, + { 0x0000e821, 0x00000004 }, + { 0x0000e82e, 0000000000 }, + { 0x02cca000, 0x00000004 }, + { 0x00140000, 0x00000004 }, + { 0x000ce1cc, 0x00000004 }, + { 0x050de1cd, 0x00000004 }, + { 0x00400000, 0x00000004 }, + { 0x000000a4, 0x00000018 }, + { 0x00c0a000, 0x00000004 }, + { 0x000000a1, 0x00000008 }, + { 0x000000a6, 0x00000020 }, + { 0x4200e000, 0000000000 }, + { 0x000000ad, 0x00000038 }, + { 0x000ca000, 0x00000004 }, + { 0x00140000, 0x00000004 }, + { 0x000c2000, 0x00000004 }, + { 0x00160000, 0x00000004 }, + { 0x700ce000, 0x00000004 }, + { 0x001400a9, 0x00000008 }, + { 0x4000e000, 0000000000 }, + { 0x02400000, 0x00000004 }, + { 0x400ee000, 0x00000004 }, + { 0x02400000, 0x00000004 }, + { 0x4000e000, 0000000000 }, + { 0x000c2000, 0x00000004 }, + { 0x0240e51b, 0x00000004 }, + { 0x0080e50a, 0x00000005 }, + { 0x0080e50b, 0x00000005 }, + { 0x00220000, 0x00000004 }, + { 0x000700e3, 0x00000004 }, + { 0x000000c0, 0x00000038 }, + { 0x000c2095, 0x00000030 }, + { 0x0880e5bd, 0x00000005 }, + { 0x000c2094, 0x00000030 }, + { 0x0800e5bb, 0x00000005 }, + { 0x000c2095, 0x00000030 }, + { 0x0880e5bc, 0x00000005 }, + { 0x000000c3, 0x00000008 }, + { 0x0080e5bd, 0x00000005 }, + { 0x0000e5bb, 0x00000005 }, + { 0x0080e5bc, 0x00000005 }, + { 0x00210000, 0x00000004 }, + { 0x02800000, 0x00000004 }, + { 0x00c000c7, 0x00000018 }, + { 0x4180e000, 0x00000040 }, + { 0x000000c9, 0x00000024 }, + { 0x01000000, 0x0000000c }, + { 0x0100e51d, 0x0000000c }, + { 0x000045bb, 0x00000004 }, + { 0x000080c3, 0x00000008 }, + { 0x0000f3ce, 0x00000004 }, + { 0x0140a000, 0x00000004 }, + { 0x00cc2000, 0x00000004 }, + { 0x08c053cf, 0x00000040 }, + { 0x00008000, 0000000000 }, + { 0x0000f3d2, 0x00000004 }, + { 0x0140a000, 0x00000004 }, + { 0x00cc2000, 0x00000004 }, + { 0x08c053d3, 0x00000040 }, + { 0x00008000, 0000000000 }, + { 0x0000f39d, 0x00000004 }, + { 0x0140a000, 0x00000004 }, + { 0x00cc2000, 0x00000004 }, + { 0x08c0539e, 0x00000040 }, + { 0x00008000, 0000000000 }, + { 0x03c00830, 0x00000004 }, + { 0x4200e000, 0000000000 }, + { 0x0000a000, 0x00000004 }, + { 0x200045e0, 0x00000004 }, + { 0x0000e5e1, 0000000000 }, + { 0x00000001, 0000000000 }, + { 0x000700e0, 0x00000004 }, + { 0x0800e394, 0000000000 }, + { 0000000000, 0000000000 }, + { 0x0000e8c4, 0x00000004 }, + { 0x0000e8c5, 0x00000004 }, + { 0x0000e8c6, 0x00000004 }, + { 0x0000e928, 0x00000004 }, + { 0x0000e929, 0x00000004 }, + { 0x0000e92a, 0x00000004 }, + { 0x000000e4, 0x00000008 }, + { 0x0000e928, 0x00000004 }, + { 0x0000e929, 0x00000004 }, + { 0x0000e92a, 0x00000004 }, + { 0x000000eb, 0x00000008 }, + { 0x02c02000, 0x00000004 }, + { 0x00060000, 0x00000004 }, + { 0x000000f3, 0x00000034 }, + { 0x000000f0, 0x00000008 }, + { 0x00008000, 0x00000004 }, + { 0xc000e000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0x000c2000, 0x00000004 }, + { 0x001d0018, 0x00000004 }, + { 0x001a0001, 0x00000004 }, + { 0x000000fb, 0x00000034 }, + { 0x0000004a, 0x00000008 }, + { 0x0500a04a, 0x00000008 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, +}; + static const u32 R520_cp_microcode[][2]={ { 0x4200e000, 0000000000 }, { 0x4000e000, 0000000000 }, diff --git a/programs/system/drivers/ati2d/pci.c b/programs/system/drivers/ati2d/pci.c index cd5ad7295c..2b1c83115d 100644 --- a/programs/system/drivers/ati2d/pci.c +++ b/programs/system/drivers/ati2d/pci.c @@ -41,11 +41,105 @@ SymTabRec RHDChipsets[] = { { -1, NULL } }; + + +static struct rhdChipsetMapStruct { + enum RHD_FAMILIES family; + Bool IGP; +} rhdChipsetMap[] = { + { RHD_FAMILY_UNKNOWN, 0 }, /* RHD_UNKNOWN */ + + { RHD_FAMILY_R300, 0 }, /* RHD_R300 */ + { RHD_FAMILY_R350, 0 }, /* RHD_R350 */ + { RHD_FAMILY_RV350, 0 }, /* RHD_RV350 */ + { RHD_FAMILY_RV380, 0 }, /* RHD_RV370 */ + { RHD_FAMILY_RV380, 0 }, /* RHD_RV380 */ + + + { RHD_FAMILY_RV515, 0 }, /* RHD_RV505 */ + { RHD_FAMILY_RV515, 0 }, /* RHD_RV515 */ + { RHD_FAMILY_RV515, 0 }, /* RHD_RV516 */ + { RHD_FAMILY_R520, 0 }, /* RHD_R520 */ + { RHD_FAMILY_RV530, 0 }, /* RHD_RV530 */ + { RHD_FAMILY_RV530, 0 }, /* RHD_RV535 */ + { RHD_FAMILY_RV515, 0 }, /* RHD_RV550 */ + { RHD_FAMILY_RV560, 0 }, /* RHD_RV560 */ + { RHD_FAMILY_RV570, 0 }, /* RHD_RV570 */ + { RHD_FAMILY_R580, 0 }, /* RHD_R580 */ + { RHD_FAMILY_RV515, 0 }, /* RHD_M52 */ + { RHD_FAMILY_RV515, 0 }, /* RHD_M54 */ + { RHD_FAMILY_RV530, 0 }, /* RHD_M56 */ + { RHD_FAMILY_R520, 0 }, /* RHD_M58 */ + { RHD_FAMILY_RV515, 0 }, /* RHD_M62 */ + { RHD_FAMILY_RV515, 0 }, /* RHD_M64 */ + { RHD_FAMILY_RV530, 0 }, /* RHD_M66 */ + { RHD_FAMILY_R580, 0 }, /* RHD_M68 */ + { RHD_FAMILY_RV515, 0 }, /* RHD_M71 */ + { RHD_FAMILY_RS690, 1 }, /* RHD_RS600 */ + { RHD_FAMILY_RS690, 1 }, /* RHD_RS690 */ + { RHD_FAMILY_RS690, 1 }, /* RHD_RS740 */ + { RHD_FAMILY_R600, 0 }, /* RHD_R600 */ + { RHD_FAMILY_RV610, 0 }, /* RHD_RV610 */ + { RHD_FAMILY_RV630, 0 }, /* RHD_RV630 */ + { RHD_FAMILY_RV610, 0 }, /* RHD_M72 */ + { RHD_FAMILY_RV610, 0 }, /* RHD_M74 */ + { RHD_FAMILY_RV630, 0 }, /* RHD_M76 */ + { RHD_FAMILY_RV670, 0 }, /* RHD_RV670 */ + { RHD_FAMILY_RV670, 0 }, /* RHD_R680 */ + { RHD_FAMILY_RV620, 0 }, /* RHD_RV620 */ + { RHD_FAMILY_RV620, 0 }, /* RHD_M82 */ + { RHD_FAMILY_RV635, 0 }, /* RHD_RV635 */ + { RHD_FAMILY_UNKNOWN, 0 }, /* RHD_M86 */ + { RHD_FAMILY_RS780, 1 } /* RHD_RS780 */ + /* RHD_CHIP_END */ +}; + + # define RHD_DEVICE_MATCH(d, i) { (d),(i) } # define PCI_ID_LIST PciChipset_t RHDPCIchipsets[] # define LIST_END { 0, 0} const PCI_ID_LIST = { + + RHD_DEVICE_MATCH( 0x4144, RHD_R300 ), /* ATI Radeon 9500 */ + RHD_DEVICE_MATCH( 0x4145, RHD_R300 ), /* ATI Radeon 9500 */ + RHD_DEVICE_MATCH( 0x4146, RHD_R300 ), /* ATI Radeon 9600TX */ + RHD_DEVICE_MATCH( 0x4147, RHD_R300 ), /* ATI FireGL Z1 */ + RHD_DEVICE_MATCH( 0x4148, RHD_R350 ), /* ATI Radeon 9800SE */ + RHD_DEVICE_MATCH( 0x4149, RHD_R350 ), /* ATI Radeon 9800 */ + RHD_DEVICE_MATCH( 0x414A, RHD_R350 ), /* ATI Radeon 9800 */ + RHD_DEVICE_MATCH( 0x414B, RHD_R350 ), /* ATI FireGL X2 */ + + RHD_DEVICE_MATCH( 0x4150, RHD_RV350 ), /* ATI Radeon 9600 */ + RHD_DEVICE_MATCH( 0x4151, RHD_RV350 ), /* ATI Radeon 9600SE */ + RHD_DEVICE_MATCH( 0x4152, RHD_RV350 ), /* ATI Radeon 9600XT */ + RHD_DEVICE_MATCH( 0x4153, RHD_RV350 ), /* ATI Radeon 9600 */ + RHD_DEVICE_MATCH( 0x4154, RHD_RV350 ), /* ATI FireGL T2 */ + RHD_DEVICE_MATCH( 0x4155, RHD_RV350 ), /* ATI Radeon 9650 */ + RHD_DEVICE_MATCH( 0x4156, RHD_RV350 ), /* ATI FireGL RV360 */ + + RHD_DEVICE_MATCH( 0x4E44, RHD_R300 ), + RHD_DEVICE_MATCH( 0x4E45, RHD_R300 ), + RHD_DEVICE_MATCH( 0x4E46, RHD_R300 ), + RHD_DEVICE_MATCH( 0x4E47, RHD_R300 ), + RHD_DEVICE_MATCH( 0x4E48, RHD_R350 ), + RHD_DEVICE_MATCH( 0x4E49, RHD_R350 ), + RHD_DEVICE_MATCH( 0x4E4A, RHD_R350 ), + RHD_DEVICE_MATCH( 0x4E4B, RHD_R350 ), + RHD_DEVICE_MATCH( 0x4E50, RHD_RV350 ), + RHD_DEVICE_MATCH( 0x4E51, RHD_RV350 ), + RHD_DEVICE_MATCH( 0x4E52, RHD_RV350 ), + RHD_DEVICE_MATCH( 0x4E53, RHD_RV350 ), + RHD_DEVICE_MATCH( 0x4E54, RHD_RV350 ), + RHD_DEVICE_MATCH( 0x4E56, RHD_RV350 ), + + + RHD_DEVICE_MATCH( 0x5B60, RHD_RV380 ), + RHD_DEVICE_MATCH( 0x5B62, RHD_RV380 ), + RHD_DEVICE_MATCH( 0x5B63, RHD_RV380 ), + RHD_DEVICE_MATCH( 0x5B64, RHD_RV380 ), + RHD_DEVICE_MATCH( 0x5B65, RHD_RV380 ), + RHD_DEVICE_MATCH( 0x7100, RHD_R520 ), /* Radeon X1800 */ RHD_DEVICE_MATCH( 0x7101, RHD_M58 ), /* Mobility Radeon X1800 XT */ RHD_DEVICE_MATCH( 0x7102, RHD_M58 ), /* Mobility Radeon X1800 */ diff --git a/programs/system/drivers/ati2d/r500.inc b/programs/system/drivers/ati2d/r500.inc index 9214acc8be..8441a39b7c 100644 --- a/programs/system/drivers/ati2d/r500.inc +++ b/programs/system/drivers/ati2d/r500.inc @@ -1,4 +1,6 @@ +#define R300_TEST + #include "r5xx_regs.h" #define RADEON_BUS_CNTL 0x0030 @@ -219,12 +221,41 @@ static void load_microcode() ifl = safe_cli(); - R5xx2DIdleLocal(); OUTREG(RADEON_CP_ME_RAM_ADDR,0); - for (i = 0; i < 256; i++) + + R5xx2DIdleLocal(); + + switch(rhd.ChipSet) { - OUTREG(RADEON_CP_ME_RAM_DATAH, R520_cp_microcode[i][1]); - OUTREG(RADEON_CP_ME_RAM_DATAL, R520_cp_microcode[i][0]); + case RHD_R300: + case RHD_R350: + case RHD_RV350: + case RHD_RV370: + case RHD_RV380: + dbgprintf("Loading R300 microcode\n"); + for (i = 0; i < 256; i++) + { + OUTREG(RADEON_CP_ME_RAM_DATAH, R300_cp_microcode[i][1]); + OUTREG(RADEON_CP_ME_RAM_DATAL, R300_cp_microcode[i][0]); + } + break; + + case RHD_RV505: + case RHD_RV515: + case RHD_RV516: + case RHD_R520: + case RHD_RV530: + case RHD_RV535: + case RHD_RV550: + case RHD_RV560: + case RHD_RV570: + case RHD_R580: + dbgprintf("Loading R500 microcode\n"); + for (i = 0; i < 256; i++) + { + OUTREG(RADEON_CP_ME_RAM_DATAH, R520_cp_microcode[i][1]); + OUTREG(RADEON_CP_ME_RAM_DATAL, R520_cp_microcode[i][0]); + } } safe_sti(ifl); }; @@ -234,8 +265,13 @@ void R5xx2DInit() { u32 base; +#ifdef R300_TEST + rhd.displayWidth = 800; + rhd.displayHeight = 600; +#else rhd.displayWidth = INREG(D1GRPH_X_END); rhd.displayHeight = INREG(D1GRPH_Y_END); +#endif rhd.__xmin = 0; rhd.__ymin = 0;