Spaceraven/kolibrios
1
0
Fork 0
forked from KolibriOS/kolibrios
Code Pull Requests Activity

code cleanup

Browse Source 
git-svn-id: svn://kolibrios.org@1129 a494cfbc-eb01-0410-851d-a64ba20cac60
This commit is contained in:
Sergey Semyonov (Serge) 2009-07-14 08:26:48 +00:00
parent b8ff8d60ed
commit a0d587989d
14 changed files with 229 additions and 69 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/video/drm/include/types.h
View File

@ -225,11 +225,12 @@ static inline void *kcalloc(size_t n, size_t size, u32_t flags)
return kzalloc(n * size, 0); return kzalloc(n * size, 0);
} }
#define ENTRY() dbgprintf("entry %s\n",__FUNCTION__) #define ENTRY() dbgprintf("enter %s\n",__FUNCTION__)
#define LEAVE() dbgprintf("leave %s\n",__FUNCTION__) #define LEAVE() dbgprintf("leave %s\n",__FUNCTION__)
#define ALIGN(x,a) __ALIGN_MASK(x,(typeof(x))(a)-1) #define ALIGN(x,a) __ALIGN_MASK(x,(typeof(x))(a)-1)
#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) #define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask))
#define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159
#endif //__TYPES_H__ #endif //__TYPES_H__

3
drivers/video/drm/radeon/atombios_crtc.c
View File

@ -559,9 +559,6 @@ void radeon_atombios_init_crtc(struct drm_device *dev,
radeon_crtc->crtc_offset = radeon_crtc->crtc_offset =
AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
dbgprintf("done %s\n",__FUNCTION__);
} }
void radeon_init_disp_bw_avivo(struct drm_device *dev, void radeon_init_disp_bw_avivo(struct drm_device *dev,

5
drivers/video/drm/radeon/makefile
View File

@ -58,8 +58,13 @@ NAME_SRC= \
radeon_ring.c \ radeon_ring.c \
r100.c \ r100.c \
r300.c \ r300.c \
r420.c \
rv515.c \ rv515.c \
r520.c \ r520.c \
r600.c \
rs400.c \
rs600.c \
rs690.c \
radeon_fb.c radeon_fb.c

192
drivers/video/drm/radeon/r100.c
View File

@ -168,10 +168,10 @@ void r100_mc_setup(struct radeon_device *rdev)
uint32_t tmp; uint32_t tmp;
int r; int r;
// r = r100_debugfs_mc_info_init(rdev); r = r100_debugfs_mc_info_init(rdev);
// if (r) { if (r) {
// DRM_ERROR("Failed to register debugfs file for R100 MC !\n"); DRM_ERROR("Failed to register debugfs file for R100 MC !\n");
// } }
/* Write VRAM size in case we are limiting it */ /* Write VRAM size in case we are limiting it */
WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size); WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size);
tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1; tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1;
@ -206,9 +206,9 @@ int r100_mc_init(struct radeon_device *rdev)
{ {
int r; int r;
// if (r100_debugfs_rbbm_init(rdev)) { if (r100_debugfs_rbbm_init(rdev)) {
// DRM_ERROR("Failed to register debugfs file for RBBM !\n"); DRM_ERROR("Failed to register debugfs file for RBBM !\n");
// } }
r100_gpu_init(rdev); r100_gpu_init(rdev);
/* Disable gart which also disable out of gart access */ /* Disable gart which also disable out of gart access */
@ -495,11 +495,9 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
uint32_t tmp; uint32_t tmp;
int r; int r;
dbgprintf("%s\n",__FUNCTION__); if (r100_debugfs_cp_init(rdev)) {
DRM_ERROR("Failed to register debugfs file for CP !\n");
// if (r100_debugfs_cp_init(rdev)) { }
// DRM_ERROR("Failed to register debugfs file for CP !\n");
// }
/* Reset CP */ /* Reset CP */
tmp = RREG32(RADEON_CP_CSQ_STAT); tmp = RREG32(RADEON_CP_CSQ_STAT);
if ((tmp & (1 << 31))) { if ((tmp & (1 << 31))) {
@ -1377,3 +1375,173 @@ int r100_init(struct radeon_device *rdev)
return 0; return 0;
} }
/*
* Debugfs info
*/
#if defined(CONFIG_DEBUG_FS)
static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
{
struct drm_info_node *node = (struct drm_info_node *) m->private;
struct drm_device *dev = node->minor->dev;
struct radeon_device *rdev = dev->dev_private;
uint32_t reg, value;
unsigned i;
seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
for (i = 0; i < 64; i++) {
WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
}
return 0;
}
static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
{
struct drm_info_node *node = (struct drm_info_node *) m->private;
struct drm_device *dev = node->minor->dev;
struct radeon_device *rdev = dev->dev_private;
uint32_t rdp, wdp;
unsigned count, i, j;
radeon_ring_free_size(rdev);
rdp = RREG32(RADEON_CP_RB_RPTR);
wdp = RREG32(RADEON_CP_RB_WPTR);
count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
seq_printf(m, "%u dwords in ring\n", count);
for (j = 0; j <= count; j++) {
i = (rdp + j) & rdev->cp.ptr_mask;
seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
}
return 0;
}
static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
{
struct drm_info_node *node = (struct drm_info_node *) m->private;
struct drm_device *dev = node->minor->dev;
struct radeon_device *rdev = dev->dev_private;
uint32_t csq_stat, csq2_stat, tmp;
unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
unsigned i;
seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
csq_stat = RREG32(RADEON_CP_CSQ_STAT);
csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
r_rptr = (csq_stat >> 0) & 0x3ff;
r_wptr = (csq_stat >> 10) & 0x3ff;
ib1_rptr = (csq_stat >> 20) & 0x3ff;
ib1_wptr = (csq2_stat >> 0) & 0x3ff;
ib2_rptr = (csq2_stat >> 10) & 0x3ff;
ib2_wptr = (csq2_stat >> 20) & 0x3ff;
seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
seq_printf(m, "Ring rptr %u\n", r_rptr);
seq_printf(m, "Ring wptr %u\n", r_wptr);
seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
/* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
* 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
seq_printf(m, "Ring fifo:\n");
for (i = 0; i < 256; i++) {
WREG32(RADEON_CP_CSQ_ADDR, i << 2);
tmp = RREG32(RADEON_CP_CSQ_DATA);
seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
}
seq_printf(m, "Indirect1 fifo:\n");
for (i = 256; i <= 512; i++) {
WREG32(RADEON_CP_CSQ_ADDR, i << 2);
tmp = RREG32(RADEON_CP_CSQ_DATA);
seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
}
seq_printf(m, "Indirect2 fifo:\n");
for (i = 640; i < ib1_wptr; i++) {
WREG32(RADEON_CP_CSQ_ADDR, i << 2);
tmp = RREG32(RADEON_CP_CSQ_DATA);
seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
}
return 0;
}
static int r100_debugfs_mc_info(struct seq_file *m, void *data)
{
struct drm_info_node *node = (struct drm_info_node *) m->private;
struct drm_device *dev = node->minor->dev;
struct radeon_device *rdev = dev->dev_private;
uint32_t tmp;
tmp = RREG32(RADEON_CONFIG_MEMSIZE);
seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
tmp = RREG32(RADEON_MC_FB_LOCATION);
seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
tmp = RREG32(RADEON_BUS_CNTL);
seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
tmp = RREG32(RADEON_MC_AGP_LOCATION);
seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
tmp = RREG32(RADEON_AGP_BASE);
seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
tmp = RREG32(RADEON_HOST_PATH_CNTL);
seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
tmp = RREG32(0x01D0);
seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
tmp = RREG32(RADEON_AIC_LO_ADDR);
seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
tmp = RREG32(RADEON_AIC_HI_ADDR);
seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
tmp = RREG32(0x01E4);
seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
return 0;
}
static struct drm_info_list r100_debugfs_rbbm_list[] = {
{"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
};
static struct drm_info_list r100_debugfs_cp_list[] = {
{"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
{"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
};
static struct drm_info_list r100_debugfs_mc_info_list[] = {
{"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
};
#endif
int r100_debugfs_rbbm_init(struct radeon_device *rdev)
{
#if defined(CONFIG_DEBUG_FS)
return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
#else
return 0;
#endif
}
int r100_debugfs_cp_init(struct radeon_device *rdev)
{
#if defined(CONFIG_DEBUG_FS)
return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
#else
return 0;
#endif
}
int r100_debugfs_mc_info_init(struct radeon_device *rdev)
{
#if defined(CONFIG_DEBUG_FS)
return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
#else
return 0;
#endif
}

14
drivers/video/drm/radeon/r300.c
View File

@ -95,10 +95,10 @@ int rv370_pcie_gart_enable(struct radeon_device *rdev)
if (r) { if (r) {
return r; return r;
} }
// r = rv370_debugfs_pcie_gart_info_init(rdev); r = rv370_debugfs_pcie_gart_info_init(rdev);
// if (r) { if (r) {
// DRM_ERROR("Failed to register debugfs file for PCIE gart !\n"); DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
// } }
rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
r = radeon_gart_table_vram_alloc(rdev); r = radeon_gart_table_vram_alloc(rdev);
if (r) { if (r) {
@ -184,9 +184,9 @@ int r300_mc_init(struct radeon_device *rdev)
{ {
int r; int r;
// if (r100_debugfs_rbbm_init(rdev)) { if (r100_debugfs_rbbm_init(rdev)) {
// DRM_ERROR("Failed to register debugfs file for RBBM !\n"); DRM_ERROR("Failed to register debugfs file for RBBM !\n");
// } }
r300_gpu_init(rdev); r300_gpu_init(rdev);
r100_pci_gart_disable(rdev); r100_pci_gart_disable(rdev);

22
drivers/video/drm/radeon/r520.c
View File

@ -57,15 +57,15 @@ int r520_mc_init(struct radeon_device *rdev)
dbgprintf("%s\n",__FUNCTION__); dbgprintf("%s\n",__FUNCTION__);
// if (r100_debugfs_rbbm_init(rdev)) { if (r100_debugfs_rbbm_init(rdev)) {
// DRM_ERROR("Failed to register debugfs file for RBBM !\n"); DRM_ERROR("Failed to register debugfs file for RBBM !\n");
// } }
// if (rv515_debugfs_pipes_info_init(rdev)) { if (rv515_debugfs_pipes_info_init(rdev)) {
// DRM_ERROR("Failed to register debugfs file for pipes !\n"); DRM_ERROR("Failed to register debugfs file for pipes !\n");
// } }
// if (rv515_debugfs_ga_info_init(rdev)) { if (rv515_debugfs_ga_info_init(rdev)) {
// DRM_ERROR("Failed to register debugfs file for pipes !\n"); DRM_ERROR("Failed to register debugfs file for pipes !\n");
// } }
r520_gpu_init(rdev); r520_gpu_init(rdev);
rv370_pcie_gart_disable(rdev); rv370_pcie_gart_disable(rdev);
@ -393,7 +393,3 @@ int radeon_fence_driver_init(struct radeon_device *rdev)
} }
//domodedovo 9-00 16/07/2009

9
drivers/video/drm/radeon/radeon_bios.c
View File

@ -58,7 +58,6 @@ static bool radeon_read_bios(struct radeon_device *rdev)
return true; return true;
} }
#if 0
static bool r700_read_disabled_bios(struct radeon_device *rdev) static bool r700_read_disabled_bios(struct radeon_device *rdev)
{ {
@ -354,8 +353,6 @@ static bool radeon_read_disabled_bios(struct radeon_device *rdev)
} }
#endif
bool radeon_get_bios(struct radeon_device *rdev) bool radeon_get_bios(struct radeon_device *rdev)
{ {
bool r; bool r;
@ -364,9 +361,9 @@ bool radeon_get_bios(struct radeon_device *rdev)
dbgprintf("%s\n\r",__FUNCTION__); dbgprintf("%s\n\r",__FUNCTION__);
r = radeon_read_bios(rdev); r = radeon_read_bios(rdev);
// if (r == false) { if (r == false) {
// r = radeon_read_disabled_bios(rdev); r = radeon_read_disabled_bios(rdev);
// } }
if (r == false || rdev->bios == NULL) { if (r == false || rdev->bios == NULL) {
DRM_ERROR("Unable to locate a BIOS ROM\n"); DRM_ERROR("Unable to locate a BIOS ROM\n");
rdev->bios = NULL; rdev->bios = NULL;

3
drivers/video/drm/radeon/radeon_connectors.c
View File

@ -351,9 +351,6 @@ struct drm_encoder *radeon_dvi_encoder(struct drm_connector *connector)
/* then check use digitial */ /* then check use digitial */
/* pick the first one */ /* pick the first one */
dbgprintf("enc_id = %x\n", enc_id);
if (enc_id) { if (enc_id) {
obj = drm_mode_object_find(connector->dev, enc_id, DRM_MODE_OBJECT_ENCODER); obj = drm_mode_object_find(connector->dev, enc_id, DRM_MODE_OBJECT_ENCODER);
if (!obj) if (!obj)

2
drivers/video/drm/radeon/radeon_device.c
View File

@ -575,7 +575,7 @@ int radeon_device_init(struct radeon_device *rdev,
if (rdev->is_atom_bios) { if (rdev->is_atom_bios) {
atom_asic_init(rdev->mode_info.atom_context); atom_asic_init(rdev->mode_info.atom_context);
} else { } else {
// radeon_combios_asic_init(rdev->ddev); radeon_combios_asic_init(rdev->ddev);
} }
} }
/* Get vram informations */ /* Get vram informations */

6
drivers/video/drm/radeon/radeon_ring.c
View File

@ -212,9 +212,9 @@ int radeon_ib_pool_init(struct radeon_device *rdev)
bitmap_zero(rdev->ib_pool.alloc_bm, RADEON_IB_POOL_SIZE); bitmap_zero(rdev->ib_pool.alloc_bm, RADEON_IB_POOL_SIZE);
rdev->ib_pool.ready = true; rdev->ib_pool.ready = true;
DRM_INFO("radeon: ib pool ready.\n"); DRM_INFO("radeon: ib pool ready.\n");
// if (radeon_debugfs_ib_init(rdev)) { if (radeon_debugfs_ib_init(rdev)) {
// DRM_ERROR("Failed to register debugfs file for IB !\n"); DRM_ERROR("Failed to register debugfs file for IB !\n");
// } }
return r; return r;
} }

6
drivers/video/drm/radeon/rs400.c
View File

@ -217,9 +217,9 @@ int rs400_mc_init(struct radeon_device *rdev)
uint32_t tmp; uint32_t tmp;
int r; int r;
// if (r100_debugfs_rbbm_init(rdev)) { if (r100_debugfs_rbbm_init(rdev)) {
// DRM_ERROR("Failed to register debugfs file for RBBM !\n"); DRM_ERROR("Failed to register debugfs file for RBBM !\n");
// } }
rs400_gpu_init(rdev); rs400_gpu_init(rdev);
rs400_gart_disable(rdev); rs400_gart_disable(rdev);

6
drivers/video/drm/radeon/rs600.c
View File

@ -194,9 +194,9 @@ int rs600_mc_init(struct radeon_device *rdev)
uint32_t tmp; uint32_t tmp;
int r; int r;
// if (r100_debugfs_rbbm_init(rdev)) { if (r100_debugfs_rbbm_init(rdev)) {
// DRM_ERROR("Failed to register debugfs file for RBBM !\n"); DRM_ERROR("Failed to register debugfs file for RBBM !\n");
// } }
rs600_gpu_init(rdev); rs600_gpu_init(rdev);
rs600_gart_disable(rdev); rs600_gart_disable(rdev);

6
drivers/video/drm/radeon/rs690.c
View File

@ -56,9 +56,9 @@ int rs690_mc_init(struct radeon_device *rdev)
uint32_t tmp; uint32_t tmp;
int r; int r;
// if (r100_debugfs_rbbm_init(rdev)) { if (r100_debugfs_rbbm_init(rdev)) {
// DRM_ERROR("Failed to register debugfs file for RBBM !\n"); DRM_ERROR("Failed to register debugfs file for RBBM !\n");
// } }
rs690_gpu_init(rdev); rs690_gpu_init(rdev);
rs400_gart_disable(rdev); rs400_gart_disable(rdev);

21
drivers/video/drm/radeon/rv515.c
View File

@ -60,15 +60,15 @@ int rv515_mc_init(struct radeon_device *rdev)
uint32_t tmp; uint32_t tmp;
int r; int r;
// if (r100_debugfs_rbbm_init(rdev)) { if (r100_debugfs_rbbm_init(rdev)) {
// DRM_ERROR("Failed to register debugfs file for RBBM !\n"); DRM_ERROR("Failed to register debugfs file for RBBM !\n");
// } }
// if (rv515_debugfs_pipes_info_init(rdev)) { if (rv515_debugfs_pipes_info_init(rdev)) {
// DRM_ERROR("Failed to register debugfs file for pipes !\n"); DRM_ERROR("Failed to register debugfs file for pipes !\n");
// } }
// if (rv515_debugfs_ga_info_init(rdev)) { if (rv515_debugfs_ga_info_init(rdev)) {
// DRM_ERROR("Failed to register debugfs file for pipes !\n"); DRM_ERROR("Failed to register debugfs file for pipes !\n");
// } }
rv515_gpu_init(rdev); rv515_gpu_init(rdev);
rv370_pcie_gart_disable(rdev); rv370_pcie_gart_disable(rdev);
@ -448,7 +448,7 @@ void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
(void)RREG32(RADEON_PCIE_DATA); (void)RREG32(RADEON_PCIE_DATA);
} }
#if 0
/* /*
* Debugfs info * Debugfs info
*/ */
@ -513,7 +513,6 @@ int rv515_debugfs_ga_info_init(struct radeon_device *rdev)
#endif #endif
} }
#endif
/* /*
* Asic initialization * Asic initialization