forked from KolibriOS/kolibrios
Bugfix in R6040 driver RX descriptors, cleanup.
git-svn-id: svn://kolibrios.org@4439 a494cfbc-eb01-0410-851d-a64ba20cac60
This commit is contained in:
hidnplayr
parent
4ebbeeff95
commit
c184a722c5
@ -1,6 +1,6 @@
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; ;;
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;; ;;
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;; Copyright (C) KolibriOS team 2004-2013. All rights reserved. ;;
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;; Copyright (C) KolibriOS team 2004-2014. All rights reserved. ;;
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;; Distributed under terms of the GNU General Public License ;;
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;; Distributed under terms of the GNU General Public License ;;
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;; ;;
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;; ;;
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;; R6040 driver for KolibriOS ;;
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;; R6040 driver for KolibriOS ;;
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@ -58,94 +58,106 @@ public version
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; Operational parameters that usually are not changed.
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; Operational parameters that usually are not changed.
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PHY1_ADDR = 1 ;For MAC1
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PHY1_ADDR = 1 ; For MAC1
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PHY2_ADDR = 3 ;For MAC2
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PHY2_ADDR = 3 ; For MAC2
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PHY_MODE = 0x3100 ;PHY CHIP Register 0
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PHY_MODE = 0x3100 ; PHY CHIP Register 0
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PHY_CAP = 0x01E1 ;PHY CHIP Register 4
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PHY_CAP = 0x01E1 ; PHY CHIP Register 4
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;**************************************************************************
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;**************************************************************************
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; RDC R6040 Register Definitions
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; RDC R6040 Register Definitions
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;**************************************************************************
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;**************************************************************************
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MCR0 = 0x00 ;Control register 0
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MCR1 = 0x01 ;Control register 1
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MAC_RST = 0x0001 ;Reset the MAC
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MBCR = 0x08 ;Bus control
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MT_ICR = 0x0C ;TX interrupt control
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MR_ICR = 0x10 ;RX interrupt control
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MTPR = 0x14 ;TX poll command register
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MR_BSR = 0x18 ;RX buffer size
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MR_DCR = 0x1A ;RX descriptor control
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MLSR = 0x1C ;Last status
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MMDIO = 0x20 ;MDIO control register
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MDIO_WRITE = 0x4000 ;MDIO write
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MDIO_READ = 0x2000 ;MDIO read
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MMRD = 0x24 ;MDIO read data register
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MMWD = 0x28 ;MDIO write data register
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MTD_SA0 = 0x2C ;TX descriptor start address 0
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MTD_SA1 = 0x30 ;TX descriptor start address 1
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MRD_SA0 = 0x34 ;RX descriptor start address 0
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MRD_SA1 = 0x38 ;RX descriptor start address 1
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MISR = 0x3C ;Status register
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MIER = 0x40 ;INT enable register
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MSK_INT = 0x0000 ;Mask off interrupts
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RX_FINISH = 0x0001 ;RX finished
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RX_NO_DESC = 0x0002 ;No RX descriptor available
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RX_FIFO_FULL = 0x0004 ;RX FIFO full
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RX_EARLY = 0x0008 ;RX early
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TX_FINISH = 0x0010 ;TX finished
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TX_EARLY = 0x0080 ;TX early
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EVENT_OVRFL = 0x0100 ;Event counter overflow
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LINK_CHANGED = 0x0200 ;PHY link changed
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ME_CISR = 0x44 ;Event counter INT status
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ME_CIER = 0x48 ;Event counter INT enable
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MR_CNT = 0x50 ;Successfully received packet counter
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ME_CNT0 = 0x52 ;Event counter 0
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ME_CNT1 = 0x54 ;Event counter 1
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ME_CNT2 = 0x56 ;Event counter 2
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ME_CNT3 = 0x58 ;Event counter 3
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MT_CNT = 0x5A ;Successfully transmit packet counter
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ME_CNT4 = 0x5C ;Event counter 4
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MP_CNT = 0x5E ;Pause frame counter register
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MAR0 = 0x60 ;Hash table 0
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MAR1 = 0x62 ;Hash table 1
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MAR2 = 0x64 ;Hash table 2
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MAR3 = 0x66 ;Hash table 3
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MID_0L = 0x68 ;Multicast address MID0 Low
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MID_0M = 0x6A ;Multicast address MID0 Medium
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MID_0H = 0x6C ;Multicast address MID0 High
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MID_1L = 0x70 ;MID1 Low
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MID_1M = 0x72 ;MID1 Medium
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MID_1H = 0x74 ;MID1 High
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MID_2L = 0x78 ;MID2 Low
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MID_2M = 0x7A ;MID2 Medium
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MID_2H = 0x7C ;MID2 High
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MID_3L = 0x80 ;MID3 Low
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MID_3M = 0x82 ;MID3 Medium
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MID_3H = 0x84 ;MID3 High
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PHY_CC = 0x88 ;PHY status change configuration register
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PHY_ST = 0x8A ;PHY status register
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MAC_SM = 0xAC ;MAC status machine
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MAC_ID = 0xBE ;Identifier register
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MAX_BUF_SIZE = 0x600 ;1536
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MCR0 = 0x00 ; Control register 0
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MCR0_RCVEN = 0x0002 ; Receive enable
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MCR0_PROMISC = 0x0020 ; Promiscuous mode
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MCR0_HASH_EN = 0x0100 ; Enable multicast hash table function
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MCR0_XMTEN = 0x1000 ; Transmission enable
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MCR0_FD = 0x8000 ; Full/Half Duplex mode
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MBCR_DEFAULT = 0x012A ;MAC Bus Control Register
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MCR1 = 0x01 ; Control register 1
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MCAST_MAX = 3 ;Max number multicast addresses to filter
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MAC_RST = 0x0001 ; Reset the MAC
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MBCR = 0x08 ; Bus control
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MT_ICR = 0x0C ; TX interrupt control
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MR_ICR = 0x10 ; RX interrupt control
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MTPR = 0x14 ; TX poll command register
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MR_BSR = 0x18 ; RX buffer size
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MR_DCR = 0x1A ; RX descriptor control
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MLSR = 0x1C ; Last status
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MMDIO = 0x20 ; MDIO control register
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MDIO_WRITE = 0x4000 ; MDIO write
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MDIO_READ = 0x2000 ; MDIO read
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MMRD = 0x24 ; MDIO read data register
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MMWD = 0x28 ; MDIO write data register
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MTD_SA0 = 0x2C ; TX descriptor start address 0
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MTD_SA1 = 0x30 ; TX descriptor start address 1
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MRD_SA0 = 0x34 ; RX descriptor start address 0
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MRD_SA1 = 0x38 ; RX descriptor start address 1
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MISR = 0x3C ; Status register
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MIER = 0x40 ; INT enable register
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MSK_INT = 0x0000 ; Mask off interrupts
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RX_FINISH = 0x0001 ; RX finished
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RX_NO_DESC = 0x0002 ; No RX descriptor available
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RX_FIFO_FULL = 0x0004 ; RX FIFO full
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RX_EARLY = 0x0008 ; RX early
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TX_FINISH = 0x0010 ; TX finished
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TX_EARLY = 0x0080 ; TX early
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EVENT_OVRFL = 0x0100 ; Event counter overflow
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LINK_CHANGED = 0x0200 ; PHY link changed
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ME_CISR = 0x44 ; Event counter INT status
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ME_CIER = 0x48 ; Event counter INT enable
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MR_CNT = 0x50 ; Successfully received packet counter
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ME_CNT0 = 0x52 ; Event counter 0
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ME_CNT1 = 0x54 ; Event counter 1
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ME_CNT2 = 0x56 ; Event counter 2
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ME_CNT3 = 0x58 ; Event counter 3
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MT_CNT = 0x5A ; Successfully transmit packet counter
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ME_CNT4 = 0x5C ; Event counter 4
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MP_CNT = 0x5E ; Pause frame counter register
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MAR0 = 0x60 ; Hash table 0
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MAR1 = 0x62 ; Hash table 1
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MAR2 = 0x64 ; Hash table 2
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MAR3 = 0x66 ; Hash table 3
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MID_0L = 0x68 ; Multicast address MID0 Low
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MID_0M = 0x6A ; Multicast address MID0 Medium
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MID_0H = 0x6C ; Multicast address MID0 High
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MID_1L = 0x70 ; MID1 Low
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MID_1M = 0x72 ; MID1 Medium
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MID_1H = 0x74 ; MID1 High
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MID_2L = 0x78 ; MID2 Low
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MID_2M = 0x7A ; MID2 Medium
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MID_2H = 0x7C ; MID2 High
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MID_3L = 0x80 ; MID3 Low
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MID_3M = 0x82 ; MID3 Medium
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MID_3H = 0x84 ; MID3 High
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PHY_CC = 0x88 ; PHY status change configuration register
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PHY_ST = 0x8A ; PHY status register
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MAC_SM = 0xAC ; MAC status machine
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MAC_ID = 0xBE ; Identifier register
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MAX_BUF_SIZE = 0x600 ; 1536
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MBCR_DEFAULT = 0x012A ; MAC Bus Control Register
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MCAST_MAX = 3 ; Max number multicast addresses to filter
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;Descriptor status
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;Descriptor status
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DSC_OWNER_MAC = 0x8000 ;MAC is the owner of this descriptor
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DSC_OWNER_MAC = 0x8000 ; MAC is the owner of this descriptor
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DSC_RX_OK = 0x4000 ;RX was successfull
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DSC_RX_OK = 0x4000 ; RX was successfull
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DSC_RX_ERR = 0x0800 ;RX PHY error
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DSC_RX_ERR = 0x0800 ; RX PHY error
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DSC_RX_ERR_DRI = 0x0400 ;RX dribble packet
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DSC_RX_ERR_DRI = 0x0400 ; RX dribble packet
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DSC_RX_ERR_BUF = 0x0200 ;RX length exceeds buffer size
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DSC_RX_ERR_BUF = 0x0200 ; RX length exceeds buffer size
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DSC_RX_ERR_LONG = 0x0100 ;RX length > maximum packet length
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DSC_RX_ERR_LONG = 0x0100 ; RX length > maximum packet length
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DSC_RX_ERR_RUNT = 0x0080 ;RX packet length < 64 byte
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DSC_RX_ERR_RUNT = 0x0080 ; RX packet length < 64 byte
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DSC_RX_ERR_CRC = 0x0040 ;RX CRC error
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DSC_RX_ERR_CRC = 0x0040 ; RX CRC error
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DSC_RX_BCAST = 0x0020 ;RX broadcast (no error)
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DSC_RX_BCAST = 0x0020 ; RX broadcast (no error)
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DSC_RX_MCAST = 0x0010 ;RX multicast (no error)
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DSC_RX_MCAST = 0x0010 ; RX multicast (no error)
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DSC_RX_MCH_HIT = 0x0008 ;RX multicast hit in hash table (no error)
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DSC_RX_MCH_HIT = 0x0008 ; RX multicast hit in hash table (no error)
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DSC_RX_MIDH_HIT = 0x0004 ;RX MID table hit (no error)
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DSC_RX_MIDH_HIT = 0x0004 ; RX MID table hit (no error)
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DSC_RX_IDX_MID_MASK = 3 ;RX mask for the index of matched MIDx
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DSC_RX_IDX_MID_MASK = 3 ; RX mask for the index of matched MIDx
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;PHY settings
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;PHY settings
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ICPLUS_PHY_ID = 0x0243
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ICPLUS_PHY_ID = 0x0243
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@ -224,7 +236,7 @@ proc START stdcall, state:dword
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.entry:
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.entry:
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DEBUGF 2,"Loading %s driver\n", my_service
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DEBUGF 2,"Loading driver\n"
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stdcall RegService, my_service, service_proc
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stdcall RegService, my_service, service_proc
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ret
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ret
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@ -415,7 +427,7 @@ ret
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align 4
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align 4
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probe:
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probe:
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DEBUGF 2,"Probing R6040 device\n"
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DEBUGF 1,"Probing R6040 device\n"
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PCI_make_bus_master
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PCI_make_bus_master
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@ -438,11 +450,11 @@ probe:
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or eax, dword [device.mac]
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or eax, dword [device.mac]
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test eax, eax
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test eax, eax
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jnz @f
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jnz @f
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DEBUGF 2, "ERROR: MAC address not initialized!\n"
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DEBUGF 2, "MAC address not initialized!\n"
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@@:
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@@:
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; Init RDC private data
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; Init RDC private data
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mov [device.mcr0], 0x1002
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mov [device.mcr0], MCR0_XMTEN or MCR0_RCVEN
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;mov [private.phy_addr], 1 ; Asper: Only one network card is supported now.
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;mov [private.phy_addr], 1 ; Asper: Only one network card is supported now.
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mov [device.switch_sig], 0
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mov [device.switch_sig], 0
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@ -463,7 +475,7 @@ probe:
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call init_rxbufs
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call init_rxbufs
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; Read the PHY ID
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; Read the PHY ID
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mov [device.phy_mode], 0x8000
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mov [device.phy_mode], MCR0_FD
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stdcall phy_read, 0, 2
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stdcall phy_read, 0, 2
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mov [device.switch_sig], ax
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mov [device.switch_sig], ax
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cmp ax, ICPLUS_PHY_ID
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cmp ax, ICPLUS_PHY_ID
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@ -513,7 +525,7 @@ probe:
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align 4
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align 4
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reset:
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reset:
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DEBUGF 2,"Resetting R6040\n"
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DEBUGF 1,"Resetting R6040\n"
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; Mask off Interrupt
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; Mask off Interrupt
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xor ax, ax
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xor ax, ax
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@ -525,11 +537,11 @@ reset:
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; attach int handler
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; attach int handler
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movzx eax, [device.irq_line]
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movzx eax, [device.irq_line]
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DEBUGF 2,"Attaching int handler to irq %x\n", eax:1
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DEBUGF 1,"Attaching int handler to irq %x\n", eax:1
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stdcall AttachIntHandler, eax, int_handler, dword 0
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stdcall AttachIntHandler, eax, int_handler, dword 0
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test eax, eax
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test eax, eax
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jnz @f
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jnz @f
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DEBUGF 2,"\nCould not attach int handler!\n"
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DEBUGF 2,"Could not attach int handler!\n"
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; or eax, -1
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; or eax, -1
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; ret
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; ret
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@@:
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@@:
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@ -600,9 +612,9 @@ reset:
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set_io MIER
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set_io MIER
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out dx, ax
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out dx, ax
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;Enable TX and RX
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;Enable RX
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mov ax, [device.mcr0]
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mov ax, [device.mcr0]
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or ax, 0x0002
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or ax, MCR0_RCVEN
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set_io 0
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set_io 0
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out dx, ax
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out dx, ax
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@ -670,9 +682,9 @@ init_rxbufs:
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.next_desc:
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.next_desc:
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mov [esi + x_head.ndesc], edx
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mov [esi + x_head.ndesc], edx
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push esi ecx
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push esi ecx edx
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stdcall KernelAlloc, MAX_BUF_SIZE
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stdcall KernelAlloc, MAX_BUF_SIZE
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pop ecx esi
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pop edx ecx esi
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mov [esi + x_head.skb_ptr], eax
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mov [esi + x_head.skb_ptr], eax
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GetRealAddr
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GetRealAddr
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@ -685,8 +697,7 @@ init_rxbufs:
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dec ecx
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dec ecx
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jnz .next_desc
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jnz .next_desc
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; complete the ring by linking the last to the first
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; complete the ring by linking the last to the first
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lea eax, [device.rx_ring]
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lea eax, [device.rx_ring]
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GetRealAddr
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GetRealAddr
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mov [device.rx_ring + x_head.sizeof*(RX_RING_SIZE - 1) + x_head.ndesc], eax
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mov [device.rx_ring + x_head.sizeof*(RX_RING_SIZE - 1) + x_head.ndesc], eax
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@ -751,9 +762,9 @@ phy_mode_chk:
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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align 4
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align 4
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transmit:
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transmit:
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DEBUGF 2,"\nTransmitting packet, buffer:%x, size:%u\n", [esp+4], [esp+8]
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DEBUGF 1,"Transmitting packet, buffer:%x, size:%u\n", [esp+4], [esp+8]
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mov eax, [esp+4]
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mov eax, [esp+4]
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DEBUGF 2,"To: %x-%x-%x-%x-%x-%x From: %x-%x-%x-%x-%x-%x Type:%x%x\n",\
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DEBUGF 1,"To: %x-%x-%x-%x-%x-%x From: %x-%x-%x-%x-%x-%x Type:%x%x\n",\
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[eax+00]:2,[eax+01]:2,[eax+02]:2,[eax+03]:2,[eax+04]:2,[eax+05]:2,\
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[eax+00]:2,[eax+01]:2,[eax+02]:2,[eax+03]:2,[eax+04]:2,[eax+05]:2,\
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[eax+06]:2,[eax+07]:2,[eax+08]:2,[eax+09]:2,[eax+10]:2,[eax+11]:2,\
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[eax+06]:2,[eax+07]:2,[eax+08]:2,[eax+09]:2,[eax+10]:2,[eax+11]:2,\
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[eax+13]:2,[eax+12]:2
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[eax+13]:2,[eax+12]:2
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@ -768,14 +779,13 @@ transmit:
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add edi, ebx
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add edi, ebx
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add edi, device.tx_ring - ebx
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add edi, device.tx_ring - ebx
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DEBUGF 2,"TX buffer status: 0x%x\n", [edi + x_head.status]:4
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DEBUGF 1,"TX buffer status: 0x%x\n", [edi + x_head.status]:4
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test [edi + x_head.status], DSC_OWNER_MAC ; check if buffer is available
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test [edi + x_head.status], DSC_OWNER_MAC ; check if buffer is available
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jnz .wait_to_send
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jnz .wait_to_send
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.do_send:
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.do_send:
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DEBUGF 1,"Sending now\n"
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DEBUGF 2,"Sending now\n"
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mov eax, [esp+4]
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mov eax, [esp+4]
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mov [edi + x_head.skb_ptr], eax
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mov [edi + x_head.skb_ptr], eax
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@ -805,7 +815,7 @@ transmit:
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||||||
.wait_to_send:
|
.wait_to_send:
|
||||||
|
|
||||||
DEBUGF 2,"Waiting for TX buffer\n"
|
DEBUGF 1,"Waiting for TX buffer\n"
|
||||||
|
|
||||||
call GetTimerTicks ; returns in eax
|
call GetTimerTicks ; returns in eax
|
||||||
lea edx, [eax + 100]
|
lea edx, [eax + 100]
|
||||||
@ -818,11 +828,11 @@ transmit:
|
|||||||
cmp edx, eax
|
cmp edx, eax
|
||||||
jb .l2
|
jb .l2
|
||||||
|
|
||||||
DEBUGF 1,"Send timeout\n"
|
DEBUGF 2,"Send timeout\n"
|
||||||
xor eax, eax
|
xor eax, eax
|
||||||
dec eax
|
dec eax
|
||||||
.fail:
|
.fail:
|
||||||
DEBUGF 1,"Send failed\n"
|
DEBUGF 2,"Send failed\n"
|
||||||
stdcall KernelFree, [esp+4]
|
stdcall KernelFree, [esp+4]
|
||||||
or eax, -1
|
or eax, -1
|
||||||
ret 8
|
ret 8
|
||||||
@ -842,7 +852,7 @@ int_handler:
|
|||||||
|
|
||||||
push ebx esi edi
|
push ebx esi edi
|
||||||
|
|
||||||
DEBUGF 1,"\n%s int\n", my_service
|
DEBUGF 1,"int\n"
|
||||||
|
|
||||||
; Find pointer of device wich made IRQ occur
|
; Find pointer of device wich made IRQ occur
|
||||||
|
|
||||||
@ -874,11 +884,11 @@ int_handler:
|
|||||||
|
|
||||||
.got_it:
|
.got_it:
|
||||||
|
|
||||||
DEBUGF 1,"Device: %x Status: %x ", ebx, ax
|
DEBUGF 1,"Device: %x Status: %x\n", ebx, ax
|
||||||
|
|
||||||
push ax
|
push ax
|
||||||
|
|
||||||
test word [esp], RX_FINISH
|
test word[esp], RX_FINISH
|
||||||
jz .no_RX
|
jz .no_RX
|
||||||
|
|
||||||
push ebx
|
push ebx
|
||||||
@ -886,45 +896,40 @@ int_handler:
|
|||||||
pop ebx
|
pop ebx
|
||||||
|
|
||||||
; Find the current RX descriptor
|
; Find the current RX descriptor
|
||||||
|
|
||||||
movzx edx, [device.cur_rx]
|
movzx edx, [device.cur_rx]
|
||||||
shl edx, 5
|
shl edx, 5
|
||||||
lea edx, [device.rx_ring + edx]
|
lea edx, [device.rx_ring + edx]
|
||||||
|
|
||||||
; Check the descriptor status
|
; Check the descriptor status
|
||||||
|
|
||||||
mov cx, [edx + x_head.status]
|
mov cx, [edx + x_head.status]
|
||||||
test cx, DSC_OWNER_MAC
|
test cx, DSC_OWNER_MAC
|
||||||
jnz .no_RX
|
jnz .no_RX
|
||||||
|
|
||||||
DEBUGF 2,"packet status=0x%x\n", cx
|
DEBUGF 1,"packet status=0x%x\n", cx
|
||||||
|
|
||||||
test cx, DSC_RX_ERR ; Global error status set
|
test cx, DSC_RX_ERR ; Global error status set
|
||||||
jnz .no_RX
|
jnz .no_RX
|
||||||
|
|
||||||
; Packet successfully received
|
; Packet successfully received
|
||||||
|
|
||||||
movzx ecx, [edx + x_head.len]
|
movzx ecx, [edx + x_head.len]
|
||||||
and ecx, 0xFFF
|
and ecx, 0xFFF
|
||||||
sub ecx, 4 ; Do not count the CRC
|
sub ecx, 4 ; Do not count the CRC
|
||||||
|
|
||||||
; Update stats
|
; Update stats
|
||||||
add dword [device.bytes_rx], ecx
|
add dword[device.bytes_rx], ecx
|
||||||
adc dword [device.bytes_rx + 4], 0
|
adc dword[device.bytes_rx + 4], 0
|
||||||
inc dword [device.packets_rx]
|
inc dword[device.packets_rx]
|
||||||
|
|
||||||
; Push packet size and pointer, kernel will need it..
|
; Push packet size and pointer, kernel will need it..
|
||||||
|
|
||||||
push ebx
|
push ebx
|
||||||
push .more_RX
|
push .more_RX
|
||||||
|
|
||||||
push ecx
|
push ecx
|
||||||
push [edx + x_head.skb_ptr]
|
push [edx + x_head.skb_ptr]
|
||||||
|
|
||||||
DEBUGF 2,"packet ptr=0x%x\n", [edx + x_head.skb_ptr]
|
DEBUGF 1,"packet ptr=0x%x\n", [edx + x_head.skb_ptr]
|
||||||
|
|
||||||
; reset the RX descriptor
|
; reset the RX descriptor
|
||||||
|
|
||||||
push edx
|
push edx
|
||||||
stdcall KernelAlloc, MAX_BUF_SIZE
|
stdcall KernelAlloc, MAX_BUF_SIZE
|
||||||
pop edx
|
pop edx
|
||||||
@ -934,18 +939,16 @@ int_handler:
|
|||||||
mov [edx + x_head.status], DSC_OWNER_MAC
|
mov [edx + x_head.status], DSC_OWNER_MAC
|
||||||
|
|
||||||
; Use next descriptor next time
|
; Use next descriptor next time
|
||||||
|
|
||||||
inc [device.cur_rx]
|
inc [device.cur_rx]
|
||||||
and [device.cur_rx], RX_RING_SIZE - 1
|
and [device.cur_rx], RX_RING_SIZE - 1
|
||||||
|
|
||||||
; At last, send packet to kernel
|
; At last, send packet to kernel
|
||||||
|
|
||||||
jmp Eth_input
|
jmp Eth_input
|
||||||
|
|
||||||
|
|
||||||
.no_RX:
|
.no_RX:
|
||||||
|
|
||||||
test word [esp], TX_FINISH
|
test word[esp], TX_FINISH
|
||||||
jz .no_TX
|
jz .no_TX
|
||||||
|
|
||||||
.loop_tx:
|
.loop_tx:
|
||||||
@ -959,7 +962,7 @@ int_handler:
|
|||||||
cmp [edi + x_head.skb_ptr], 0
|
cmp [edi + x_head.skb_ptr], 0
|
||||||
je .no_TX
|
je .no_TX
|
||||||
|
|
||||||
DEBUGF 2,"Freeing buffer 0x%x\n", [edi + x_head.skb_ptr]
|
DEBUGF 1,"Freeing buffer 0x%x\n", [edi + x_head.skb_ptr]
|
||||||
|
|
||||||
push [edi + x_head.skb_ptr]
|
push [edi + x_head.skb_ptr]
|
||||||
mov [edi + x_head.skb_ptr], 0
|
mov [edi + x_head.skb_ptr], 0
|
||||||
@ -971,6 +974,42 @@ int_handler:
|
|||||||
jmp .loop_tx
|
jmp .loop_tx
|
||||||
|
|
||||||
.no_TX:
|
.no_TX:
|
||||||
|
test word[esp], RX_NO_DESC
|
||||||
|
jz .no_rxdesc
|
||||||
|
|
||||||
|
DEBUGF 2, "No more RX descriptors!\n"
|
||||||
|
|
||||||
|
.no_rxdesc:
|
||||||
|
test word[esp], RX_FIFO_FULL
|
||||||
|
jz .no_rxfifo
|
||||||
|
|
||||||
|
DEBUGF 2, "RX FIFO full!\n"
|
||||||
|
|
||||||
|
.no_rxfifo:
|
||||||
|
test word[esp], RX_EARLY
|
||||||
|
jz .no_rxearly
|
||||||
|
|
||||||
|
DEBUGF 1, "RX early\n"
|
||||||
|
|
||||||
|
.no_rxearly:
|
||||||
|
test word[esp], TX_EARLY
|
||||||
|
jz .no_txearly
|
||||||
|
|
||||||
|
DEBUGF 1, "TX early\n"
|
||||||
|
|
||||||
|
.no_txearly:
|
||||||
|
test word[esp], EVENT_OVRFL
|
||||||
|
jz .no_ovrfl
|
||||||
|
|
||||||
|
DEBUGF 2, "Event counter overflow!\n"
|
||||||
|
|
||||||
|
.no_ovrfl:
|
||||||
|
test word[esp], LINK_CHANGED
|
||||||
|
jz .no_link
|
||||||
|
|
||||||
|
DEBUGF 1, "Link changed\n"
|
||||||
|
|
||||||
|
.no_link:
|
||||||
pop ax
|
pop ax
|
||||||
|
|
||||||
pop edi esi ebx
|
pop edi esi ebx
|
||||||
@ -983,7 +1022,7 @@ int_handler:
|
|||||||
align 4
|
align 4
|
||||||
init_mac_regs:
|
init_mac_regs:
|
||||||
|
|
||||||
DEBUGF 2,"initializing MAC regs\n"
|
DEBUGF 1,"initializing MAC regs\n"
|
||||||
|
|
||||||
; MAC operation register
|
; MAC operation register
|
||||||
mov ax, 1
|
mov ax, 1
|
||||||
@ -1012,7 +1051,7 @@ init_mac_regs:
|
|||||||
align 4
|
align 4
|
||||||
proc phy_read stdcall, phy_addr:dword, reg:dword
|
proc phy_read stdcall, phy_addr:dword, reg:dword
|
||||||
|
|
||||||
DEBUGF 2,"PHY read, addr=0x%x reg=0x%x\n", [phy_addr]:8, [reg]:8
|
DEBUGF 1,"PHY read, addr=0x%x reg=0x%x\n", [phy_addr]:8, [reg]:8
|
||||||
|
|
||||||
mov eax, [phy_addr]
|
mov eax, [phy_addr]
|
||||||
shl eax, 8
|
shl eax, 8
|
||||||
@ -1036,7 +1075,7 @@ proc phy_read stdcall, phy_addr:dword, reg:dword
|
|||||||
in ax, dx
|
in ax, dx
|
||||||
and eax, 0xFFFF
|
and eax, 0xFFFF
|
||||||
|
|
||||||
DEBUGF 2,"PHY read, val=0x%x\n", eax:4
|
DEBUGF 1,"PHY read, val=0x%x\n", eax:4
|
||||||
|
|
||||||
ret
|
ret
|
||||||
|
|
||||||
@ -1050,7 +1089,7 @@ endp
|
|||||||
align 4
|
align 4
|
||||||
proc phy_write stdcall, phy_addr:dword, reg:dword, val:dword
|
proc phy_write stdcall, phy_addr:dword, reg:dword, val:dword
|
||||||
|
|
||||||
DEBUGF 2,"PHY write, addr=0x%x reg=0x%x val=0x%x\n", [phy_addr]:8, [reg]:8, [val]:8
|
DEBUGF 1,"PHY write, addr=0x%x reg=0x%x val=0x%x\n", [phy_addr]:8, [reg]:8, [val]:8
|
||||||
|
|
||||||
mov eax, [val]
|
mov eax, [val]
|
||||||
set_io 0
|
set_io 0
|
||||||
@ -1076,7 +1115,7 @@ proc phy_write stdcall, phy_addr:dword, reg:dword, val:dword
|
|||||||
jnz .write
|
jnz .write
|
||||||
@@:
|
@@:
|
||||||
|
|
||||||
DEBUGF 2,"PHY write ok\n"
|
DEBUGF 1,"PHY write ok\n"
|
||||||
|
|
||||||
ret
|
ret
|
||||||
endp
|
endp
|
||||||
@ -1086,7 +1125,7 @@ endp
|
|||||||
align 4
|
align 4
|
||||||
read_mac:
|
read_mac:
|
||||||
|
|
||||||
DEBUGF 2,"Reading MAC: "
|
DEBUGF 1,"Reading MAC: "
|
||||||
|
|
||||||
mov cx, 3
|
mov cx, 3
|
||||||
lea edi, [device.mac]
|
lea edi, [device.mac]
|
||||||
@ -1100,7 +1139,7 @@ read_mac:
|
|||||||
dec cx
|
dec cx
|
||||||
jnz .mac
|
jnz .mac
|
||||||
|
|
||||||
DEBUGF 2,"%x-%x-%x-%x-%x-%x\n",[edi-6]:2, [edi-5]:2, [edi-4]:2, [edi-3]:2, [edi-2]:2, [edi-1]:2
|
DEBUGF 1,"%x-%x-%x-%x-%x-%x\n",[edi-6]:2, [edi-5]:2, [edi-4]:2, [edi-3]:2, [edi-2]:2, [edi-1]:2
|
||||||
|
|
||||||
ret
|
ret
|
||||||
|
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user